JPS60257674A - Broad band gamma correction circuit - Google Patents

Broad band gamma correction circuit

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Publication number
JPS60257674A
JPS60257674A JP59114118A JP11411884A JPS60257674A JP S60257674 A JPS60257674 A JP S60257674A JP 59114118 A JP59114118 A JP 59114118A JP 11411884 A JP11411884 A JP 11411884A JP S60257674 A JPS60257674 A JP S60257674A
Authority
JP
Japan
Prior art keywords
characteristic
gamma
current
correction circuit
gamma correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59114118A
Other languages
Japanese (ja)
Inventor
Tatsuo Nagasaki
達夫 長崎
Hiroyoshi Fujimori
弘善 藤森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Corp
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Corp, Olympus Optical Co Ltd filed Critical Olympus Corp
Priority to JP59114118A priority Critical patent/JPS60257674A/en
Publication of JPS60257674A publication Critical patent/JPS60257674A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To realize a gamma correction circuit having a broad band characteristic to be reproduced at a correct gradation by using a current switch comprising a differential amplifier provided with a required limiter characteristic to form the gamma characteristic. CONSTITUTION:A couple of transistors Qi, Qi' (i=1, 2, 3) formed in the circuit constitution of a differential amplifier require arranged characteristics in current switches 12A, 12B, 12C and arranged resistance value and temperature coefficient are used for a couple of emitter resistors REi, REi'. In setting properly amplification factors a1, a2, a3 of the current switches 12A, 12B, 12C, the input characteristic is similar to the desired gamma characteristic curve.

Description

【発明の詳細な説明】 [発明の技術分野1 本発明は被写体の画像を忠実に再現Jるための広−11
域ガンマ補H回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention 1] The present invention provides a method for faithfully reproducing an image of a subject
This relates to a range gamma correction H circuit.

[発明の技術的背與どその問題点] =・般(J、被写体の階調を正しく再現するためには)
コン−カメラから最終のカラーブラウン管等の表示装置
で表示されるまでのシスデ仝体の総合特性のガンマを1
にすることが必要どされる。今、被写体の輝度を横!+
I11にとり、再生画像の輝度を縦軸にどって、イれぞ
れ対応点を両対数目盛り′c1[1ツトした揚台、その
ブロワl〜したものが横軸と45度4rリ−直線どなる
場合がガンマくγ)1の叩想的なシスjムど4【る。
[Technical background of the invention and its problems] =・General (J, In order to correctly reproduce the gradation of the subject)
- The gamma of the overall characteristics of the system body from the camera to the final display device such as a color cathode ray tube is set to 1.
It is necessary to do so. Now, change the brightness of the subject horizontally! +
For I11, the brightness of the reproduced image is plotted along the vertical axis, and the respective corresponding points are plotted on the logarithmic scale 'c1'. The case is gamma γ) 1's contemplative system d4.

ところて゛、カラーカメラに広く用いられている踊像管
の光電変換特性(ガンマ特性)は、例えばビジ」ンCは
0.6−0.7.リーチコン及びカル二二」ンでは約1
というように、それぞれ異っている。一方、カラーブラ
ウン管の蛍光面の発光輝度も、直線的でなく、そのガン
マ特+!lは約2.2程度である。従って−、システム
全体の総合γ特性を1にザるためには、回路的にガンマ
補正を行わなりればならない。この場合、酋遍性をfJ
lこせるIこめ、ガンマ補j[はカメラ側で行うように
定められている。
However, the photoelectric conversion characteristics (gamma characteristics) of the image tube widely used in color cameras are, for example, 0.6-0.7 for Visin C. Approximately 1 for Reachcon and Karini
As you can see, each one is different. On the other hand, the luminance of the phosphor screen of a color cathode ray tube is not linear, and its gamma characteristic is +! l is about 2.2. Therefore, in order to reduce the overall gamma characteristic of the entire system to 1, it is necessary to perform gamma correction using a circuit. In this case, the permissiveness is fJ
It is specified that the correction and gamma correction should be performed on the camera side.

上記シス7ムの総合ガンマをγ、カラーブラウン管のガ
ンマをγl、ビジ]ンのガンマを72゜補正回路のガン
マをT3どづるど、 T−γ1 T2・γ3 どなり、γ3・−・1/′γ1 ・γ2となるようにガ
ンマ補正回路て補iIするようにしでいる。
The overall gamma of the system 7 system is γ, the gamma of the color cathode ray tube is γl, the gamma of the visual tube is 72°, and the gamma of the correction circuit is T3. A gamma correction circuit is used to compensate iI so that γ1 and γ2.

従来のガンマ補正回路は、第1図に示・ノように1〜ラ
ンジスタ1Rの出力側に設りたそれぞれ異るバイアス電
源[−1にそれぞれ直列にダイオードD1及び抵抗r1
 (1−・1,2.3)を接続し、各タイオー1〜D1
が出力信号レベルに応じ(−順次導通して合成抵抗値が
([を下し、それにつれて増幅度を折れ線状に可変して
総合ガンマ特性が1になるようにガンマ補正していた。
The conventional gamma correction circuit has a diode D1 and a resistor r1 connected in series to different bias power supplies [-1], respectively, which are installed on the output sides of transistors 1 to 1R, as shown in FIG.
Connect (1-・1, 2.3) and each Taioh 1 to D1
is sequentially turned on according to the output signal level (-), and the combined resistance value ([ is lowered, and the amplification degree is varied in a polygonal manner accordingly to perform gamma correction so that the total gamma characteristic becomes 1.

1記従来例は、ダイオードを用いているため、第2図に
示t J、うに同図(a)のようイ【幅がtPのパルス
が同図(b )のダイオードDに入力されると、ぞの出
力パルスは同図(C)で承りようになり、人力パルス−
C逆バイアスにされでも、順り内時の電荷が中和される
までの逆回復り間(リカバリータイム)11.たり、応
答がイれ、変化の速い信号に対−リ−る応答待+1が悪
化する。
1. The conventional example uses a diode, so when a pulse with a width tP is input to the diode D shown in FIG. 2, tJ is shown in FIG. , the output pulse is shown in the same figure (C), and the manual pulse
C Reverse recovery time (recovery time) until the charge is neutralized even when reverse biased 11. or the response is lost, and the response time +1 for rapidly changing signals worsens.

又、し・ランジスクについても、第3図(a>に示す幅
IPの人力パルスが同図(b)に示づトランジスタT 
Rのベースに入力されると、そのコレクタ出力波形は同
図(C)となり、入力パルスがなくなっても接合付近の
電荷がぬりるJ、での蓄積時間Lstgだり応答が遅く
なる。
Also, regarding Shiranjisku, when the manual pulse of width IP shown in Fig. 3 (a) is applied to the transistor T shown in Fig. 3 (b),
When it is input to the base of R, its collector output waveform becomes as shown in FIG. 3(C), and even if the input pulse disappears, the charge near the junction spreads, resulting in a slow accumulation time Lstg and a slow response.

従って、上記従来例では応答待fj1が低いので、被写
体の微細な部分の色あいあるいは]ン1ヘラスト等を正
しい階調で再現づることができなくなる。
Therefore, in the conventional example described above, since the response time fj1 is low, it is impossible to reproduce the color tone of minute parts of the subject or the gray scale of the subject with correct gradation.

又、近年固体搬像素子を搬像手段に用いたカラーカメラ
とか内視鏡が提案されている。特に内視鏡においては、
特願昭58−18 ’I 683号にあるように最も小
型化できるライン転送方式の固体撮像素子が適している
。しかしながらこのライン転送方式の固体撮像素子は、
感光部(受光部)と転送部とが共用されるので、1最像
しI〔画素に対応した電荷信号を読み出すために、り[
]ツクパルスを印加してその出力端に転送を行っている
時にはスミア現象を防+L する必要士、踊像(照明)
を行えない。つまり照明期間(受光蓄積期間)の合い間
の短い時間内に信号処理回路側に搬像した信号の読み出
しを行わなければならない。これ(31,1−2照明期
間が短くなると、暗く−C]ン1〜ラストの低い像にな
るのて、この照明1g1間が人さく、11つ時間的に遅
れの少い像を得るために(よ、信号の読み出しh間を’
J、Cr < シて、その短い時間内に烏速磨で読み出
りことが必要となるからである。この場合映像信号t)
でれに伴って当然広帯域(0〜10M1−12)と41
つ、被写体を忠実に再現り−るに【、1応答特f1−の
=く周波数特性)の良好なガンマ補iト回路が必要とな
る。
Furthermore, in recent years, color cameras and endoscopes using solid-state image carriers as image carriers have been proposed. Especially in endoscopy,
As disclosed in Japanese Patent Application No. 58-18'I683, a line transfer type solid-state image pickup device that can be made most compact is suitable. However, this line transfer type solid-state image sensor
Since the photosensitive section (light receiving section) and the transfer section are shared, it is necessary to read out the charge signal corresponding to each pixel.
] It is necessary to prevent the smear phenomenon when applying a pulse pulse and transmitting data to its output terminal.
I can't do it. In other words, the signal transferred to the signal processing circuit side must be read out within a short period of time between illumination periods (light reception and accumulation periods). (31, 1-2 When the illumination period is shortened, the image becomes dark and low -C]n1~last, so this illumination 1g1 interval is crowded and 11 to obtain an image with less time delay. (The signal readout interval is
This is because J, Cr < , it is necessary to read out the data within such a short period of time. In this case, the video signal t)
Of course, along with this, wideband (0-10M1-12) and 41
In order to faithfully reproduce the subject, a gamma compensation circuit with good frequency characteristics is required.

[発明の目的1 本発明は上述した点にか/υがみてなされたもので、応
答qlr性が良好で、被写体を微細な部位まで止しい階
調で再現可能どする広帯域カンマ補f「回路を提供づる
ことを目的とり−る。
[Objective of the Invention 1] The present invention has been made in view of the above-mentioned points, and provides a wide-band comma correction circuit that has good response QLR characteristics and is capable of reproducing the subject with precise gradation down to minute parts. The purpose is to provide the following.

[発明の概要] 本発明は差動増幅器で形成し1=電流スイツチを複数用
いてガンマ補正回路を構成づ−ることによって、広帯域
の周波数に対して十分応答し1する応答特性を実現しで
、正しい階調の像を再生η・きるようにいる。又、差動
増幅器を用いて構成することによって、殆んど温度に影
響されることのない侵れた特f1を実現しでいる。
[Summary of the Invention] The present invention is capable of realizing a response characteristic of 1 that sufficiently responds to a wide band of frequencies by configuring a gamma correction circuit using a plurality of differential amplifiers and current switches. , it is possible to reproduce an image with the correct gradation. Furthermore, by using a differential amplifier, it is possible to realize a characteristic f1 that is almost unaffected by temperature.

[発明の実施例1 以上、図面を参照して本発明を具体的に説明づる。[Embodiment 1 of the invention The present invention will now be described in detail with reference to the drawings.

第4図ないし第7図は本発明の第1実施例に係り、第4
図は第1実施例の基本構成を示し、第5図は第4図の第
1実施例を形成する差動増幅器を示し、第6図(a)は
第1実施例を形成づる各差動増幅器の入出力特性を示し
、同図(b)は第1実施例の入出力特性を示し、第7図
は第1実施例の具体的回路構成を示1゜ 第1実施例のカンマ補正回路11 !;L、差動11つ
幅器で形成されたカレントスイッチ12△、12B。
4 to 7 relate to the first embodiment of the present invention, and FIG.
The figure shows the basic configuration of the first embodiment, FIG. 5 shows the differential amplifier forming the first embodiment of FIG. 4, and FIG. 6(a) shows each differential amplifier forming the first embodiment. The input/output characteristics of the amplifier are shown, and FIG. 7(b) shows the input/output characteristics of the first embodiment, and FIG. 7 shows the specific circuit configuration of the first embodiment.1゜Comma correction circuit of the first embodiment 11! ;L, current switch 12Δ, 12B formed by differential 11 width switch;

12Cと、これらカレントスイッV−12A、12B、
12Cの出力を加算【ノC出力り−る加算器13どから
構成されている。
12C, these current switches V-12A, 12B,
It consists of an adder 13 that adds the outputs of 12C.

上記ノjレン1〜スイッヂ12△、12B、12Gは、
それぞれ第5図に示すように差動増幅器で構成されてい
る。
The above Nojren 1 to Switch 12△, 12B, 12G are as follows:
Each of them is composed of a differential amplifier as shown in FIG.

即し、特性の揃った1対のNPN型1〜ランジス夕Q、
Q−はぞれそれの1ミツタか抵抗Rc 、 R[−を介
してJI、油化され、定電流源Iに接続されている。
Therefore, a pair of NPN types 1 to Rungis Q with uniform characteristics,
Q- is connected to constant current source I through its respective resistors Rc and R[-.

各ベースはぞれぞれ抵抗r<、r<−を介して一方が入
力端V1に、他方は接地され(−いる。又、各コレクタ
は一方が正の給電端−IVに接続され、他力かその出力
端V oどされると共に、(〕荷低抵抗1−を介して正
の給電Da −1−Vに接続されでいる。尚、両トラン
ジスタQ、Q’″は負荷抵抗1又1 が一方のみに設(
Jてあり、非対称であるので準差動増幅器と61pPば
れることがあるが、本発明にJ3いては差動増幅器と呼
ぶ。
One side of each base is connected to the input terminal V1 and the other is grounded (-) through resistors r<, r<-, respectively. Also, one side of each collector is connected to the positive power supply terminal -IV, and the other The output terminal V o is connected to the positive power supply Da -1-V via the load resistor 1-. Note that both transistors Q and Q''' are connected to the load resistor 1 or 1 is set only on one side (
J3 is asymmetrical, so it is sometimes called a semi-differential amplifier, but in the present invention, J3 is called a differential amplifier.

]−記差動増幅器は、入力端■1に印加される信号が他
方のベース電位より6高り4ヨると、そのレベルに応じ
C−プjの1〜ランジスタQのコレクタ・エミッタ間に
電流か流れ、それに1芯じて他方の1−ランジスタQ′
を流れる電流が減少しく出力端VOの出力レベルが増大
づる。しかして、コレクタ・J−ミッタ間に流れる7f
i流(よ定電流源Iによって規定される電流が上限どな
り、出力レベルはそれ以上流れない′4に態に保持され
、−てのAンしCいるトランジスタQは飽和状態にi!
 L ’Jい−(、能動状態で動作Jるのて、蓄積時間
が小さく、超高速動作にも応答でさるようになっている
。この入出力特性はぞの抵抗RE 、RE ’、RLに
応じて第6図(a)に示!jようにリミットされる1l
ftまで略りニアに増加し、折れ曲がる折れ線状の特性
どなる。
] - When the signal applied to the input terminal 1 becomes 6 higher than the other base potential, the differential amplifier generates a signal between the collector and emitter of transistor Q and transistor Q according to the level. A current flows, and one core is connected to the other transistor Q'.
As the current flowing through the output terminal VO decreases, the output level at the output terminal VO increases. Therefore, 7f flowing between the collector and J-mitter
The current defined by the constant current source I reaches its upper limit, and the output level is held at a state where no further flow occurs, and the transistor Q between A and C becomes saturated.
Since it operates in the active state, the storage time is short and it responds well to ultra-high-speed operation.This input/output characteristic is determined by the resistances RE, RE', and RL. Accordingly, 1l is limited as shown in Figure 6(a)!
It increases approximately near to ft and has a curved line-like characteristic.

又、上記特性の揃った1対の1−ランジスタQ、Q′を
用いることによって、各1〜ランジスクQ、Q−の湿度
依存性が相殺されて、殆/υど流電に影響されないで・
安定性の良いカレントスイップどして機能りるようにし
である。又、カレン1〜スイツヂCきる。
In addition, by using a pair of 1-transistors Q and Q' with the same characteristics as described above, the humidity dependence of each 1-transistor Q and Q- is canceled out, so that it is almost unaffected by current current.
It is a stable current sweep that works well. Also, Karen 1~Suitsuji C is Kiru.

第7図に示づ第1実施例の具体的回路においては、各カ
レン1〜スイツヂ12△、12B、42Cは第5図に示
1差動増幅器の回路構成にて形成されている。各差動増
幅器を形成づ゛るそれぞれ1ス・1のトランジスタQi
 、Qi ” (!=1.2.3)1;1お!jいに特
++の揃ったbのが用いられ、各1対の丁ミッタ抵抗R
Fi 、 R1,i −らモの値及び温度係数等の揃つ
Iこものを用いることによ−)て、温庶に殆/υど影響
されないようになっている1、尚、各カレントスイップ
−12Δ、128.12Gの負荷抵抗Rl−L;L共通
化され、この抵抗R1−で電流加算を行い、その出力端
から加算されたイ1−18が出力されるようにな−)−
〇いる。
In the specific circuit of the first embodiment shown in FIG. 7, each of the currents 1 to 12Δ, 12B, and 42C is formed with the circuit configuration of a differential amplifier shown in FIG. One transistor Qi forming each differential amplifier
, Qi ” (!=1.2.3)1;
Fi, R1, i - By using I-components with the same values and temperature coefficients, etc., it is almost unaffected by temperature. Ip -12Δ, 128.12G load resistance Rl-L;L is shared, current is added by this resistor R1-, and the added value I1-18 is output from its output terminal -)-
Yes, there is.

十記各カレン1〜スイッチ12△、12B、120の増
幅度を第4図あるいは第6図(a)に示すよう【1ニイ
れぞれal、a2.a3どし、これらを加算しlこ構成
の第1実施例の入力出力特性は第6図(b)に示づにう
になるので座標(XI 、Y+ )、(X2.Y> >
、(X3 、Y3 )で屈曲させて、所望とづるガンマ
特性曲線に近似させる場合には、同図り日ら次の関係式 %式% が成りfL一つ。この連立方程式を解くと、a+ = 
(XI Y2−X;+ Y+ )/ (XI(XI−X
2 )) a7 = ((X2−X3 )Y+ −(XI −X:
l ) Y2 ト (XI −−X 2 ) Y3 )
/ ((XI −X2 ) (X2 −X3 ))a3
− (Y2−Y3 )/(X2− ×3 )となり、各
差動増幅器の増幅度a(、a2.a3を上式を満たづよ
うに設定づ−ることによって、略所望ど号るカンマ特性
の゛ものを実現できる。
As shown in FIG. 4 or FIG. 6(a), the amplification degrees of the switches 1 to 12A, 12B, and 120 are as shown in FIG. a3, and these are added, and the input/output characteristics of the first embodiment with this configuration are as shown in FIG. 6(b), so the coordinates (XI, Y+), (X2.Y>>
, (X3, Y3) to approximate the desired gamma characteristic curve, the following relational expression % formula % holds true. Solving this simultaneous equation gives a+ =
(XI Y2-X; + Y+ )/ (XI(XI-X
2)) a7 = ((X2-X3)Y+ -(XI-X:
l) Y2 (XI --X2) Y3)
/ ((XI -X2) (X2 -X3))a3
- (Y2 - Y3)/(X2 - You can achieve anything.

らなみに各差動増幅器の増幅度al、al、83は近似
的に8 + =RL/Re + 、a2=RL 11’
<e2.a:+−Iく1./Re 3と表わされ、リミ
ッタレベルa1 ・×1.a2 ・×2.a3 ・×3
(ま各差動増幅器の電流源をIt、12.13どすると
、al ′X+ =RL 01+ 、a2 °X2 =
Rt・+2 、a3 ・X3−RL−13からめられる
Incidentally, the amplification degree al, al, 83 of each differential amplifier is approximately 8 + =RL/Re + , a2 = RL 11'
<e2. a:+-Iku1. /Re 3, and the limiter level a1 ・×1. a2 ・×2. a3 ・×3
(If the current source of each differential amplifier is It, 12.13, al 'X+ = RL 01+ , a2 °X2 =
Rt・+2, a3・X3-RL-13 are intertwined.

尚、上記抵抗ROi は(REi−R−Ei より)R
e’ i −2R[E i である。
The above resistance ROi is (from REi-R-Ei) R
e' i -2R[E i .

第8図は本発明の第2実施例を示す。FIG. 8 shows a second embodiment of the invention.

この第2実施例は、第7図に承り−1記第1実施例に4
3いて、その出力端が各カレントスイッチ中−12△、
128.120の出力端と並列接続点になる構成にしイ
【いで、ベース接地のバラノア増幅用]・ランジスタ0
4をカスケードに接続しである。
This second embodiment is based on FIG.
3, and its output terminal is -12△ in each current switch,
128. Configure it to be a parallel connection point with the output end of 120 [For base-grounded Balanoa amplification] ・Lanister 0
4 are connected in cascade.

この]ヘランジスタQ4をカスケードに接続して、各カ
レン1−スイッチ12A、12B、12Cの増幅度に依
存してその拡散容量が等価的に増大するミシー効果によ
って、周波数特性が劣化す゛るのを防ぎ、より広1) 
11i化さUである。
This ] helangistor Q4 is connected in cascade to prevent the frequency characteristics from deteriorating due to the Missy effect in which the diffusion capacitance thereof equivalently increases depending on the amplification degree of each Karen 1-switch 12A, 12B, 12C, Wider1)
11i U.

尚、第7図に示づカレントスイッチ12△、12B、1
2Cのそれぞれ差動の負荷側にベース接地の1ヘランジ
スタを接続してそれぞれ差動型のバッファを形成し、各
カレントスイッチ12△、12B、12Cのミラー効果
をそれぞれ小さくして、共通の負荷抵抗でRLで電流加
粋する構造にしても良い。
In addition, the current switches 12△, 12B, 1 shown in FIG.
A common-base 1H transistor is connected to each differential load side of 2C to form a differential type buffer, and the mirror effect of each current switch 12△, 12B, and 12C is reduced, and a common load resistance is It is also possible to have a structure in which the current is added at RL.

尚、子連のカレントスイッチ12Δ、12B。In addition, the child series current switches 12Δ, 12B.

12Cの数を増ぜば、折線の数を増大でき、望ましいガ
ン7特性により近づ(〕ることができる。又、ダイナミ
ックレンジを広くできる。
By increasing the number of 12Cs, the number of broken lines can be increased, and the desired gun 7 characteristics can be approached. Also, the dynamic range can be widened.

尚、上述の各実施例にJ5いては、ぞれぞれのカレン1
−スイッチ12Δ、12B、12Gの出力を加算してい
るが、対となる1〜ランジスタ(例えばQ2.Q2−)
のコレクタを入り換えて(又はベース側を入れ変えて)
接続して、仝C加算としないで、減算もt+−:>で所
望とづるガン7特性を得るようにりることbできる。
In addition, in each of the above-mentioned examples, each Karen 1
- The outputs of switches 12Δ, 12B, and 12G are added, but the paired 1 to transistors (e.g. Q2, Q2-)
Replace the collector (or replace the base side)
By connecting, subtraction can also be performed to obtain the desired gun 7 characteristics with t+-:> instead of addition.

尚、バイポーラ1〜ランジスタでなく電界効果型1ヘラ
ンジスタ等Cカレン1−スイッチを形成しても良い。
Note that a C-current 1-switch such as a field effect type 1-transistor may be formed instead of a bipolar 1-transistor.

さらに、入力111号を(必要に応じCレベルシフ1〜
手段を用いる)定電流源を形成1−るl〜ランジスタの
ベースあるい(まグー1〜等の制W端に印加して、その
電流を可変さ支去ることをイ]加りる等して乗粋(ある
いは除り)的特性を持たせC所望のガンマ特性を実現り
−ることもできる。
Furthermore, input No. 111 (C level shift 1 to
Form a constant current source (by applying it to the base of the transistor or the control end of the resistor, etc., and apply a variable current to it). It is also possible to achieve a desired gamma characteristic by giving a characteristic (or subtractive) characteristic.

[発明の効果1 以ト述べたように本発明にJ:れば、ガンマ特性をそれ
ぞれ所要のリミッタ特性を持!こせた差動増幅器で構成
したカレン1へスイッチを用い−C形成しであるので、
応答が速く、正しい階調で再41てきる広帯域特性を右
りるガンマ補正回路を実現C′きる。又、温度に)[右
されることのなく、さらにダイナミックレンジの広いガ
ンマ補正回路を実現できる。
[Effect of the Invention 1] As described above, if the present invention is applied, each gamma characteristic has the required limiter characteristic! Since -C is formed using a switch to Karen 1, which is made up of a differential amplifier,
It is possible to realize a gamma correction circuit that has a wide band characteristic that has a fast response and can reproduce the correct gradation. In addition, it is possible to realize a gamma correction circuit with a wider dynamic range without being affected by temperature.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第3図は従来例に係り、第1図41従来例
を承り一回路図、第2図は第1図に用いられているタイ
オードのスイップーング特f1を示りlζめの説明図、
第3図は第1図に用いられているトランジスタのスイッ
ヂング特f!]を示すための特性図、第4図ないし第7
図は本発明の第′1実施例に係り、第4図1.−L第1
実施例の基本構成を示づ回路図、第5図(31各カレン
トスイップーの構成を示1回路図、第6図< a > 
t;を各カレン1へスイッチの入出カ特性を示ゴー特性
図、第6図(b)4よ第1実施例の入出力特性を示す特
性図、第7図は第1実施例の具体的構成を示づ回路図、
第8図は本発明の第2実施例を示す回路図である。 11・・・ガン7?1ti正回路 12△、1211,12C・・カレンl−スイッチ1;
3・・・加Q器 1・・・定電流源Q、に)”・・・1
〜ランジスタ 1<1−・・・f+荷抵抗\ゝ−1//
Figures 1 to 3 relate to conventional examples, Figure 1 is a circuit diagram based on the conventional example, and Figure 2 is an explanatory diagram showing the switching characteristic f1 of the diode used in Figure 1. ,
Figure 3 shows the switching characteristics f! of the transistor used in Figure 1. ] Characteristic diagrams, Figures 4 to 7
The figure relates to the '1st embodiment of the present invention, and is shown in FIG. -L 1st
A circuit diagram showing the basic configuration of the embodiment, Fig. 5 (31) A circuit diagram showing the configuration of each current sweep, Fig. 6 <a>
Figure 6(b) 4 is a characteristic diagram showing the input/output characteristics of the switch to each current 1, Figure 6(b) is a characteristic diagram showing the input/output characteristics of the first embodiment, and Figure 7 is a specific diagram of the first embodiment. Circuit diagram showing the configuration,
FIG. 8 is a circuit diagram showing a second embodiment of the present invention. 11...Gun 7?1ti positive circuit 12△, 1211, 12C...Karen l-switch 1;
3...Q adder 1...constant current source Q)"...1
~Ran resistor 1<1-...f+load resistance \ゝ-1//

Claims (1)

【特許請求の範囲】[Claims] 被写体を正しい階調で再現リ−るためのガンマ補m回路
にa3いて、それぞれ所要のリミッタ特性を右し、差動
増幅器で構成された複数の電流スインfど、これら電流
スイッチの出力をhu算して出力する加9手段とを設(
)だことを特徴と覆る広帯域ガンマ補J]回路、6
In order to reproduce the subject with the correct gradation, the gamma complement circuit is used to set the required limiter characteristics, and the outputs of these current switches, such as multiple current switches made up of differential amplifiers, are 9 means for calculating and outputting (
) wideband gamma correction circuit, 6
JP59114118A 1984-06-04 1984-06-04 Broad band gamma correction circuit Pending JPS60257674A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59114118A JPS60257674A (en) 1984-06-04 1984-06-04 Broad band gamma correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59114118A JPS60257674A (en) 1984-06-04 1984-06-04 Broad band gamma correction circuit

Publications (1)

Publication Number Publication Date
JPS60257674A true JPS60257674A (en) 1985-12-19

Family

ID=14629584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59114118A Pending JPS60257674A (en) 1984-06-04 1984-06-04 Broad band gamma correction circuit

Country Status (1)

Country Link
JP (1) JPS60257674A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62112479A (en) * 1985-11-11 1987-05-23 Sony Corp Polygonal line approximation type function generation circuit
JPH03171880A (en) * 1989-11-29 1991-07-25 Nec Corp Gamma correcting circuit
JPH05110899A (en) * 1991-10-21 1993-04-30 Nec Ic Microcomput Syst Ltd Video signal processing circuit
WO1994014276A1 (en) * 1992-12-04 1994-06-23 Hughes-Jvc Technology Corporation Gamma correction circuit for use in image projectors
JPH06205340A (en) * 1993-01-05 1994-07-22 Nec Corp Liquid crystal display device
WO1995006999A1 (en) * 1993-09-03 1995-03-09 Hughes-Jvc Technology Corporation Dynamic gamma correction circuit for use in image projectors
US5461430A (en) * 1992-12-04 1995-10-24 Hughes Jvc Tech Corp Dynamic gamma correction circuit for use in image projectors
US5473372A (en) * 1991-03-18 1995-12-05 Canon Kabushiki Kaisha Gamma correction circuit approximating non-linear digital conversion
US5900918A (en) * 1997-07-30 1999-05-04 Hughes-Jvc Technology Corporation Adjustable video gamma circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5945775A (en) * 1982-09-09 1984-03-14 Sharp Corp Gamma correcting circuit
JPS5967784A (en) * 1982-10-12 1984-04-17 Hitachi Ltd Gamma correcting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5945775A (en) * 1982-09-09 1984-03-14 Sharp Corp Gamma correcting circuit
JPS5967784A (en) * 1982-10-12 1984-04-17 Hitachi Ltd Gamma correcting circuit

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62112479A (en) * 1985-11-11 1987-05-23 Sony Corp Polygonal line approximation type function generation circuit
JPH03171880A (en) * 1989-11-29 1991-07-25 Nec Corp Gamma correcting circuit
US5473372A (en) * 1991-03-18 1995-12-05 Canon Kabushiki Kaisha Gamma correction circuit approximating non-linear digital conversion
JPH05110899A (en) * 1991-10-21 1993-04-30 Nec Ic Microcomput Syst Ltd Video signal processing circuit
WO1994014276A1 (en) * 1992-12-04 1994-06-23 Hughes-Jvc Technology Corporation Gamma correction circuit for use in image projectors
US5461430A (en) * 1992-12-04 1995-10-24 Hughes Jvc Tech Corp Dynamic gamma correction circuit for use in image projectors
JPH06205340A (en) * 1993-01-05 1994-07-22 Nec Corp Liquid crystal display device
WO1995006999A1 (en) * 1993-09-03 1995-03-09 Hughes-Jvc Technology Corporation Dynamic gamma correction circuit for use in image projectors
US5900918A (en) * 1997-07-30 1999-05-04 Hughes-Jvc Technology Corporation Adjustable video gamma circuit

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