JPH04241586A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To easily suppress fixed pattern noise caused by the dispersion of a threshold voltage or the like at low cost by easily obtaining an offset corrected image signal without using an external memory or the like at an AMI. CONSTITUTION:At each picture element 1, a column select signal having a binary amplitude is supplied to a column select line Lx to which a horizontal switching transistor Tx and a transistor Trs for reset are connected, and a signal current superimposing a real signal current and an offset current to and an offset current are successively outputted to a signal line Ls. Then, the respective signal current and offset current are converted to voltages by an operational amplifier 4 and defined as a signal output voltage and a reset output voltage respectively and afterwards, these output voltages Vo are sampled/held, for example, so as to subtract the above-mentioned signal output voltage and reset output voltage by using a differential amplifier, for example, in the rear step.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device in which a plurality of pixels are arranged in a matrix, and more particularly to an internal amplification type solid-state imaging device in which optical signal charges are amplified within each pixel, so-called AMI. (Amplified MOS
The present invention relates to a solid-state imaging device having an Intelligent Imager.

0002

[Prior Art] As the resolution of solid-state imaging devices increases, research is being conducted on internally amplified solid-state imaging devices that have an amplification function for each pixel. "Solid-state imaging technology", "Television Society Journal" 78
The description is on pages 7-793, Vol. 42, No. 8 (1988).

[0003] Here, to briefly explain an example of an amplification type solid-state imaging device, the circuit configuration of each pixel is as shown in FIG. It is composed of a reset transistor Trs. That is,
The gate of the amplification transistor Ta and the source of the reset transistor Trs are connected to the light receiving element PD, the source of the vertical switching transistor Ty is connected to the drain of the amplification transistor Ta, and the drains of the vertical switching transistor Ty and the reset transistor Trs are connected to each other. A common power supply line L is connected, and the output signal of the corresponding pixel is obtained through the source of the amplification transistor Ta. FIG. 5 shows an equivalent circuit related to signal readout processing of this pixel. Here, Tx indicates a horizontal switching transistor.

In this amplification type solid-state imaging device, an amplified signal is obtained by applying a signal charge corresponding to the amount of light incident on the light receiving element PD of each pixel to the gate of an amplification transistor Ta provided for each pixel. The current is taken out as an output signal from the source of the amplifying transistor Ta.

[0005]

However, a common problem in conventional amplified solid-state imaging devices is fixed pattern noise (FPN). As shown in FIG. 6, this fixed pattern noise appears as an offset current Ios superimposed on the output signal (output current) Io,
In particular, as the amount of received light increases, the SN ratio of the output signal Io deteriorates. This fixed pattern noise is caused by the adhesion of dust during the transistor manufacturing process, non-uniformity of optical masks, non-uniformity of processing precision such as mask alignment accuracy and exposure conditions. There are variations in threshold voltage, etc.

[0006] As a method for removing the fixed pattern noise caused by variations in the threshold voltage, an external memory is currently used. (See “Noise Removal Method”). In this case, a frame memory is required, but if this frame memory is configured with 1 pixel and 8 bits, a display with 780 (H) x 500 (V) pixels will require 780 x 500 x 8 = 3.1 M bits. becomes. In addition, HDT of 1150 (H) x 500 (V) pixels
For V-compatible displays, 1150 x 500 x 8 = 4
．． 8M bits are required. In this way, when using external memory, the cost increases due to the addition of memory (for example, DRAM, etc.) and a large-scale signal processing circuit that accesses the memory, and there are disadvantages such as increased power consumption. be.

The present invention has been made in view of the above-mentioned problems, and its purpose is to eliminate the need for an external memory that increases costs, and to easily reduce output current offset due to threshold voltage. An object of the present invention is to provide a solid-state imaging device that can suppress fixed pattern noise.

[0008]

[Means for Solving the Problems] The present invention provides a light receiving element PD.
, an amplification means Ta for amplifying the signal charge from the light receiving element PD, and a reset means T for resetting the signal charge.
rs in each pixel 1, and these pixels 1 are arranged in a matrix, the row selection signal V
reset means connects a row selection switch Ty to a row selection line Ly to which m is supplied, and connects the row selection switch Ty to a column selection line Lx to which column selection signals H[1] and H[2] having binary amplitudes Vx1 and Vx2 are supplied; Trs and the column selection switch Tx are connected, and the amplifying means Ta is configured to sequentially output an output signal I[1] and a reset output signal I[2] to the signal line Ls.

[0009]

[Operation] According to the configuration of the present invention described above, in each pixel 1, the column selection signal H[1 having binary amplitudes Vx1 and Vx2 is connected to the column selection line Lx to which the reset means Trs and the column selection switch Tx are connected. ] and H[2], and output signal (signal in which true signal current Io and offset current I[2] are superimposed) I[1] and reset output signal (offset current) I[ 2] are sequentially output, so each output signal I[1] and I[2] is sampled and held, and the output signal I[1] and the above are output using a differential amplifier 8 in a subsequent stage. Reset output signal I[
2], the offset-corrected signal output So can be easily obtained, and fixed pattern noise due to variations in threshold voltage can be suppressed easily and at low cost.

0010

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 shows that the main parts of the solid-state imaging device according to this embodiment, in particular the structure of each pixel, are connected to a MOSFET (MOS
FIG. 2 is a circuit diagram showing an internal amplification type solid-state image sensor A of a type in which current is amplified by applying current to the gate of a field effect transistor (type field effect transistor).

Each pixel 1 of this solid-state image sensor A includes a photodiode PD, an amplification transistor Ta each composed of a MOSFET, and a horizontal switching transistor T.
x, a vertical switching transistor Ty, and a reset transistor Trs, and these pixels 1 are arranged in a matrix to form an image portion of the solid-state image sensor A. Further, a vertical scanning circuit 2 for vertical scanning and a horizontal scanning circuit 3 for both reset and horizontal scanning are provided around the image portion.

The vertical scanning circuit 2 controls on/off the vertical switching transistors Ty in each row, and the horizontal scanning circuit 3
controls on/off of the horizontal switching transistor Tx and reset transistor Trs in each column. and,
For example, by the row selection signal Vm from the vertical scanning circuit 2,
Assuming that a row is selected (vertical switching transistor Ty for m rows is on), the horizontal scanning circuit 3
For example, column n-1, column n, column n+1, etc. are sequentially selected in accordance with the column selection signal H from . m rows n+1 columns・
The output current I of the pixel 1 at ... appears on the video line VL via the m-row signal line Ls.

Next, to explain the configuration of each pixel 1, the photodiode PD in each pixel 1 is connected to the drain of a vertical switching transistor Ty through its cathode, and this vertical switching transistor Ty has its source connected to the drain of the vertical switching transistor Ty. It is connected to the gate of the amplification transistor Ta through the amplification transistor Ta. Furthermore, a row selection line Ly from the vertical scanning circuit 2 is connected to the gate of the vertical switching transistor Ty. Only when the gate of the vertical switching transistor Ty is turned on through the row selection line Ly, a potential based on the optical signal charge generated in the photodiode PD is applied to the gate of the amplification transistor via the vertical switching transistor. Further, a horizontal switching transistor Tx is connected in series to the amplification transistor Ta, and a column selection line Lx from the horizontal scanning circuit 3 is connected to the gate of the horizontal switching transistor Tx. A signal line Ls is connected to the source.

The photodiode PD is also connected to the reset transistor Trs in addition to the vertical switching transistor Ty, and the gate of the reset transistor Trs is connected to the horizontal scanning circuit 3 similarly to the horizontal switching transistor Tx. Column selection line Lx from is connected. A power supply voltage Vdd common to all pixels is applied to each drain of the amplification transistor Ta and the reset transistor Trs. Furthermore, in this example, the thresholds at which the horizontal switching transistor Tx and the reset transistor Trs are turned on are set to V, respectively.
Assuming thx and Vthr, these two transistors Tx and Trs are designed so that Vthx<Vthr.

Next, please also refer to FIGS. 2 and 3 regarding the operation of the solid-state imaging device according to this example, and in particular, the readout method for removing offset potentials caused by variations in threshold values and suppressing fixed pattern noise. I will explain. FIG. 2 is a block diagram showing the subtraction processing circuit B used in the solid-state imaging device of this example, and FIG. 3 is a waveform diagram showing signal readout processing of this example.

First, in the initial state of the solid-state image sensor A, an initial value Vdd is set in the photodiode PD of each pixel 1 via the reset transistor Trs. During the subsequent light reception period, electrons excited by the incident light are absorbed by the photodiode PD, so the potential of the photodiode PD decreases in accordance with the incident light. Next, a row selection signal Vm is supplied from the vertical scanning circuit 2 to the row selection line Ly of m rows, for example. By supplying this row selection signal Vm, the gate of the vertical switching transistor Ty of the m row is turned on, and the potential of the photodiode PD regarding the m row is applied to the gate of the amplification transistor Ta through the vertical switching transistor Ty. Note that this solid-state image sensor A has a so-called negative type characteristic in which the output current is largest in a dark state, and the output current decreases as the incident light increases.

Next, a column selection signal Hn-1 is supplied from the horizontal scanning circuit 3 to the column selection line Lx of the n-1 column, for example. This column selection signal Hn-1 is divided into primary and secondary selection signals, and the voltage amplitude VX1 of the primary selection signal Hn-1 [1] is smaller than that of the secondary selection signal. That is, the voltage amplitude VX1 of the primary selection signal Hn-1 [1] is larger than the threshold value Vthx of the horizontal switching transistor Tx and the threshold value Vth of the reset transistor Trs.
is set smaller than r (Vthx<VX1<Vthr)
, the voltage amplitude VX2 of the secondary selection signal Hn-1 [2] is set larger than the threshold value Vthr of the reset transistor Trs (VX2>Vthr).

Therefore, the primary selection signal Hn-1 [1]
At the time of input, the horizontal switching transistor Tx turns on, and the signal current (signal in which the true signal current and offset current are superimposed) corresponding to the potential applied to the gate of the amplification transistor Ta is horizontally switched on. The signal is read out to the signal line Ls through the switching transistor Tx, and further read out to the video line VL through the signal line Ls. At this time, the reset transistor Trs is off. When the next secondary selection signal Hn-1 [2] is input, the reset transistor Trs is turned on while the horizontal switching transistor Tx remains on, and the photodiode PD is reset. At this time, the signal current (offset current) In-1 [1] at the time of reset is read out to the video line VL through the signal line Ls. Then, sequentially from the horizontal scanning circuit 3, n columns, n+1 columns, n+
A column selection signal Hn, is applied to each column selection line Lx of two columns...
By supplying Hn+1, Hn+2...
The signal current I[1] of the pixel 1 regarding the m row and the signal current I[2] at the time of reset are read out to the video line VL through the signal line Ls of the m row.

Hereinafter, the primary selection signal (Hn-
1 [1], Hn[1], Hn+1 [1], Hn+2
[1]...), secondary selection signal (Hn-1 [2]
, Hn [2], Hn+1 [2], Hn+2 [2]・
), signal current (In-1 [1], In [1],
In+1 [1], In+2 [1]...) and offset current (In-1 [2], In [2], In+1
[2], In+2 [2]...) are respectively collectively called,
They are written as H[1], H[2], I[1] and I[2].

Each of the signal currents I[1] and I[2] read out to the video line VL is voltage-converted by the operational amplifier 4 in the next stage, and is supplied to the subtraction processing circuit B in the subsequent stage as an output voltage Vo. . Similar to the signal current I, the output voltage Vo is the signal output voltage V[1] (Vn-1 [1], Vn[1], Vn+1) corresponding to the primary selection signal H[1].
[1], Vn+2 [1]...) and the secondary selection signal H
Reset output voltage V[2] (Vn-1
[2], Vn [2], Vn+1 [2], Vn+2
[2]...) are output in sequence.

The subtraction processing circuit B includes three sampling and holding circuits (hereinafter simply referred to as S/H circuits) 5, 6, and 7, and a differential amplifier 8. The above output voltage Vo is
The first S/H circuit 5 and the third S/H circuit 5 through contact a, respectively.
It is supplied to the circuit 7. The output voltage Vo input to the first S/H circuit 5 is sampled and held as the signal output voltage V[1] based on the first clock signal C1, and input to the third S/H circuit 7. The output voltage Vo is reset to the reset output voltage V[2 based on the second clock signal C2.
] is sampled and held. First S/H circuit 5
The first sampling hold signal (hereinafter simply referred to as S/H signal) SH1 output from the second S/H signal
It is supplied to the H circuit 6. The first S/H signal SH1 input to the second S/H circuit 6 is sampled and held based on the second clock signal C2. Then, from this second S/H circuit 6, the signal output voltage V
[1] and has the same amplitude as the second clock signal C2
A second S/H signal SH2 synchronized with the output timing of
is output from the third S/H circuit 7, and the third S/H has the same amplitude as the reset output voltage V[2] and is synchronized with the output timing of the second clock signal C2.
Signal SH3 is output.

These second S/H signal SH2 and third S/H signal SH3 are supplied to the next stage differential amplifier 8, and in the differential amplifier 8, each S/H signal SH2 and S
H3 subtraction processing is performed, and the image pickup signal So after the subtraction processing is output from the output terminal φo. That is, the second S/H signal SH2 has the same value as the signal output voltage V[1], and this signal SH2 has a reset output voltage V[2] based on the offset current I[2] at the time of reset. ] are superimposed. Further, the third S/H signal SH3
is equal to the reset output voltage V[2], so this subtraction process cancels out the reset output voltage V[2], and therefore, the true signal is output from the output terminal φo of the subtraction process circuit B. An imaging signal So based on the current Io (=I[1]-I[2]) is output.

As described above, according to this example, in each pixel 1, two lines are connected to the column selection line Lx to which the horizontal switching transistor Tx and the reset transistor Trs are connected.
Column selection signal H[1] with amplitudes of values VX1 and VX2
and H[2] to supply the true signal current I to the signal line Ls.
Signal current I[ where o and offset current I[2] are superimposed
1] and offset current I[2] sequentially, and output each signal current I[1] and offset current I[2] to operational amplifier 4.
After converting the voltages into the signal output voltage V[1] and the reset output voltage V[2] respectively, these output voltages Vo are sampled and held, and the above-mentioned signal is converted using the differential amplifier 8 in the subsequent stage, for example. Since the output voltage V[1] and the above-mentioned reset output voltage V[2] are subtracted,
The offset-corrected imaging signal So can be easily obtained without using an external memory or the like, and fixed pattern noise caused by variations in threshold voltage and the like can be suppressed easily and at low cost.

[0024]

[Effects of the Invention] According to the solid-state imaging device of the present invention, there is no need for an external memory that increases costs, and the output current offset due to the threshold voltage can be easily reduced, and fixed pattern noise can be easily and inexpensively reduced. can be suppressed.

[Brief explanation of the drawing]

[Fig. 1] A circuit diagram showing the configuration of a main part (solid-state imaging device) of a solid-state imaging device according to this embodiment.

FIG. 2 is a block diagram showing the configuration of the subtraction processing circuit according to the present embodiment.

[Fig. 3] Waveform diagram showing signal processing of the solid-state imaging device according to the present example

[Fig. 4] A circuit diagram showing the circuit configuration of a pixel according to a conventional example.

[Fig. 5] Equivalent circuit diagram showing conventional signal readout processing

[Figure 6]
Characteristic diagram showing changes in output current with respect to amount of received light

[Explanation of symbols]

A Solid-state image sensor B Subtraction processing circuit 1 Pixel 2 Vertical scanning circuit 3 Horizontal scanning circuit 4 Operational amplifier 5 First S/H circuit 6 Second S/H circuit 7 Third S/H circuit 8 Differential amplifier Ta Amplification Transistor Ty Vertical switching transistor Tx Horizontal switching transistor Trs Resetting transistor PD Photodiode

Claims (1)

[Claims] 1. A solid-state image pickup in which each pixel has a light receiving element, an amplification means for amplifying a signal charge from the light receiving element, and a reset means for resetting the signal charge, and these pixels are arranged in a matrix. In the device, a row selection switch is connected to a row selection line to which a row selection signal is supplied;
The reset means and column selection switch are connected to a column selection line to which a column selection signal having a binary amplitude is supplied, and an output signal and a reset output signal are sequentially output from the amplification means to the signal line. solid-state imaging device.