JPS60257631A - Optical reception circuit - Google Patents

Optical reception circuit

Info

Publication number
JPS60257631A
JPS60257631A JP59113591A JP11359184A JPS60257631A JP S60257631 A JPS60257631 A JP S60257631A JP 59113591 A JP59113591 A JP 59113591A JP 11359184 A JP11359184 A JP 11359184A JP S60257631 A JPS60257631 A JP S60257631A
Authority
JP
Japan
Prior art keywords
circuit
transistor
voltage
current
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59113591A
Other languages
Japanese (ja)
Other versions
JPH0586685B2 (en
Inventor
Seigo Naito
内藤 清吾
Hiroshi Mabuchi
馬渕 浩
Toshitsugu Tamura
田村 年次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP59113591A priority Critical patent/JPS60257631A/en
Publication of JPS60257631A publication Critical patent/JPS60257631A/en
Publication of JPH0586685B2 publication Critical patent/JPH0586685B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B10/00Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60Receivers
    • H04B10/66Non-coherent receivers, e.g. using direct detection
    • H04B10/69Electrical arrangements in the receiver
    • H04B10/691Arrangements for optimizing the photodetector in the receiver
    • H04B10/6911Photodiode bias control, e.g. for compensating temperature variations

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Optical Communication System (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To prevent an output voltage from being affected by temperature and power supply voltage by connecting a current-voltage conversion preamplifier circuit to a photodetector and connecting a main amplifier circuit to the preamplifier circuit via a resistor. CONSTITUTION:The current-voltage converting preamplifier circuit 1 feeds back an output of a transistor (TR)Q2 to an input side of a TR circuit via a resistor R1. Similarly, an output of a TRQ7 is fed back to the input of a TRQ6 via a resistor R4 in a main amplifier circuit 2. The preamplifier circuit 1 and the main amplifier circuit 2 are connected via a resistor R3. A reference voltage generating circuit 3 decides the operating current of TRs Q5, Q10. In setting the value of resistors R1, R3, R5 and R7 so as to establish the relation of R3R7=R1R5 and selecting the ratio of the resistor R3 to the R4 to a prescribed value, the output voltage is made independent of the temperature and power voltage.

Description

【発明の詳細な説明】 〔発明の背景と目的〕 本発明は光受信回路に係り、特に出力電圧を温度、電圧
に依存しない安定なものとするのに好適な光受信回路に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Background and Objectives of the Invention] The present invention relates to an optical receiving circuit, and particularly to an optical receiving circuit suitable for making the output voltage stable regardless of temperature and voltage.

従来の光受信回路に使用されている増幅器の一例を第1
図に示す。トランジスタQ、のエミッタはダイオードD
を介して接地してあり、トランジスタQ1は、負荷抵抗
&を含めてエミッタ接地回路として動作するようにしで
ある。トランジスタQ2はコレクタ接地(コミツタフォ
ロワ)回路を構成シており、出力インピーダンスを下げ
て抵抗1(、Fによる帰還ループへの影響を小さくして
いる。l−ランジスタQll Q21 ダイオードD、
抵抗Rb、 R,F、 REからなる増幅部は、いわゆ
るl・ランスインピーダンス形増幅回路を構成しており
、低入力インピーダンであるため、効率のよい電流−電
圧変換回路として受光素子P I)と組合せて光受信回
路として使用されている。なお、ダイオードDは、出力
型イ立を」二げて次段との接続を行いやすくする働きを
もっている。
The first example of an amplifier used in a conventional optical receiver circuit is
As shown in the figure. The emitter of transistor Q is diode D.
The transistor Q1, including the load resistor &, is designed to operate as a common emitter circuit. Transistor Q2 constitutes a common collector (committee follower) circuit, and lowers the output impedance to reduce the influence of resistor 1 (, F) on the feedback loop.
The amplifier section consisting of resistors Rb, R, F, and RE constitutes a so-called lance impedance type amplifier circuit, and has a low input impedance, so it can be used as an efficient current-to-voltage conversion circuit with the light receiving element PI). The combination is used as an optical receiver circuit. Note that the diode D has the function of reducing the output type problem and making it easier to connect to the next stage.

さて、光入力がない場合の出力電圧V1は、次式で表わ
される。
Now, the output voltage V1 when there is no optical input is expressed by the following equation.

VI= VBEI + Vp + In+Rp ・=(
1)ここに、■BE1;トランジスタQlのベース・エ
ミッタ間電圧 IB+ : t□ランジスタQ、のコレクタ電流■F;
ダイオードDの電圧降下 RF;抵抗Rpの抵抗値 次に、トランジスタQ1のコレクタ電流■clをめると
、 RI。
VI= VBEI + Vp + In+Rp ・=(
1) Here, ■BE1; Base-emitter voltage IB+ of transistor Ql: t□Collector current of transistor Q, ■F;
Voltage drop RF of diode D; resistance value of resistor Rp Next, when collector current ■cl of transistor Q1 is subtracted, RI.

ここに、vcc;電源電圧 Vngz : l・ランジスタQ2のベース、エミッタ
間電圧 几1= r抵抗几■、の抵抗値 となる。ところで、IC1−IB・hFE(hFEはト
ラ、ジスタの電流増幅率)であることを考慮して(IL
 (2)式より■1をめると、次式となる。
Here, vcc is the resistance value of power supply voltage Vngz: l and the voltage between the base and emitter of transistor Q2 1=r resistance 几■. By the way, considering that IC1-IB・hFE (hFE is the current amplification factor of a transistor or a transistor), (IL
Subtracting ■1 from equation (2) yields the following equation.

ここで、VBEI 、 Vngz、 VFは一般に約−
2mV/degという大きな負の温度係数をもっている
上に、(3)式かられかるように、’ Vlは電源電圧
V。0およびトランジスタのhFEという基本的な特性
に依存するので、直流的に次段増幅器と接続すると、特
性変動が大きくなり、安定な動作が困難であるという問
題を生ずる。
Here, VBEI, Vngz, VF are generally about -
In addition to having a large negative temperature coefficient of 2 mV/deg, as can be seen from equation (3), 'Vl is the power supply voltage V. Since it depends on the basic characteristics of 0 and hFE of the transistor, if it is connected to the next stage amplifier in a direct current manner, the characteristics will fluctuate greatly and stable operation will be difficult.

本発明は上記に鑑みてなされたもので、その目的とする
ところは、温度や電源電圧に対して特性が安定な光受信
回路を提供することにある。
The present invention has been made in view of the above, and an object of the present invention is to provide an optical receiving circuit whose characteristics are stable with respect to temperature and power supply voltage.

〔発明の概要〕[Summary of the invention]

本発明の特徴は、光信号を入力して電流に変換する受光
素子と、この受光素子の出力電流を電圧に変換するエミ
ッタにダイオードを接続し、コレクタにPNPI−ラン
ジスタのコレクタを接続してこのPNPトランジスタを
能動負荷としたトランジスタからなるエミッタ接地回路
と別のトランジスタからなるコレクタ接地回路とを接続
し、とのコレクタ接地回路の出力を上記エミッタ接地回
路の入力側に帰還回路を介して帰還するようにしてなる
電流−電圧変換前置増幅回路と、この前置増幅回路の出
力端に抵抗を介して接続した上記前置増幅回路と同一回
路構成の主増幅回路と、上記前置増幅回路および主増幅
回路のPNPトランジスタの動作電流を決定する基準電
圧発生回路とからなる回路構成とした点にある。
The feature of the present invention is that a diode is connected to a photodetector that inputs an optical signal and converts it into a current, an emitter that converts the output current of this photodetector to a voltage, and a collector of a PNPI transistor is connected to the collector. A common emitter circuit consisting of a transistor with a PNP transistor as an active load is connected to a common collector circuit consisting of another transistor, and the output of the common collector circuit is fed back to the input side of the common emitter circuit via a feedback circuit. A current-to-voltage conversion preamplifier circuit formed by the above, a main amplifier circuit having the same circuit configuration as the preamplifier circuit connected to the output terminal of the preamplifier circuit via a resistor, the preamplifier circuit and The present invention has a circuit configuration including a reference voltage generation circuit that determines the operating current of the PNP transistor of the main amplifier circuit.

〔実施例〕〔Example〕

以下本発明を第2図に示した実施例を用いて詳細に説明
する。
The present invention will be explained in detail below using the embodiment shown in FIG.

第2図は本発明の光受信回路の一実施例を示す回路図で
ある。第2図において、トランジスタQ+〜Q4.抵抗
Rt、 R2からなる回路部1は、受光素子PDで受け
た光信号を電圧に変換する働きをする電流−電圧変換前
置増幅回路である。トランジスタQ6〜Qlo、抵抗R
4,R5からなる回路部2は、主増幅回路で回路部1と
抵抗R3を介して接続しである。
FIG. 2 is a circuit diagram showing an embodiment of the optical receiving circuit of the present invention. In FIG. 2, transistors Q+ to Q4. A circuit section 1 including resistors Rt and R2 is a current-to-voltage conversion preamplifier circuit that functions to convert an optical signal received by the light receiving element PD into a voltage. Transistors Q6 to Qlo, resistor R
The circuit section 2 consisting of 4 and R5 is a main amplifier circuit and is connected to the circuit section 1 via a resistor R3.

また、トランジスタQllj抵抗R6,R7からなる回
路部3は、l−ランジスタQ5p Qloの動作電流を
決定する基準電圧発生回路である。
Further, the circuit section 3 consisting of the transistor Qllj and the resistors R6 and R7 is a reference voltage generation circuit that determines the operating current of the l-transistor Q5p Qlo.

トランジスタQs、 Qloは、PNP )ランジスタ
を用いてあり、定電流源として使用してあり、それぞれ
トランジスタQ+、 Q6の能動負荷として動作する。
Transistors Qs and Qlo are PNP transistors, used as constant current sources, and operate as active loads for transistors Q+ and Q6, respectively.

なお、回路部1は、エミッタにダイオード(第2図では
トランジスタQ3が用いてあり、第1図のダイオードD
と同じ作用をする)を接続し、コレクタにPNP )ラ
ンジスタQ5のコレクタを接続してPNI〕トランジス
タQ5を能動負荷としたトランジスタQ1からなるエミ
ッタ接地回路とトランジスタQ2からなるコレクタ接地
回路とを接続し、このコレクタ接地回路の出力を上記エ
ミッタ接地回路の入力側に抵抗R+からなる帰還回路を
介して帰還するようにしである。回路部2も同様で、エ
ミッタにダイオード(第2図ではトランジスタQs)を
接続し、コレクタにP N I) )ランジスタQIo
のコレクタを接続してPNP)ランジスタQ!oを能動
負荷としたトランジスタQ6からなるエミッタ接地回路
とトランジスタQ7からなるコレクタ接地回路とを接続
し、このコレクタ接地回路の出力を上記エミッタ接地回
路の入力側に抵抗R4からなる帰還回路を介して帰還す
るようにしである。
Note that the circuit section 1 has a diode (a transistor Q3 is used in FIG. 2, and a diode D in FIG. 1 is used as an emitter).
The collector of PNP transistor Q5 is connected to the collector of transistor Q5, and the common emitter circuit consisting of transistor Q1 with transistor Q5 as an active load is connected to the common collector circuit consisting of transistor Q2. The output of this common collector circuit is fed back to the input side of the common emitter circuit via a feedback circuit consisting of a resistor R+. Circuit section 2 is similar, with a diode (transistor Qs in Figure 2) connected to the emitter, and a transistor QIo connected to the collector.
Connect the collector of PNP) transistor Q! A common emitter circuit consisting of a transistor Q6 with o as an active load is connected to a common collector circuit consisting of a transistor Q7, and the output of this common collector circuit is connected to the input side of the common emitter circuit via a feedback circuit consisting of a resistor R4. I am planning to return.

次に、第2図の回路の動作を式を用いて説明する。ただ
し、引算で次のことを仮定する。各トランジスタの電流
増幅率は同一であるものとし、これをhFFとする。捷
だ、各抵抗は温度依存性がないものとする。これらは集
積回路内では容易に成立する条件であり、妥当なもので
ある。なお、トランジスタQ+−Qoのベース電流はI
n+〜IBIIのように、また、コレクタ電流は■。1
〜IC11、また、ベース・エミッタ間電圧はV!IE
I〜VBEI+のように表示する。1だ、各抵抗の抵抗
値は各抵抗を示す符号がそれを示すものとする。
Next, the operation of the circuit shown in FIG. 2 will be explained using equations. However, in subtraction, assume the following. It is assumed that the current amplification factor of each transistor is the same, and this is referred to as hFF. Assume that each resistor has no temperature dependence. These conditions are easily satisfied within an integrated circuit and are appropriate. Note that the base current of transistor Q+-Qo is I
As n+ to IBII, the collector current is ■. 1
~IC11, and the base-emitter voltage is V! IE
It is displayed as I to VBEI+. 1. The resistance value of each resistor is indicated by the symbol representing each resistor.

まず、トランジスタQuの動作電流Ioは、次式で表わ
される。
First, the operating current Io of the transistor Qu is expressed by the following equation.

しだがって、PNPトランジスタQs、 Qloのコレ
クタ電流■c 5. Ic+oは、次式で表わされる。
Therefore, the collector currents of the PNP transistors Qs and Qlo 5. Ic+o is expressed by the following formula.

Ic 5−IBI −I。2−I。3=I。4= Io
X &/ R2・・・(51 ’C+o = Ice = IC7°I(s = IC
9−Io X &/ R5−(6) 次に、トランジスタQ6のベース電流IB6は、第2図
に示しである電流■2とI+との差であるから、次式で
表わされる。
Ic 5-IBI-I. 2-I. 3=I. 4 = Io
X &/R2...(51'C+o = Ice = IC7°I(s = IC
9-Io X &/R5-(6) Next, since the base current IB6 of the transistor Q6 is the difference between the current 2 and I+ shown in FIG. 2, it is expressed by the following equation.

ここで、 V+=Vt+r++VnE3+IBg+R1= 2VI
]EI+ IBI Rt ・・・(8)Vz=Vnp:
6+Vr+ag= 2VBE6 − (9)寸だ、 V8゜6 Vn+:+=に=−工6・±C6、、、(。
Here, V+=Vt+r++VnE3+IBg+R1= 2VI
]EI+IBI Rt...(8)Vz=Vnp:
6+Vr+ag= 2VBE6 - (9) Dimensions, V8゜6 Vn+:+=to=-6・±C6,,,(.

q Ic1 (8)〜t!DJを(7)式に代入してv3をめると、
V3= 2V++。6+R4(In2−町■8.)3 ところでz Ioa (= Ice / hpF、)と
I旧(−Ic+ / hpg )とは+5L (6)式
から明らかなように、R2,Rsの選び方で自由に設定
できる。いま、In2 =−−−−−IBI 几3 すなわち、 l R7−−−−−・R5 3 と選ぶと、0刀式は、 と表わされる。V3を温度Tで微分して■3の温度係数
をめると、 が得られる。(I3)式の第1項は負の温度係数(約−
2mv/deg )をもつのに対し、第2項は正の温度
係数であり、 Vnge  R7 と選ぶと、■3、すなわち、出力電圧は温度に対して変
動することはない。
q Ic1 (8)~t! Substituting DJ into equation (7) and subtracting v3, we get
V3=2V++. 6+R4 (In2-Machi■8.)3 By the way, z Ioa (= Ice / hpF,) and I old (-Ic+ / hpg) are +5L As is clear from equation (6), you can freely choose R2 and Rs. Can be set. Now, if we choose In2 =----IBI 几3, that is, l R7----・R5 3, the zero sword type is expressed as follows. By differentiating V3 with respect to temperature T and subtracting the temperature coefficient of ■3, the following is obtained. The first term of equation (I3) has a negative temperature coefficient (approximately -
2 mv/deg), whereas the second term is a positive temperature coefficient, and if Vnge R7 is chosen, then the following equation is satisfied: (3), that is, the output voltage does not vary with temperature.

また、(支)式のVI]E’6を、 ここに、■s:逆方向飽和電流 に置き換えると、 であるから、■3は電源電圧依存性を有する。しかし、
その値は極めて小さく、Ic6を100/Aとした場合
の■3の変動は、vccが5■から10%変動しても■
3の変動分は20 m v以内であり、全く問題となら
ない値である。したがって、第2図の回路によれば、出
力電圧■3が温度および電源電圧に依存せず、安定に動
作する。
In addition, if VI]E'6 of the (supporting) equation is replaced here with ■s: reverse saturation current, then ■3 has power supply voltage dependence. but,
The value is extremely small, and when Ic6 is 100/A, the change in ■3 is even if vcc changes by 10% from 5■.
The variation of 3 is within 20 mv, which is a value that does not pose any problem at all. Therefore, according to the circuit shown in FIG. 2, the output voltage (3) is independent of temperature and power supply voltage and operates stably.

なお、第2図の回路の受光素子PDKPINの光入力が
入射した場合の出力電圧はPIN・几1・R4/R3で
表わされる。
Note that the output voltage when light is input to the light receiving element PDKPIN of the circuit shown in FIG. 2 is expressed as PIN・几1・R4/R3.

そして、トランジスタの+1r+w t7− 慇、7>
什猷11+r変動しても、その比率が一定であれば、や
はり出力電圧v3が温度、電源′市川に依存せず安定で
あるので、集積回路として実現しやすい。
And +1r+w t7- of the transistor, 7>
Even if 11+r fluctuates, as long as the ratio is constant, the output voltage v3 is stable regardless of temperature and power source Ichikawa, so it is easy to implement as an integrated circuit.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、出力電圧が温度
や電源電圧に依存せず、温度や電源電圧に対して特性が
安定なものにできるという効果がある。
As explained above, according to the present invention, the output voltage does not depend on temperature or power supply voltage, and the characteristics can be made stable with respect to temperature and power supply voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の光受信回路の増幅器の一例を示す回路図
、第2図は本発明の光受信回路の一実施例を示す回路図
である。 1 電流−電圧変換前置増幅回路、2・主増幅回路、3
 基準電圧発生回路、 Q+−Q4. Q6〜Q91Q
l+・・・トラノジスタ+ Qs、 Q+o・・・PN
Pトランジスタ。 R1〜I(,7・抵抗。 第 1 図 + 2 3
FIG. 1 is a circuit diagram showing an example of an amplifier of a conventional optical receiving circuit, and FIG. 2 is a circuit diagram showing an embodiment of the optical receiving circuit of the present invention. 1. Current-voltage conversion preamplifier circuit, 2. Main amplifier circuit, 3.
Reference voltage generation circuit, Q+-Q4. Q6~Q91Q
l+...Tranogista+Qs, Q+o...PN
P transistor. R1~I(,7・Resistance. Figure 1 + 2 3

Claims (1)

【特許請求の範囲】[Claims] ■、 光信号を人力して電流に変換する受光素子と該受
光素子の出力電流を電圧に変換するエミッタにダイオー
ドを接続し、コレクタにPNPトランジスタのコレクタ
を接続して該PNPトランジスタを能動負荷としたl・
ランジスクからなるエソタ接地回路と別のトランジスタ
からなるコレクタ接地回路とを接続1〜、該コレクタ接
地回路の出力を前記エミッタ接地回路の入力側に帰還回
路を介して帰還するようにしてなる電流−電圧変換前置
増幅回路と、該前置増幅回路の出力端に抵抗を介して接
続した前記前置増幅回路と同一回路構成の主増幅回路と
、前記前置増幅回路および主増幅回路のP N P )
ランジスタの動作電流を決定する基準電圧発生回路とか
らなることを特徴とする光受信回路。
② Connect a diode to a photodetector that manually converts an optical signal into a current and an emitter that converts the output current of the photodetector to a voltage, connect the collector of a PNP transistor to the collector, and use the PNP transistor as an active load. I did it.
An esota grounded circuit consisting of a transistor and a collector grounded circuit consisting of another transistor are connected (1) to a current-voltage such that the output of the collector grounded circuit is fed back to the input side of the emitter grounded circuit via a feedback circuit. a conversion preamplifier circuit, a main amplifier circuit connected to the output terminal of the preamplifier circuit via a resistor and having the same circuit configuration as the preamplifier circuit, and P N P of the preamplifier circuit and the main amplifier circuit. )
An optical receiving circuit comprising a reference voltage generating circuit that determines the operating current of a transistor.
JP59113591A 1984-06-01 1984-06-01 Optical reception circuit Granted JPS60257631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59113591A JPS60257631A (en) 1984-06-01 1984-06-01 Optical reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59113591A JPS60257631A (en) 1984-06-01 1984-06-01 Optical reception circuit

Publications (2)

Publication Number Publication Date
JPS60257631A true JPS60257631A (en) 1985-12-19
JPH0586685B2 JPH0586685B2 (en) 1993-12-14

Family

ID=14616093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59113591A Granted JPS60257631A (en) 1984-06-01 1984-06-01 Optical reception circuit

Country Status (1)

Country Link
JP (1) JPS60257631A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02200030A (en) * 1989-01-30 1990-08-08 Oki Electric Ind Co Ltd Current/voltage converting circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182906A (en) * 1982-04-20 1983-10-26 Hitachi Cable Ltd Preamplifying circuit for optical receiver

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182906A (en) * 1982-04-20 1983-10-26 Hitachi Cable Ltd Preamplifying circuit for optical receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02200030A (en) * 1989-01-30 1990-08-08 Oki Electric Ind Co Ltd Current/voltage converting circuit

Also Published As

Publication number Publication date
JPH0586685B2 (en) 1993-12-14

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