JPS60254904A - Mos analog amplifier circuit - Google Patents

Abstract

PURPOSE:To generate a stable output voltage which is not affected by variation in source voltage by adjusting the gate voltage of MOS transistors (TR) as the load resistance of a source follower through a bias voltage circuit so that variation in output voltage with the source voltage is canceled. CONSTITUTION:A depletion type TR is used as a Tr2 of a load bias circuit and its operation point is set in a nonsaturation region (triode region). An enhancement type TR is used as a Tr1 of the load bias circuit, and the gate is connected to the drain, allowing the TR to operate in a saturation region. The Tr1 and Tr2 divide the source voltage VDD and the divided voltage Vb is outputted from the connection point A and supplied to gates of the Tr2, Tr5, and Tr7. The Tr2 is in the nonsaturation triode region, so the voltage Vb at the output terminal A rises as the source voltage VDD rises, and consequently the gate voltage of the Tr5 and Tr7 rises to increase the conductivity, so that the output voltage Vout does not rise with the source voltage VDD.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an analog amplifier circuit using an MO3I transistor as a source follower.

Conventional technology and problems In the source follower circuit, the amplification element used is n-channel MOS)
In the case of a transistor, its drain is connected to a power supply, its source is connected to ground via a load resistor, an input voltage is applied to its gate, and an output voltage is obtained from the connection point between the source and the load resistor. Although the source follower has a gain of 1 or less, it is often used for impedance conversion. One practical example is the output section of a COD (charge-coupled device), an outline of which is shown in FIG.

In this figure, T r I % T r 7 is an n-channel MOS
) transistors, and T r 4 to T r 7 constitute a two-stage source follower. That is 'l'r4. The drain of 'l'r6 is connected to the power supply VDD, and the source of transistor Tr5.'l'r6 serves as a load resistance. Connected to the drain of Tr7,
The sources of the Try and Tr7 are connected to the power supply (ground) Vss. Try, Tr2 are load bias circuits, and transistors 'l'r5. A gate voltage is supplied to Tr7 to set these as load resistances of appropriate values. If the source follower is connected in two stages, the gain will further decrease, but two stages are often used in COD to accommodate load capacitance. The D shown by the diode mark is COD (
It is the output part of a charge-coupled device (charge-coupled device) and consists of diffusion regions similar to the source and drain of a transistor. The output section is connected to the power supply VDD via the transistor T r 3.

This transistor T r 3 is a depletion type and is normally cut off, and when the reset clock φR is input, it is cut on (on) and the output section is directly connected to the power supply VDD (equivalently). Reset.

(b) of FIG. 2 shows the waveform of the reset clock φR,
FIG. 5(a) shows the waveform of the output voltage Vout. When the reset clock φR is applied to the transistor T r 3 in FIG. 1, T r 3 turns on and the output part of COD is connected to the power supply
DD, transistor T r 4 , 'rr
5° is divided according to the on-resistance values of TR6 and TR7, and the output voltage Vout is obtained. When the reset clock φR is cut off, the potential at the output section drops slightly due to the gate-source capacitance of the transistor T r 3, and as a result, the output voltage Vo
ut is also slightly lower. This portion Q becomes the DC (direct current) reference level. Next, when the charges (electrons) of the COD are transferred and enter the output section, the potential of the output section decreases. The potential change in this portion R is determined by the inflow charge, so Q-R
becomes the signal voltage Vsg. Reading the signal voltage is done in part R
An output is obtained by reading the potential of the intermediate part of each part and calculating the difference from the reference level Q.

When a COD is used in a portable television camera or the like, the power source is a dry battery or the like, and the power supply voltage is likely to fluctuate when power is supplied after boosting the voltage from the dry battery. When the power supply voltage VDD fluctuates, the output voltage Vout as a whole fluctuates as the power supply voltage fluctuates, as shown in Figure 2 (C1).In this case, the partial Q and R levels also fluctuate, so the output signal obtained by sampling this includes power supply voltage fluctuations, making it unstable.

OBJECTS OF THE INVENTION The present invention aims to improve the above points and generate a stable output voltage that is not affected by power supply voltage fluctuations.

Structure of the Invention The present invention consists of a MOS transistor circuit connected to a source follower, a MOS transistor circuit serving as a load resistance of the circuit, and a pair of MOS transistors having the gate connected to the drain.
In a MOS analog amplifier circuit equipped with a load bias circuit that applies a bias voltage obtained by dividing a power supply voltage using a transistor, a pair of Mo
One of the s transistors is a depletion type and is operated in a non-saturation region, so that the load bias circuit outputs a voltage that fluctuates so that the output voltage of the source follower does not fluctuate due to fluctuations in the power supply voltage when the power supply voltage fluctuates. Next, this will be explained with reference to examples.

Embodiments of the Invention In the present invention, the transistor T of the load bias circuit shown in FIG.
r2 is made into a depletion type, and the operating point is selected in the non-saturation region (triode region). In the conventional circuit, this transistor T r 2 is of an enhancement type, and its operating point is in the saturation region. The transistor T r H of the load bias circuit is of an enhancement type in both the circuit of the present invention and the conventional circuit, and the gate is connected to the drain to operate in the saturation region.

Transistor Tr1. Tr2 divides the power supply voltage VDD, outputs the divided voltage from the connection point A, and outputs the divided voltage vb.
are transistors T r2 , T r5 . Supplied to the gate of Tr7. As in the conventional circuit, the transistor T r
When both l and T r2 operate in the saturation region, the voltage v
b is not affected much by the power supply voltage VDD and remains constant. Therefore, when the power supply voltage VDD increases, for example, the output voltage Vout of the source follower stage also increases.

On the other hand, in the circuit of the present invention, the transistor Tr2 is in the unsaturated triode region, so when the power supply voltage VDD increases, the voltage Vb at the output terminal A increases, and as a result, the gate voltage of the transistors Tr5 and Trt increases. The conductivity is increased, that is, the resistance becomes low, and the output voltage Vout does not rise as the power supply voltage VDD increases. voltage v
It is desirable that b changes so as to sufficiently suppress the change in Vout due to the change in VDD.
This can be achieved by appropriately selecting the size such as W/L (gate middle/gate length) of Tr2 and the operating region of Tr2. The depletion of transistor Tr2 is as follows:
This is done by implanting an impurity such as P (phosphorus) into the channel region of the transistor.

As described in detail, in the present invention, the gate voltage of the MOS transistor serving as the load resistance of the source follower is adjusted by the bias voltage circuit so as to cancel out the output voltage change caused by the power supply voltage change. A stable output voltage can be obtained even when the voltage is likely to fluctuate.
Further, since the means for this purpose is simple, that is, one of the transistors in the load bias circuit is made into a depletion type and operated in a non-saturation region, there is an advantage that the circuit does not become complicated.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation. In the drawing, T'6 and Tr7 are M connected to the source follower.
OS) transistor circuit, Tr7 is a MOS that serves as a load resistance
) The transistors Try and Tr2 are transistors of a load bias circuit that divides the power supply voltage, and T r 2 is one of the transistors. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] A MO3I-transistor circuit connected to a source follower,
In a MOS analog amplifier circuit comprising a load bias circuit that applies a bias voltage obtained by dividing the power supply voltage with a pair of MOS transistors whose gates are connected to drains to the gates of MOS transistors serving as load resistances of the circuit, One of the pair of MOS transistors constituting the load bias circuit is a depletion type and is operated in a non-saturation region, so that the output voltage of the source follower fluctuates when the power supply voltage fluctuates so that the output voltage of the source follower does not fluctuate due to the power supply voltage fluctuation. 1. A MOS analog amplifier circuit configured to output a voltage of