JPS60254760A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS60254760A
JPS60254760A JP59111524A JP11152484A JPS60254760A JP S60254760 A JPS60254760 A JP S60254760A JP 59111524 A JP59111524 A JP 59111524A JP 11152484 A JP11152484 A JP 11152484A JP S60254760 A JPS60254760 A JP S60254760A
Authority
JP
Japan
Prior art keywords
lead frame
alloy
chip
film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59111524A
Other languages
Japanese (ja)
Inventor
Nobuo Ogasa
小笠　伸夫
Seisaku Yamanaka
山中　正策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP59111524A priority Critical patent/JPS60254760A/en
Publication of JPS60254760A publication Critical patent/JPS60254760A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
    • H01L2224/32506—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To fabricate highly reliable chip bonds and wire bonds at a low cost, by forming a film of an Au-Sn alloy and a film of Ag on a die-pad part and an inner lead part in a lead frame, respectively. CONSTITUTION:An Au-Sn alloy film 8 is coated on a chip bonding part 2 of a lead frame 1 made of 42wt% Ni-Fe alloy. Ag films 9 are applied on wire bonding parts 3. The films are formed by a wet plating method or an evaporation method. By using this lead frame, an Si chip is bonded under the eutactic condition. Then the uniform wetting equivalent to the conventional method can be confirmed. Thus excellent ohmic conct property and mechanical bonding strength can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は樹脂封止型集積回路（工０）装置用リードフ
レーム（以下単にリードフレームと略称する）に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame (hereinafter simply referred to as lead frame) for a resin-sealed integrated circuit (process 0) device.

〔従来の技術〕[Conventional technology]

現在使用されているリードフレームは、材質から大別す
るとＦｅ　−Ｎｉ系、Ｃｕ系、Ｆｅ系などがあるが、使
用目的特に工Ｃそのものの高信頼性を必要とするものに
ついては、Ｆｅ　Ｎｉ系が主として使用されている。The lead frames currently in use can be broadly classified into Fe-Ni, Cu, and Fe-based lead frames based on their materials. However, for those that require high reliability for the purpose of use, especially for the construction itself, Fe-Ni-based lead frames are used. is mainly used.

これは半導体チップとリードフレームとの熱膨張の差に
起因するものであり、特に大型チップ、高集積チップに
ついてはＦｌｌｌ　ＮＩ　Ｍリードフレームが用いられ
ている。This is due to the difference in thermal expansion between the semiconductor chip and the lead frame, and in particular, Full NI M lead frames are used for large chips and highly integrated chips.

このＦｅ−Ｎｉ系リードフレームの金属被膜に関しては
、チップボンド、ワイヤーボンドなどのＩＣ組立実装の
点からＡｕ、Ａｇなどが用いられており、これらはＩＣ
の信頼性の要求度合、Ｓ１チツプの搭載方式、金属被膜
のコストなどにより使い分けられている。Regarding the metal coating of this Fe-Ni lead frame, Au, Ag, etc. are used for IC assembly and mounting such as chip bonding and wire bonding.
They are used depending on the degree of reliability required, the mounting method of the S1 chip, the cost of the metal coating, etc.

そしてこれら金属の被膜形状としては、リードフレーム
全面あるいはスポット状に形成されているが、チップボ
ンド、ワイヤーボンドなどの特性およびコスト面からみ
た場合、これら金属の単一組成での被膜が工Ｃ実装で必
ずしも最適とは云えないというのが現状である。These metal coatings are formed on the entire surface of the lead frame or in spots, but from the viewpoint of characteristics and costs for chip bonding, wire bonding, etc., coatings with a single composition of these metals are preferable for C-mounting. The current situation is that this cannot necessarily be said to be optimal.

第２図に従来の一般的なＡｕ又はＡｇの単一組成金属被
膜４を有するＦｅ−Ｎｉ合金のリードフレームを用いた
樹脂封止型工Ｃの断面を示す。FIG. 2 shows a cross section of a conventional resin-sealed mold C using a Fe--Ni alloy lead frame having a single-composition metal coating 4 of Au or Ag.

即ちＡｕ単一被膜では、被膜自体が極めて高価な為に使
用される工Ｃが限定される。またＡｕワイヤー６と接続
されるインナーリード部３は必ずしもＡｕである必要が
ない。That is, in the case of a single Au coating, the coating itself is extremely expensive, so the process C that can be used is limited. Furthermore, the inner lead portion 3 connected to the Au wire 6 does not necessarily need to be made of Au.

又、Ａｇ単一被膜では、被膜コストはＡｕに比べ大幅に
低減するものの、Ｓ１チツプ５の塔載の際、オーミック
接合性あるいは熱伝導性が要求される場合、Ａｕ−３ｉ
共晶合金形成による接続法を用いる為、Ａｕ箔あるいは
Ａｕ−８ｉ片の挿入が必要となり、結果として高コスト
になっている。Furthermore, although the cost of a single Ag film is significantly lower than that of Au, if ohmic contact or thermal conductivity is required when mounting an S1 chip 5, Au-3i
Since a connection method based on eutectic alloy formation is used, it is necessary to insert an Au foil or an Au-8i piece, resulting in high cost.

〔発明が解決しようとする問題点３ 以上の背景で、Ａｕ−８ｉ共晶法によるチップボンディ
ングが低コストで行なえるリードフレームが強く要求さ
れている。[Problem to be Solved by the Invention 3] Under the above background, there is a strong demand for a lead frame that can perform chip bonding by the Au-8i eutectic method at low cost.

〔問題点を解決するための手段〕[Means for solving problems]

この発明は上記したような現状の問題点に鑑み・リード
フレームにおいてダイパッド部とインナーリード部にそ
れぞれＡｕ−Ｓｎ合金およびＡｇの被膜を形成すること
により、信頼性の高いチップボンドとワイヤーボンドを
、従来よりも低コストで可能とすることを目的としてい
る。In view of the current problems as described above, this invention provides highly reliable chip bonding and wire bonding by forming Au-Sn alloy and Ag coatings on the die pad portion and inner lead portion of the lead frame, respectively. The aim is to make this possible at a lower cost than before.

この発明のリードフレームは、樹脂封止型Ｘａ（Ｄ　中
１７）　Ａｕ　Ｓｉ　共晶合金チップボンドタイプに用
いられるリードフレームを対象としてはい名が、他のチ
ップボンドタイプに適用できることは勿論である。Although the lead frame of the present invention is intended for a lead frame used in a resin-sealed Xa (D medium 17) Au Si eutectic alloy chip bond type, it is of course applicable to other chip bond types.

次に、この発明のリードフレームの構造をその一例を示
す第１図にて説明すると、リードフレーム１のチップボ
ンディング部２上に、ＡｕＳｎ　合金被膜８が被覆され
、ワイヤーボンディング部３上にＡｇ被膜９が被覆され
ているものである。これらの被膜は湿式めっきにて行な
えるが１他の方法例えば蒸着法で行なっても良い。Next, the structure of the lead frame of the present invention will be explained with reference to FIG. 9 is coated. These coatings can be formed by wet plating, but may also be formed by other methods such as vapor deposition.

〔作用〕[Effect]

チップボンディング部２におけるＡｕ−Ｓｎ合金被膜は
、発明者等が種々の検討を行なった結果、３１チツプと
のオーミック接合性あるいは熱放散性を害さずに、Ａｕ
使用量の低減をはかる方法として見出したものである。As a result of various studies conducted by the inventors, the Au-Sn alloy coating in the chip bonding part 2 was found to be suitable for Au-Sn alloy coating without impairing the ohmic bonding property with the 31 chip or the heat dissipation property.
This was discovered as a way to reduce the amount used.

この発明において、Ａｕ−Ｓｎ合金被膜厚を０．５〜５
．０μｍと規定した理由は、リードフレーム素材表面の
微細な凹凸を考えると０．５μｍ以下の厚さでは均一な
共晶組織が得られず、５．０μｍ以上ではコスト低減効
果が発揮できない。In this invention, the Au-Sn alloy coating thickness is 0.5 to 5.
．． The reason why it is specified as 0 μm is that, considering the fine irregularities on the surface of the lead frame material, a uniform eutectic structure cannot be obtained with a thickness of 0.5 μm or less, and a cost reduction effect cannot be achieved with a thickness of 5.0 μm or more.

又、合金組成としてＳｎ　６〜２５原子％と規定した理
由は、現状のＡｕ　−Ｓｉ共晶合金形成条件である３８
０〜４２０Ｃの温度範囲でＡｕ−Ｓｎ合金被膜層自体が
融解しない為の組成範囲であり、省Ａｕ効果上、好まし
くはＳｎ　４５〜６０原子％の範囲である０ 〔実施例〕 次にこの発明を実施例によって説明する。In addition, the reason why the alloy composition was specified as Sn 6 to 25 atomic % was because of the current Au-Si eutectic alloy formation conditions38
The composition range is such that the Au-Sn alloy coating layer itself does not melt in the temperature range of 0 to 420C, and in terms of the Au saving effect, the Sn content is preferably in the range of 45 to 60 atomic %.[Example] Next, this invention will be explained using examples.

実施例 打抜加工により得た４２重量％Ｎ１＝Ｆｅ合金リードフ
レーム上に、まずグイバット部に開口を有する弾性体シ
ートを用いてＫＡｕ　（ａＢＪ）　ｏ、　０　：３　ｍ
ｏｌ／　ｌ　ＮＳ　ｎ　２Ｐ　２０　ｙ　Ｏ−２５ｍｏ
　／ｌ　Ｎ　Ｋ　４Ｐ２　ｏ７０−５”１／ｌのめっき
浴にて電流密度１０Ａ／ｄｍで処理して、膜厚３μｍの
Ａｕ　−Ｓｎ合金めっき（Ｓｎ　：　１５　ａｔ％）を
施した。Example: On the 42% by weight N1=Fe alloy lead frame obtained by punching, an elastic sheet having an opening in the guide portion was first used to form KAu (aBJ) o, 0:3 m.
ol/l NS n 2P 20 y O-25mo
/l NK 4P2 o70-5'' 1/l plating bath at a current density of 10 A/dm to form a 3 μm thick Au-Sn alloy plating (Sn: 15 at%).

その後インナーリード部に開口を有する弾性体シートを
用いてＡｇ０Ｎ　２　ｇ／ｌ　、ＫＯＮ　１００　νｔ
のめっき浴にて電流密度２Ａ／ｄｍでストライク処理を
行ない、然るのちＡｇ０Ｎ　６０　ｇ／’ｌ　５ＫＯＮ
　９０　ｇ／１（７）めっき浴にて電流密度５０Ａ／ｄ
ｍで処理して３μｍのＡｇ層を設けた。After that, using an elastic sheet with openings in the inner lead part, Ag0N 2 g/l, KON 100 νt
Strike treatment was performed at a current density of 2 A/dm in a plating bath, and then Ag0N 60 g/'l 5KON
90 g/1(7) Current density 50 A/d in plating bath
A 3 μm Ag layer was provided by treatment with m.

このようにして得られたリードフレームを用いて、Ｓｉ
チップを共晶条件で接合しても、従来のＡｕ被膜を有す
るリードフレームの場合と同等の均一な濡れが確認され
、良好なオーミック接合性、機械的接合強度が得られた
。Using the lead frame thus obtained, Si
Even when the chips were bonded under eutectic conditions, uniform wetting equivalent to that of a conventional lead frame with an Au film was confirmed, and good ohmic bonding properties and mechanical bonding strength were obtained.

〔発明の効果〕〔Effect of the invention〕

以上詳述のように、この発明はＡｕ−８ｉ共晶系でのリ
ードフレームにおいて＼インナージー１部にＡｇ被膜、
グイバット部にＡｕ−５ｎ合金被膜を形成することによ
り、現状実装工程を変更することなく高信頼性、低コス
トのＩＣ生産を可能とするものである。As described in detail above, the present invention is based on a lead frame using an Au-8i eutectic system, in which an Ag coating is applied to the first part of the inner
By forming an Au-5n alloy film on the Guibat part, it is possible to produce ICs with high reliability and low cost without changing the current mounting process.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のリードフレームを用いた樹脂封止型Ｉ
Ｃの断面図、第２図は従来のリードフレームを用いた樹
脂封止型工Ｃの断面図である。 出願人　住友電気工業株式会社 〆・ 代理人　弁理土中村勝成゛、′、□　、！°′・〔し′ 第１図 第２図Figure 1 shows a resin-sealed type I using the lead frame of the present invention.
FIG. 2 is a cross-sectional view of a resin-sealed mold C using a conventional lead frame. Applicant: Sumitomo Electric Industries, Ltd. / Agent: Patent Attorney Katsunari Nakamura゛,′,□,! °'・[shi' Figure 1 Figure 2

Claims (4)

【特許請求の範囲】[Claims] （１）　打抜加工あるいはエツチングにより形成したリ
ードフレームにおいて、インナーリード部にＡｇ被膜、
グイバット部にＡｕ−Ｓｎ合金Ｍ膜が形成されているこ
とを特徴とする半導体装置用リードフレーム。(1) In a lead frame formed by punching or etching, the inner lead part is coated with Ag,
A lead frame for a semiconductor device, characterized in that an Au-Sn alloy M film is formed on a guide portion. （２）　グイバット部のＡｕ　−Ｓｎ合金被膜厚が０．
５〜５．０μｍであることを特徴とする特許請求の範囲
（１）項記載の半導体装置用リードフレーム。(2) The thickness of the Au-Sn alloy coating on the Guibat part is 0.
A lead frame for a semiconductor device according to claim (1), wherein the lead frame has a thickness of 5 to 5.0 μm. （３）　グイバット部のＡｕ　−Ｓｎ合金被膜組成がＳ
ｎ６〜２５原子％に対しＡｕ　９４〜７５原子％である
ことを特徴とする特許請求の範囲（１）項または（２）
項記載の半導体装置用リードフレーム。(3) The composition of the Au-Sn alloy coating on the Guibat part is S.
Claim (1) or (2) characterized in that Au is 94 to 75 at % to n6 to 25 at %.
A lead frame for a semiconductor device as described in . （４）　ダイパッド部のＡｕ　−Ｓｎ合金被膜組成が５
ｎ４５〜６０原子％に対しＡｕ　５５〜４０原子％であ
ることを特徴とする特許請求の範囲（１）項または（２
）項記載の半導体装置用リードフレーム。(4) The composition of the Au-Sn alloy coating on the die pad is 5.
Claim (1) or (2) characterized in that Au is 55 to 40 at % to n45 to 60 at %.
) A lead frame for a semiconductor device as described in item 2.
JP59111524A 1984-05-31 1984-05-31 Lead frame for semiconductor device Pending JPS60254760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59111524A JPS60254760A (en) 1984-05-31 1984-05-31 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59111524A JPS60254760A (en) 1984-05-31 1984-05-31 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS60254760A true JPS60254760A (en) 1985-12-16

Family

ID=14563512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59111524A Pending JPS60254760A (en) 1984-05-31 1984-05-31 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS60254760A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100369501B1 (en) * 1998-12-31 2003-03-28 앰코 테크놀로지 코리아 주식회사 Semiconductor Package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100369501B1 (en) * 1998-12-31 2003-03-28 앰코 테크놀로지 코리아 주식회사 Semiconductor Package

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