JPS6025462A - Integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the number of terminals without requiring any other test terminal by connecting a field effect transistor (FET) which has a floating gate to a terminal for normal operation. CONSTITUTION:Signals inputted to terminals 1 and 2 of an integrated circuit L which is a one-chip microcomputer are supplied to input circuits 3 and 9 which serve as a buffer through lines 10 and 11 and are used for the arithmetic operation of the microcomputer. When the integrated circuit L is placed in test mode, a voltage having a larger absolute value than a normal operating voltage is applied between the terminals 1 and 2. Consequently, a change is injected into the FET5, which turns on, so that the voltage at a connection point 12 exceeds the threshold value of a level discriminating circuit 7. Therefore, a line 14 goes up to a high level and the integrated circuit L performs predetermined operation in test mode.

Description

TECHNICAL FIELD This invention relates to integrated circuits, such as large scale integrated circuits such as 1-chip microcomputers and memories.

BACKGROUND ART In such integrated circuits, it is desirable to reduce the number of terminals as much as possible. In the prior art, an integrated circuit, such as a one-chip microcomputer, is provided with test terminals for testing its operation.

A predetermined signal representing, for example, logic "1" is applied to this test terminal +, thereby performing a test mode operation in which the mask read only memory is dumped and its contents are read. In such prior art, it is necessary to separately provide a test terminal in addition to the two terminals for normal operation.

OBJECT It is an object of the present invention to provide an integrated circuit with a reduced number of terminals.

Example FIG. 1 is a block diagram of one embodiment of the present invention.

It has an integrated circuit LU, which is a one-chip microcomputer, and has terminals 1.2 which are used for normal operation. The signals from these terminals 1 and 2 are on lines to and 11.
Input circuits 3 and 9 that function as buffers etc.
are given to each. The signals from the input circuit 3.9 are used for the arithmetic operations of the microcomputer. i':1' on line 11.

A field effect transistor 5 having a floating gate 1 structure and a depletion type field effect transistor 4 are connected in series. These field effect transistors 4
, 5 connection point level discrimination circuit 7 having a level discrimination function
given to. It is connected to the floating gate 13 of the signal from line 10.

During normal operation, a voltage of about 5 .mu.m at most is applied to terminal 1.2. As a result, input circuit 3
, 9, an arithmetic operation is performed in response to the outputs from . At this time, the field effect transistor 5 remains cut off, so that the connection point 12 is at the ground level. The voltage at the connection point 12 at this time is less than the threshold value of the level discrimination circuit 7, and therefore the signal led out to the line 14 is at the halo level. With line 14 at low seal, normal operation continues as described above.

To enter the integrated circuit test mode, a voltage, for example 20 V, having an absolute value greater than 1° voltage (eg, 5 V across the terminals as described above) is applied to the terminals. The duration of the application of the voltage 20V from the terminal 1 to the floating gate 13 via the line 10 may be, for example, 20 msec, thereby injecting charges (i.e. electrons or holes) into the field effect transistor 5 and making it conductive. Next door.

The conductive state is maintained. For example, the voltage of 20V remains applied to the terminal 2 as described above. As a result, the voltage at the connection point 12 becomes equal to or higher than the threshold value of the level discrimination circuit 7, and the voltage at the line 14 becomes an extremely high level.

Therefore, a predetermined operation is performed in the integrated circuit test mode.The predetermined operation in this test mode is, for example, an operation of dumping a mask read-only memory and reading its contents. To enter test mode in this way, terminals 2. A voltage high enough to cause the peak effect transistor 5 to undergo avalanche injection is applied, and at the same time, a voltage sufficient to draw the injected charge to the terminal IK to the floating gate 13 is applied. As a result, charge is accumulated in the 70-signature 13, and it becomes conductive as described above.

The threshold value of the level discrimination circuit 7 is set to '1vth, and the mutual conductance of the field effect transistor 4.5 is β4. β5
(g, m) and the voltage 't:Vin applied to the terminal 2 when operating in the test mode, the mutual conductance β4. β5 is selected so as to satisfy the first equation.

β5 V th (−・V i n −(1) β4 The field effect transistor 5 has a so-called EE (Elec
It may have a trically Erasable structure. As a result, after the predetermined operation in the test mode is completed, the charge is fully injected from the terminal 1 into the 70-ring gate 13, and the circuit is cut off.

In another embodiment of the invention, the field effect transistor 5 is switched into the switching state 451! by irradiation with ultraviolet light.
The configuration may be such that it can be completely erased.

Effects As described above, according to the present invention, no additional test terminals are required to perform predetermined operations in the test mode, so the number of terminals can be reduced.

[Brief explanation of drawings]

The drawing is an electrical circuit diagram of an embodiment of the present invention. 1.2...terminal, 3,9...input circuit, 4...depletion type field effect transistor, 5...field effect transistor having floating gate structure,
7...Level discrimination circuit agent Patent attorney Kei Nishi

Claims (1)

[Claims] A field effect transistor having a floating gate connected to a terminal used for normal operation is provided, and the field effect transistor has a voltage on the floating gate having an absolute value larger than that during the normal operation. 1. An integrated circuit that changes its switching mode when a voltage of 100% is applied and charges are injected, and performs a predetermined operation as a test mode in response to the output of the field effect transistor.