JPS60253955A - Propriety discriminating device for glass tube - Google Patents

Abstract

PURPOSE:To perform discrimination accurately and speedily by providing a sealed-part front and a sealed-part flank propriety discriminating means which convert a silhouette image obtained with transmitted light into a binary signal and discriminating said image, and discriminating a nondefective article when both means output propriety discriminating result. CONSTITUTION:A light source 2 irradiates a one-end sealed part 1a with light through a light diffusing plate 3 from the other end opening part of a glass tube 1 which has one end sealed almost hemispherically, and a light source 4 irradiates the sealed part 1a of the tube 1 with light through a light diffusing plate 5 from the outside of one flank. A linear image sensor 6 is arranged in front of the sealed part 1a, and a linear image sensor 7 is arranged at the outside of the other flank of the sealed part 1a. Output signals of the sensors 6 and 7 are converted into a binary signal by setting threshold values respectively and their binary-coded signals are used to discriminate whether the surface and flank of the sealed part are nondefective or not. Thus, the discrimination is made accurately and speedily and automation is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a device for determining the quality of glass tubes of lamps used in automobile headlights and the like.

[Technical background of the invention and its problems] For example, lamps used in automobile headlights are made by sealing one end of a glass tube, inserting a filament electrode from the other end and sealing it, with one end facing the front. It is ready to be installed. For this reason, the sealing portion on one end side of the glass duplex needs to have a proper shape designed to obtain good light distribution characteristics. Therefore, it is important to inspect the sealed portion at one end of the glass tube to determine whether it is good or bad. However, in the past, pass/fail was determined by visual inspection by an expert, which resulted in variations in non-defective products and the possibility of misjudgment.Furthermore, the inspection took a long time and required a lot of manpower to carry out on the lamp manufacturing line. There was a problem.

[Purpose of the Invention] This invention was made to solve these problems, and provides a device for determining the quality of glass tubes that can accurately and quickly determine the quality of glass tubes, and that can be easily automated in, for example, a lamp manufacturing line. The purpose is to provide

[Summary of the Invention] This invention uses a pair of one-dimensional image sensors to move each line on an arbitrary line in a silhouette image obtained by light transmitted from the front of the sealed portion and light transmitted from the side of the sealed portion of a glass tube whose one end is sealed. The output signal from each image sensor is binarized at a threshold level set by a pair of binarization circuits, and the range of imaging by each image sensor is set by a pair of imaging range setting means. The binarized signal from one of the binarization circuits in the imaging range set by one imaging range setting means is inputted to determine the quality of the front surface of the sealing part, and the imaging range set by the other imaging range setting means is set. The binarized signal from the other binarization circuit is manually used to determine the quality of the side surface of the sealing part, and when both pass/fail determinations are positive, the glass tube is determined to be non-defective.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a glass tube whose one end is sealed and molded into a substantially hemispherical shape, and 2 is a glass tube that irradiates light from the other end opening of the glass tube 1 to the end sealing portion 1a via a light diffusing plate 3. A light source 1 and a second light source 4 irradiate light onto the sealed portion 1a of the glass tube 1 from one side outside through a light diffusing plate 5. A first one-dimensional image sensor 6 is disposed in front of the sealing part 1a of the glass tube 1, and a second one-dimensional image sensor 6 is disposed on the outside of the other side of the sealing part 1a of the glass tube 1.
A one-dimensional image sensor 7 is arranged. The first image sensor 6 includes a clock generation circuit '8, an image sensor element 9, a driver circuit 10 for driving the image sensor element 9, a synchronization signal generation circuit 11, and a hold circuit 12. drives the image sensor element 9 in response to the clock signal from the clock generation circuit 8, and outputs the output signal from the image sensor element 9 to the hold circuit 12.
I'm holding H. Further, the synchronization signal generation circuit 11
generates a synchronizing signal in response to a clock signal from the clock generating circuit 8.

Then, an arbitrary line, for example, the center line, in the silhouette image obtained by the transmitted light from the other end of the glass tube 1 is imaged by the image sensor element 9 through the lens 13. Said second image sensor
Similarly to the first image sensor 6, the image sensor 7 is also provided with a clock generation circuit 14, an image sensor element 15, a driver circuit 16 for driving the image sensor element 15, a synchronization signal generation circuit 17, and a hold circuit 18. The driver circuit 16 drives the image sensor element 15 in response to the clock signal from the clock generation circuit 14, and the output signal from the image sensor element 15 is temporarily held in the hold circuit 18. Further, the synchronization signal generation circuit 17 is connected to the clock generation circuit 1.
A synchronization signal is generated in response to a clock signal from 4.

Then, an arbitrary line, for example, the center line, in a silhouette image obtained by transmitted light from the outside of one side of the glass tube 1 is imaged by the image sensor element 15 through the lens 19. The hold circuit 12
．． The output signals from 18 are input to binarization circuits 22 and 23 via amplifiers 20 and 21, respectively. Each of the binarization circuits 22 and 23 binarizes the input signal according to the threshold level set by the level setting circuit 24 and 25, and outputs the binarized signal.

The clock signal from the clock generation circuit 8 of the first image sensor 6 and the synchronization signal from the synchronization signal generation circuit 11 are supplied to the first window setting circuit 26 forming one of the imaging range setting means, and The clock signal from the clock generation circuit 14 of the second image sensor 7 and the synchronization signal from the synchronization signal generation circuit 17 are supplied to the second window setting circuit 27 forming the other imaging range setting means. The first window setting circuit 2
6 are a pair of clock counters 28, 29, a pair of comparators 30, 31, a window start setting circuit 32, a window end setting circuit 33.2, manual OR gates 34 and 4.
It consists of a bit binary counter 35, the clock counters 28 and 29 count the clock signal from the clock generation circuit 8, and the comparator 30 compares the clock count number of the counter 28 with the clock signal set in the window start setting circuit 32. Compare the counted value and
When the clock count number reaches the set count value, an output signal is supplied from the comparator 30 to the binary counter 35 via the OR gate 34, and the comparator 31 outputs the clock count number of the counter 29 and the window end setting circuit 33. When the clock count number reaches the set count value, an output signal is supplied from the comparator 31 to the binary counter 35 via the OR gate 34. The binary counter 35 outputs a high level window signal from its QA output terminal.

Each of the counters 28, 29, and 35 is cleared by a synchronizing signal from the synchronizing signal generating circuit 11.

The second window setting circuit 27 also includes a pair of clock counters 36 similarly to the first window setting circuit 26.
．． 37, a pair of comparators 38, 39, a window start setting circuit 40, a window end setting circuit 41, 2, a manual OR gate 42, and a 4-bit binary counter 43. The clock signal is counted, and the comparator 38 compares the clock count number of the counter 3G with the count value set in the window start setting circuit 40, and when the clock count number reaches the set count value, the comparator 38 outputs the clock signal. A signal is supplied to the binary counter 43 via the OR gate 42, and the comparator 39 compares the clock count number of the counter 37 with the count value set in the window end setting circuit 41, and determines the clock count number. When the set count value is reached, an output signal from the comparator 39 is supplied to the binary counter 43 via the OR gate 42.

The binary counter 43 outputs a high level window signal from its QA output terminal.

Each of the counters 36, 37, and 43 is cleared by a synchronization signal from the synchronization signal generation circuit 17.

The binarized signal from the binarization circuit 22 and the signal from the QA output terminal of the binary counter 35 are input to the two-person AND gate 44, and the binarized signal from the binarization circuit 22 and the signal from the QA output terminal of the binary counter 35 are input to the two-person AND gate 44. A signal from the QA output terminal of the binary counter 35 and a clock signal from the clock generation circuit 8 are input to the three-man AND gate 45. Further, the binarized signals from the binarization circuit 23 and the signal from the QA output terminal of the pinary counter counter 43 are input to the two-input AND gate 46, and the signals from the binarization circuit 23 Binarized signal, the binary counter 4
The signal from the QA output terminal of No. 3 and the clock signal from the clock generation circuit 14 are input to the three-man AND gate 47.

The output signal of the AND gate 44 is supplied to a 4-bit binary counter 48, and the output signal of the AND gate 45 is
A clock signal from the clock counter 49 is supplied to the clock counter 49. Further, the output signal of the AND gate 46 is supplied to a 4-bit binary counter 50, and the clock signal from the AND gate 47 is supplied to the clock counter 50.
1. A signal from the QB output terminal of the binary counter 48 is supplied to a flip-flop 52, and a count signal from the clock counter 49 is supplied to a comparator 53. The comparator 53 compares the clock count number of the clock counter 49 with the count value set in the pulse width upper limit setting circuit 54, and outputs a high level signal when the clock count number is less than the set count value, and changes the set count value. When the limit is exceeded, a low-level defective product determination signal is output.

When the flip 70 knob 52 is in a clear state, it outputs a high level signal from its output terminal, and when it is set, it outputs a low level defective product discrimination signal from its output terminal.

The output signal from the output terminal of the flip-flop 52 and the output signal from the comparator 53 are supplied to a Nant gate 55, and the output of the Nant gate 55 is outputted via a NOR gate 56. The binary counter 48, the clock counter 49 and the flip-flop 52
is cleared by the synchronization signal from the synchronization signal generation circuit 11. The binary counter 48, the clock counter 49, the Noritsu flop 52, the comparator 53, the pulse width upper limit setting circuit 54, and the Nant gate 55
constitutes a means for determining whether the front side of the sealing portion is good or bad.

The signal from the QB output terminal of the binary counter 50 is supplied to the 7-lip flop 57, and the count signal of the clock counter 51 is supplied to the comparators 58 and 5.
9. The comparator 58 compares the clock count number of the clock counter 51 with the count value set in the pulse width upper limit setting circuit 60, and outputs a high level signal when the clock count number is less than the set count value, and changes the set count value. When it exceeds the pulse width, the comparator 59 outputs a low-level defective product discrimination signal, and also compares the clock count number of the clock counter 51 with the count value set in the pulse width lower limit setting circuit 61, and determines that the clock count number is When the count value is greater than or equal to the set count value, a high level signal is output, and when it is smaller than the set count value, a low level defective product determination signal is output.

When the flip-flop 57 is in a clear state, it outputs a high level signal from its d output terminal, and when set, it outputs a low level defective product discrimination signal from its d output terminal.

The output signals from both the comparators 58 and 59 are supplied to a two-man AND gate 62. The output signal from the d output terminal of the flip-flop 57 and the output signal from the AND gate 62 are supplied to a Nant gate 63, and the output of the Nant gate 63 is outputted via the NOR gate 56.

The binary counter 50, click counter 51 and flip-flop 57 are cleared by the synchronization signal from the synchronization signal generation circuit 17. The binary counter 50, the clock counter 51, the flip-flop 57, the comparators 58, 59, and the pulse width upper limit setting circuit 60. Pulse width lower limit setting circuit 61, AND gate 62
The Nandt gate 63 constitutes a means for determining the quality of the side surface of the sealing portion.

The output of the Noah gate 56 is supplied, for example, to a tube reject device (not shown) in a lamp manufacturing line, and when the output is at a low level, the tube reject device operates to reject the glass tube under inspection from the line. ing.

Next, the operation of the apparatus according to the embodiment of the present invention constructed as described above will be described.

Now, suppose that the first image sensor 6 inspects the front silhouette image of the sealed portion 1a of the glass tube 1 along the scanning line 11 along the center line.
) When the image is a ring-shaped silhouette image with a clear outline, the input signal to the binarization circuit 22 becomes a signal at a level higher than the threshold level only at that ring portion, and the binarization circuit as shown in the figure 22 outputs are obtained. On the other hand, in the first window setting circuit 26, the clock counters 28 and 29 count the clock signals from the clock generation circuit 8, and when the count number of the counter 28 reaches the set count value of the window start setting circuit 32, a signal is sent from the comparator 30. is output, and the binary counter 35 performs one count operation based on the signal. Therefore, the counter 35 counts "1", and the Q
The A ratio output becomes high level. Thereafter, when the count number of the counter 29 reaches the set count value of the window end setting circuit 33, a signal is output from the comparator 31,
In response to this signal, the binary counter 35 performs the counting operation again. As a result, the counter 35 counts "2", and the QA ratio output is inverted to low level. That is, at this time, although not shown, the QB ratio output becomes high level. Therefore, the QA of the binary counter 35
If the period during which the specific output is at a high level, that is, the output period of the window signal, is set in advance so that it occurs when scanning inside the ring portions on both sides as shown in the figure, the output period as shown in Fig. 2 (a) can be obtained. In this case, the AND gate does not hold true for any of the AND gates 44.45, so the counter 48.49
None of these will ever work. Therefore, the d output of the flip-flop 52 and the output of the comparator 53 are both at a high level, the output of the NOR gate 56 is at a high level, and the tube reject device does not operate. That is, the front inspection of the sealing portion 1a in this case determines that the product is non-defective. In addition, when a multiple ring-shaped Silera 1-image appears as shown in FIG. 2(b), the input signal to the binarization circuit 22 exceeds the threshold level at several points during the window signal generation period. During the period in which this threshold level is exceeded, the logical product of the two gates 44 and 45 is established, and the binary counter 48 counts the number exceeding the threshold level, and the clock counter 49 counts the number exceeding the threshold level. Count the number of corresponding clock signals.

When the binary counter 48 counts "2", the QB ratio output is set to high level, and the flip-flop 52 is set. However, Noritsubu flop 52
d output is inverted to low level. Further, the count number of the clock counter 49 is compared with the pulse width upper limit value by the comparator 53, and when the count number exceeds the pulse width upper limit value, the output of the comparator 53 is inverted to low level. Therefore, if the threshold level is exceeded in at least two places during the window signal generation period, or if the number of clock signals generated during the period in which the threshold level is exceeded even at one point exceeds the pulse width upper limit value. When such a situation occurs, the output of the Nant gate 55 is inverted to high level, and a low level reject signal is output from the Noah gate 56. A defect on the front side of the sealing part is determined, and the reject device removes the glass tube. Rejected.

Further, if the second image sensor 7 inspects the silhouette image of the side surface of the sealed portion 1a of the glass tube 1 along the scanning line 11 along the center line, for example, the image shown in FIG.
As shown in a), the width of the dark area is uniform and the horizontal U has a clean outline.
In the case of a character-shaped silhouette image, the input signal to the binarization circuit 23 becomes a signal higher than the threshold level only in one dark area, and the input signal to the binarization circuit 23 as shown in the figure becomes a signal higher than the threshold level.
Three outputs are obtained. On the other hand, the second window setting circuit 27
In this case, clock counters 36 and 37 are clock generation circuit 1.
4, and when the count number of the counter 36 reaches the set count value of the window start setting circuit 40, a signal is output from the comparator 38,
The binary counter 43 performs a counting operation according to the signal.

As a result, the counter 43 counts "1", and its QA ratio output becomes high level. Thereafter, when the count number of the counter 37 reaches the set count value of the window end setting circuit 41, a signal is output from the comparator 39, and the binary counter 43 performs the counting operation again based on the signal. However, the counter 43 is "2".
” is counted, and its QA ratio output is inverted to low level. In other words, although not shown at this time, Q
B ratio output becomes high level. Therefore, the period in which the QA ratio output of the binary counter 43 is at a high level, that is, the period in which the window signal is output, is determined by the sealing part 1 as shown in the figure.
If the setting is made in advance so that the silhouette image of a is included in between, a high-level binary signal is input to the counter 50 via the AND gate 46 only once in the case shown in FIG. 3(a). Therefore, the counter 50 counts "1".

However, even if the counter 50 counts "1", the Q
Since the e ratio output is maintained at a low level, the flip-flop 57 maintains a reset state and its Q output maintains a high level state. On the other hand, the AND gate 47 also opens its gate only during the period when the high-level binary signal is input from the binarization circuit 23, and the clock signal is supplied to the clock counter 51 via the AND gate 47 during that period.

Therefore, the counter 51 counts the number of clock signals during this period. Therefore, the set count values of both setting circuits 60 and 61 are set in advance so that the number of clock counts during this period is between the set count value of the pulse width upper limit setting circuit 60 and the set count value of the pulse width lower limit setting circuit 61. If set, the pulse width will always be between the upper limit count value and the lower limit pulse width count value in the case shown in FIG. The output of the AND gate 62 becomes high level. Therefore, the output of the Nant gate 63 remains at a low level, the output of the NOR gate 56 remains at a high level, and the tube reject device does not operate. That is, the side surface inspection of the sealed portion 1a in this case is determined to be a non-defective product. Furthermore, if an abnormally wide silhouette image appears in the sealing portion 1a as shown in FIG. becomes wider, and therefore, although the binary counter 50 only counts "1", the clock counter 51 counts the number of clock signals exceeding the count value set by the pulse width upper limit setting circuit 60.

As a result, the output of the comparator 58 is inverted to low level, the output of the Nant gate 63 becomes high level, and the NOR gate 56 outputs a low level eject signal. Then, it is determined that the side surface of the sealing portion is defective, and the reject device rejects the glass tube.

Furthermore, if multiple silhouette images appear in the sealing portion 1a as shown in FIG. 3(C), the input signal to the binarization circuit 23 exceeds the threshold level at multiple points during the window signal generation period The binary counter 50 counts the number of clock signals exceeding the threshold level, and the clock counter 51 counts the number of clock signals corresponding to the total period exceeding the threshold level. When the binary counter 50 counts "2", the QB ratio output is set to high level, and the flip-flop 57 is set. Therefore, the d output of the Noritsubu flop 57 is inverted to low level. Further, the count number of the clock counter 51 is compared with the pulse width upper limit value and the pulse width lower limit value by comparators 58 and 59, and when the count number exceeds the pulse width upper limit value, the output of the comparator 58 is inverted to a low level. Therefore, if the threshold level is exceeded in at least two places during the window signal generation period, or if the number of clock signals generated in the total period exceeding the threshold level exceeds the pulse width upper limit, the Figure 3 (b
), the output of the Nant gate 63 is inverted to high level, and the NOR gate 56 outputs a low level or reject signal, and it is determined that there is a defect on the side surface of the sealing part, and the reject device removes the glass. Tube is rejected.

In this way, the front silhouette image and the side silhouette image of the sealed portion 1a in the glass tube 1 are inspected using a pair of image sensors 6 and 7, and the set values are set for the number and width of dark areas in either silhouette image. If a different abnormality is observed, the product is determined to be defective and rejected from the line, so unlike in the past, which relied on human visual inspection, the standard for discrimination is always constant and accurate discrimination is possible. This allows for quick identification. Therefore, automation can be easily realized in the lamp manufacturing line and productivity can be improved.

In the above embodiment, the quality of the sealing portion 1a is determined based on both the number of high-level binary signals generated during the window signal generation period and the number of clocks in the total time width of the binary signals. However, it is not necessarily limited to this, and only one of them may be used depending on the purpose.

Also, depending on the lamp, for example, one with a thick sealing part or one with multiple stages may be considered good, but in such cases, the count number and clock signal for determining good quality of the high-level binary signal are also used. If the set count number for determining non-defective products is appropriately set, it is possible to easily determine whether the product is good or bad.

Further, in the embodiment described above, the quality determination is made by scanning the center line of the silhouette image, but the invention is not necessarily limited to this, and there is no problem even if the image is slightly deviated from the center line. Furthermore, if the glass tube is rotated about its longitudinal center axis and the pass/fail determination is performed by scanning the center line of the silhouette image at multiple locations at the rotational position, the entire glass tube can be scanned. It is possible to judge whether the product is good or bad, and even more accurate judgment can be made.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a device for determining the quality of glass tubes that can accurately and quickly determine the quality of glass tubes, and that can be easily automated in, for example, a lamp manufacturing line. .

[Brief explanation of drawings]

The figures show an embodiment of the present invention. Fig. 1 is a block diagram showing the circuit configuration, Fig. 2 is a diagram showing signal waveforms of each part in the process of determining the quality of the front of the sealing part, and Fig. 3 is a diagram showing the sealing part. It is a figure which shows the signal waveform of each part in the quality determination process of the part side surface. 1...Glass tube, 2.4...Light source, 6.7.
・・One-dimensional image sensor-122, 23 ・・Binarization circuit, 26.27 ・・Window setting circuit, 48.5
0...Binary counter, 49.51...Clock counter, 52.57...Flip-flop, 53.
58... Comparator, 54.6o... Pulse width upper limit setting circuit, 61... Pulse width lower limit setting circuit. Applicant's representative Patent attorney Takehiko Suzue No. 2 (a) (49) Kisara Kawanto (b)

Claims (4)

[Claims] (1) A pair of one-dimensional images captured on arbitrary lines in a silhouette image obtained by a glass tube whose one end is sealed and the light transmitted from the front side of the sealing part and the light transmitted from the side of the sealing part of this glass tube. sensor and
a pair of binarization circuits that respectively set threshold levels and binarize the output signals from each of the image sensors; a pair of imaging range setting means that respectively set the range of imaging by each of the image sensors; Sealing part front quality determining means for determining the quality of the sealing part front surface by inputting a binary signal from one of the binary circuits in the imaging range by one imaging range setting means, and the other imaging range setting means a sealing part side surface quality determining means for inputting a binary signal from the other binary circuit in the imaging range according to the method and determining whether the side surface of the sealing part is good or bad; A device for determining the quality of a glass tube, characterized in that the glass tube is determined to be a non-defective product when the following steps are performed. (2) The sealing part front side quality determination means and the sealing part side quality determination means are two
The device for determining the quality of a glass tube according to claim 1, wherein the quality of the front surface of the sealed portion and the side surface of the sealed portion is determined based on the total time width of the value signal. (3) The sealing part front side quality determination means and the sealing part side quality determination means are two
2. The device for determining the quality of a glass tube according to claim 1, wherein the quality of the front surface of the sealed portion and the side surface of the sealed portion is determined based on the number of value signals. (4) The sealing part front side quality determination means and the sealing part side quality determination means are two
The quality determination of the glass tube according to claim 1, characterized in that the quality determination of the front side of the sealed part and the side face of the sealed part is performed based on both the total time width of the digitized signal and the number of the binarized signals. Device.