JPS60253330A - Pcm coding and decoding device containing two-wire/four-wire conversion function - Google Patents

Abstract

PURPOSE:To attain the compensation of delay with high accuracy and to obtain a satisfactory return loss by controlling the signal delay at a circuit part having a short sampling cycle. CONSTITUTION:The PCM signal supplied from a four-wire type input line 115 is converted into a linear PCM signal by an expander 112 and then into a digital signal by a digital filter 110. This digital signal is partially demodulated into an analog signal via a digital filter 108, an over-sample type D/A converter 107 and a post filter 106. This analog signal is partially sent to a two-wire type line 206 serving as a subscriber line via a termination impedance 205. While the analog signal C sent from a subscriber line 206 is converted into a digital signal by an over-sample type A/D converter 102 via an amplifier 203 and a pre-filter 101 and applied to a subtractor 113 via a digital filter 103. The output of the subtractor 113 is applied to a digital filter 104 with only the signal component given from the line 206 and then converted into a linear PCM signal. This PCM signal is converted into a nonlinear PCM signal by a compressor 105 and sent to a four- wire type output line 114.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a PCM code decoder having a two-line and four-line conversion function;
More specifically, it decodes the PCM signal input to the 4-wire input line used in the subscriber circuit of the digital converter, converts it into an analog signal, and sends it to the 2-wire line that is the subscriber line. , a code that encodes the analog signal from the two-wire subscriber line into a PCM signal and sends it to the four-wire transmission line;
This relates to decoders (codecs).

[Background of the invention]

A subscriber circuit for telephone conversion requires a 2-wire/4-wire conversion function, but this function has conventionally been achieved using a hybrid transformer. However, with recent advances in semiconductor technology, so-called electronic hybrids that implement a 2-wire and 4-wire conversion function using filters and subtracters have become commonplace. On the other hand, PCM code decoders are also becoming more and more integrated into single-chip LSIs, and it is becoming possible to incorporate other functions necessary for subscriber circuits onto the same chip. Furthermore, at a stage when LSI integration becomes highly integrated, it becomes possible to implement most of the PCM code decoder using digital signal processing technology. (Hereinafter, such a PCM code decoder will be referred to as a digital CODEC).

When adding a 2-wire/4-wire conversion function configured using digital signal processing technology to a digital CODEC, delay compensation becomes a problem. FIG. 1 is a diagram for explaining this problem, and shows one configuration of a digital CODEC. In FIG. 1, 101 and 106 are pre- and post-filters, respectively, 102 and 107 are oversampled A/D and D/A converters whose sampling frequency is sufficiently higher than the Nyquist frequency of 8 KHz for the audio band of 4 KHz, and LO3. ”,
104, 108, 109, 110 are all filters,
105 and 112 are compressors and expanders, respectively, and 113 is a subtracter. In the figure, an input analog signal (audio signal) has high frequency components cut off by a prefilter 101 and is A/D converted. The output of the A/D converter 102 is normally a signal sampled at 512 KHz or higher, and in order to actually send it out as an output PCM signal, this is sampled at 8 KHz.
It is necessary to convert it into a sampled signal. This conversion is usually performed in two stages. Filter 103
, 104 are used for sampling frequency conversion, and among these, the filter 104 is mainly used for the A/D converter and 1
Taking into consideration the characteristics of GODEC 03, the signal that also has the role of realizing the frequency characteristics necessary for GODEC (for example, CCITT G712.) is converted into an analog signal (audio signal) through the reverse conversion process. Digital C0DE with the above configuration
In the 2#14 line conversion function in C, the output of the D/A converter 106 appears on the A/D converter 101 side, as will be explained in detail later. As shown, this is achieved by generating the same signal as the signal coming from the filter 110 output via the filter 109 through the above-mentioned D/A and A/D conversion, and subtracting it from the filter 103 output. Therefore, in this case, the frequency characteristics H, N(f) of the filter 109 are such as to cancel the signal coming from the output of the post filter 106 to the bris filter 101 via an external circuit not described here, that is, the return signal. It is necessary to have the characteristics described above in 108, 107, 106. External circuit, 101
It is necessary to comprehensively determine the characteristics of ゜102 and 103. That is, H,N(f)=H,. ,(f)・
H. , 7Cc)-Hlog(f)·Hl. 1(f)・
'1o2(f)・Hlo3(f)' Hexr
(f) is determined.

As explained above, when realizing 2-line and 4-line conversion, a new problem is the filter, especially the 103°, 108°, and
These are delays required for digital signal processing by A/D and D/A converters, and analog delays caused by filters 101 and 106. The output of filter 109 must be a signal with this signal delay compensated as much as possible. For example, the sampling frequency of the output signal of the filter 110 is set to 32K.
Hz, the method of placing a delay element on the input or output side of the filter 109 results in a minimum delay unit of about 31 μs, which makes it impossible to perform delay compensation with sufficient accuracy. It is difficult to ensure a high rate of cancellation of incoming signals.

[Purpose of the invention]

Therefore, an object of the present invention is to realize a digital CODEC having a 2-wire/4-wire conversion function with sufficient return loss using digital signal processing technology.

[Summary of the invention]

In order to achieve the above object, the present invention enables highly accurate delay compensation and obtains sufficient return loss by adjusting the signal delay in a circuit section with a high sampling frequency, that is, a short sampling period. It is something. That is, a second means is provided for converting the 4-wire input line, the 4-wire output line, and the above-mentioned 2-wire digital PCM signal into a digital PCM signal having a sampling frequency lower than the sampling frequency of the bidirectional transmission converter. A third means for converting the input PCM signal into a digital signal with a sampling frequency higher than the sampling frequency of the input PCM signal, which is arranged between the 41iiA type input line and the two-wire line in order; a fourth means for converting into a digital signal with a sampling frequency higher than the sampling frequency of the output; and a D/A converter for converting the output digital signal of the fourth means into an analog signal and applying it to the two-wire line. In order to cancel the output of the D/A converter going around the four-wire output line, a filter is provided between the output of the third means and the output of the first means. A PCM code decoder configured to subtract the output of said filter from the output of said first . The sampling frequency of the output signal of the third converting means is fl + f2, and the first . When the sum of delay times of the fourth conversion means, A/D and D/A converters is Td, fl and f2 are given.

[Embodiments of the invention]

-Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 2 is a block diagram showing the configuration of one embodiment of the PCM encoder/decoder according to the present invention.

In FIG. 2, the same components as those in FIG. 1 are given the same numbers. The PCM signal (PCM signal according to μ law) from the 4-wire input line 114 is sent to the expander 112.
is converted into a linear PCM signal by digital filter 11.
0, the sampling frequency is converted to a digital signal of 32 KHz, and a part of it is further passed through a digital filter 108.
is converted into a digital signal with a sampling frequency of 512 KHz by the delay means 201, and then sent to the oversampling type D/A converter 107. It becomes a demodulated analog signal through the Bost filter 106, and the buffer amplifier 20
4. A portion of the signal is sent out via the terminal impedance 205 to a two-wire line 206, which is a subscriber line.

On the other hand, the analog signal C from the subscriber line 206 is transmitted to the amplifier 2.
03. Via the filter 01, the oversampled A/D converter 102 converts the signal into a digital signal sampled at a sampling frequency of 512 KHz, and the digital filter 03 converts it into a digital signal with a sampling frequency of 32 KHz. Added. The subtracter 113 is for decoding the digital signal from the 4IlA type input line 115 and removing the component that has passed through the path of the blocks 101, 102 and 103 via the amplifier 204 and the terminal impedance 205. A part of the output of the digital filter 10 is delayed by the delay means 202.
, 8% filter 09 and the component d added to the subtracter 113. The output of the subtracter 113 is a linear PCM signal (sampling frequency 8 KHz) by adding only the signal component from the two-wire line to the digital filter 104.
Convert to Further, the linear PCM signal is converted by the compressor 105 into a μ-law or A-law nonlinear PCM signal, for example, and sent to a four-wire output line 115.

As described above, a delay of Td=:tl+t4+tad+tda occurs before the decoded signal goes to the encoder side from the filter 108 to the subtracter. Here, tl, i4, tad.

tda is filter 1'03, 108°A/D, respectively.
Converter 102. This is the delay time of the D/A converter 107.

Therefore, in order to remove this component, the same signal as the component must be
N filter 109. is created by the delay means 202.

Normally oversampled A/D, D/A converters are 512
A sampling frequency of KHz or higher is used, and this A/
A higher frequency clock (for example, 1024 KHz) is used for the digital filter that processes the D conversion result. Therefore, if this clock is used, the delay adjustment in the delay circuits 201 and 202 will be performed with one clock pulse period of 1 μs.
You can perform the following precisions, etc.

As a result, filter 103. 108. A/D.

D/A converters 102, 107. Pre/post filter 1
01,106. Considering each delay, etc., the sum of the delay amounts and the delay amount of the delay circuit 201 is
By adjusting the delay amount of the delay circuit 201 so that it is close to an integral multiple of the sampling period of the delay circuit 20,
2 to cancel the wraparound signal (filter 1
09 output) can be adjusted. For example, the sampling frequency of the filter 110 output.

32KHz, A/D, D/A converter sampling frequency is 512KHz, clock is 4.096MHz, filters 103, 108 . A/D.

D/, A converter, 102. IQ7. If the total delay time of the pre- and post-filters 101 and 106 is 119.5 μs, the delay circuit 201 can be controlled by a 4.096 MHz clock, so the amount of delay is 5.62 μs (23
X1/4.096X10').

therefore.

By inserting the delay circuit 201, the total delay amount is reduced to 125.1 μs.
It can be done. This value is four times the sampling period of the filter 110 output signal (1/32xlO3x4=1
25 μs), and the delay circuit 202 has a value close to 31.2 μs.
Since a delay of an integer multiple of 5 μsC = 1/32 KHz) can be given, the output of the filter 109 is 0.
．． Delay compensation can be performed with an accuracy of 1 μS.

It is clear that the delay circuit in FIG. 2 can be easily constructed using a shift register×memory or the like. In the embodiment, the delay circuit 20 is inserted on the input side of the D/A converter, but it can also be installed on the input side of the filter 108, the output side of the A/D converter, or the output side of the filter 103. may be installed in a distributed manner.

Furthermore, it goes without saying that exactly the same effect can be obtained even if the roles of the delay circuits 201 and 202 are swapped and the delay amount is finely adjusted in 202.

As explained above, according to the present invention, it is possible to compensate for signal delay with high accuracy, and to configure and realize a 2-wire 4-wire conversion function with good characteristics in a digital C0DEC-LSI, which is different from conventional The converter subscriber circuit has been made smaller and has been configured by adding a transformer or external circuit.
Economicization becomes possible.

[Brief explanation of drawings]

Fig. 1 is a diagram for explaining the problems when adding a 2-wire 4-wire conversion function to a digital GODEC, and Fig. 2 shows the configuration of an embodiment of a CODEC with a 2-wire 4-wire conversion function according to the present invention. show. Description of symbols 1ON...Prefilter, 102...A/D converter, 103-104, 108-110...Filter, 1
05...Compressor, 106...Post filter, 10
7... D/A converter, 112... Expander, 113.
...Subtractor, 201-202...Delay circuit. M1 figure

Claims (1)

[Claims] 1. An A/D converter, a first conversion means for converting the output of the A/D converter into a signal with a lower sampling frequency, and an output of the first conversion means for converting the output of the first conversion means into a signal with a lower sampling frequency. a second conversion means for converting an externally input PCM signal into a signal with a higher sampling frequency; and a third conversion means for converting an externally input PCM signal into a signal with a higher sampling frequency; a fourth converting means for converting into a signal at a sampling frequency; a D/A converter receiving the output of the fourth converting means; a filter receiving the output of the third converting means; and a filter outputting the filter output. In the PCM code decoder, the PCM code decoder has a subtraction means for subtracting from the output of the first converting means and inputting the result to the second converting means. The sampling frequency of the output signal of the third converting means is set to fl+f2, respectively. Fourth conversion means, A
/D. When the sum of the delay times of the D/A converter is Td, let fl and f2 be an integer ratio, and further Td''n/max28
In the PCM code decoder according to claim 1, by providing a delay means between the A/D converter and the first delay means or between the fourth conversion means and the D/A converter, the T.
d-n/max PCM code decoder. 3. In the PCM code decoder according to item 1 or 2, a delay circuit is provided on the input or output side of the filter means. A fourth transform M-code decoder. 4. In the PCM code decoder according to item 1, item 2, or item 3, the second conversion means includes a circuit for converting the input digital signal into a linear PCM signal, and the linear PCM signal.
It has a signal conversion circuit that converts the CM signal into a companded PCrJ signal and outputs it, and the third means converts the companded PCM signal into a linear pgM signal and converts it into a linear PC signal.
, M signal, and a circuit for converting it into the input signal of the fourth means.
PCM code decoder.