JPS6025267A - Semiconductor resistance element and usage thereof - Google Patents

Semiconductor resistance element and usage thereof

Info

Publication number
JPS6025267A
JPS6025267A JP13330483A JP13330483A JPS6025267A JP S6025267 A JPS6025267 A JP S6025267A JP 13330483 A JP13330483 A JP 13330483A JP 13330483 A JP13330483 A JP 13330483A JP S6025267 A JPS6025267 A JP S6025267A
Authority
JP
Japan
Prior art keywords
resistance
region
voltage
semiconductor
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13330483A
Other languages
Japanese (ja)
Inventor
Eigo Fuse
布施 英悟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13330483A priority Critical patent/JPS6025267A/en
Publication of JPS6025267A publication Critical patent/JPS6025267A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802Resistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain an element having high resistance and high accuracy, resistance thereof hardly changes by the applying of reverse bias voltage, by forming a plurality of only semiconductor resistance elements, voltage applied between both terminals thereof is equal, into one insular region. CONSTITUTION:In semiconductor elements 3A, 3B, 3C, 3D and 3A', 3B' consisting of P type semiconductor regions formed in insular regions 2' and 2'' composed of insulated and isolated N type semiconductors, resistance elements, voltage applied between both terminals thereof is equal, are divided into groups, and each formed in several insular region. The resistance elements having the same voltage are arranged in the insular region in the same N type semiconductor region even when resistance values differ, and the resistance elements having different voltage are disposed in the insular regions in separate N type semiconductor regions even when resistance values are equal. A resistance change by reverse bias voltage is reduced largely because reverse bias voltage between the N type insular regions and P type resistance regions reaches to zero volt at all times with the exception of components by voltage applied to resistance element themselves.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、半導体装置に用いられる半導体抵抗素子及び
その使用方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor resistance element used in a semiconductor device and a method of using the same.

〔従来技術〕[Prior art]

従来の半導体抵抗素子は、層抵抗を基本にして面積計算
で行なわれた設計に基づいて形成され、任意の回路を構
成させる場合、使用箇所に応じて、抵抗をその内に形成
するN型半導体領域(以下の説明は一導電型がN型の場
合について行なう。)の島領域を分離せず、使用される
抵抗素子すべてを同−島領域内又は同一抵抗値の素子毎
に配列されている。
Conventional semiconductor resistance elements are formed based on a design based on area calculation based on layer resistance, and when configuring an arbitrary circuit, depending on the location of use, an N-type semiconductor with which the resistance is formed is used. (The following explanation is given for the case where one conductivity type is N type.) All the resistive elements used are arranged within the same island region or for each element with the same resistance value, without separating the island regions. .

また、寄生PNP現象等不安定要素を防止するためN型
の島領域を所望回路の最高電位に接続する場合が多い。
Furthermore, in order to prevent unstable factors such as parasitic PNP phenomena, the N-type island region is often connected to the highest potential of the desired circuit.

第1図(a)は、かかる従来の半導体抵抗素子の一例の
配列を示す平面図、第1図(b)はその人−に断面図を
示したものである。第1図(a)の1はP型半導体の絶
縁分離領域であシ、2はN型半導体領域からなる島領域
、3A、 3A、 3B、 3B・、3C。
FIG. 1(a) is a plan view showing an arrangement of an example of such a conventional semiconductor resistance element, and FIG. 1(b) is a sectional view showing the arrangement. In FIG. 1(a), 1 is an insulating isolation region of a P-type semiconductor, 2 is an island region consisting of an N-type semiconductor region, and 3A, 3A, 3B, 3B., 3C.

3DはP型半導体領域からなる抵抗素子である。3D is a resistance element made of a P-type semiconductor region.

ここで、抵抗素子3A、3B、3C,3Dは抵抗値は異
なるが回路構成して使用されるときの両端に印加される
電圧は同一であシ、又、抵抗素子3Aと3Nは同一抵抗
値、3Bと3B’は同一抵抗値であるが、回路構成して
使用されるときの両端に印加される電圧は異なっている
ものとする。
Here, the resistance elements 3A, 3B, 3C, and 3D have different resistance values, but when used in a circuit configuration, the voltage applied to both ends is the same, and the resistance elements 3A and 3N have the same resistance value. , 3B and 3B' have the same resistance value, but when used in a circuit configuration, the voltages applied to both ends are different.

従来は、第1図(a)のように、島領域2内に、任意の
回路構成で使用されるすべての抵抗素子を配列させるか
、同−抵抗値毎に島領域を分けて配列(図は省略)させ
ている。又、島領域2は通常、回路の最?atN位に接
続されている。
Conventionally, as shown in FIG. 1(a), all the resistance elements used in a given circuit configuration are arranged in the island region 2, or the island regions are divided and arranged according to the resistance value (Fig. 1(a)). (omitted). Also, island region 2 is usually the topmost part of the circuit. It is connected to the atN position.

いま、島領域2が回路の最高電位である1oボルトの電
位に接続されておシ、各抵抗素子の一端は接地され、抵
抗素子3A、3B、3C,3Dには1ボルト、3A′、
3B′には2ボルトの電圧が印加されているものとする
。この状態の下では抵抗素子3A。
Now, the island region 2 is connected to a potential of 10 volts, which is the highest potential of the circuit, one end of each resistance element is grounded, and resistance elements 3A, 3B, 3C, and 3D have a voltage of 1 volt, 3A', and 3A'.
It is assumed that a voltage of 2 volts is applied to 3B'. Under this condition, the resistance element 3A.

313、3C,3Dが形成されているP型半導体領域と
、N型半導体の島領域2の間には抵抗素子の接地側の端
で10ボルト、高電位側の端で9ボルトの逆バイアス電
圧が加わることになる。同様にして、抵抗素子3八′、
3B′の接地側端には10ボルト、高電位側端で8ボル
トの逆バイアス電圧が加わることになる。
A reverse bias voltage of 10 volts at the ground side end of the resistor element and 9 volts at the high potential side end is applied between the P-type semiconductor region where 313, 3C, and 3D are formed and the N-type semiconductor island region 2. will be added. Similarly, resistive elements 38',
A reverse bias voltage of 10 volts is applied to the ground side end of 3B', and a reverse bias voltage of 8 volts is applied to the high potential side end.

このように、島領域と抵抗素子を形成している半導体領
域間に逆バイアス電圧が印加されると、高抵抗側である
抵抗領域が空間電荷領域の形成のため小さくなシ、結果
として抵抗が犬となる。この逆バイアス効果は、抵抗素
子の両端間に印加される電圧による成分と、島領域に印
加されている電圧による成分とに分けられる。
In this way, when a reverse bias voltage is applied between the island region and the semiconductor region forming the resistance element, the resistance region on the high resistance side becomes small due to the formation of a space charge region, and as a result, the resistance increases. Become a dog. This reverse bias effect is divided into a component due to the voltage applied across the resistive element and a component due to the voltage applied to the island region.

そして前者の場合は両端間電圧の変化1ボルトの変化に
対して抵抗値の変化は数%程度である。
In the former case, the change in resistance value is about several percent for a 1 volt change in the voltage across both ends.

これに対し後者の場合には、抵抗素子の両端に印加する
電圧を一定として、逆バイアス電圧1ボルトに対して、
数〜数十パーセントと大きく変化する。もちろん、この
抵抗変化は層抵抗値の大なる程、従って高抵抗値の抵抗
素子程その影響が大となる。
On the other hand, in the latter case, with the voltage applied across the resistance element constant, for a reverse bias voltage of 1 volt,
It varies greatly, from several to several tens of percent. Of course, the influence of this resistance change becomes greater as the layer resistance value increases, and therefore, the resistance element has a higher resistance value.

一方、近年、大規模化集積回路の低電力化に伴って極め
て精度の良い高抵抗素子が必要とされている。さらに、
この種の抵抗素子は集積密度を上げるため、素子領域も
従来と同等もしくは小さくし々ければならず、製造上、
層抵抗を大きくしなければならない状態にある。この層
抵抗を大きくして製造された高抵抗素子には数十Ω〜数
にΩの低抵抗値の抵抗素子とは異なシ前述のように逆バ
イアス電圧による抵抗変化が大きな問題となる。
On the other hand, in recent years, with the reduction in power consumption of large-scale integrated circuits, highly accurate high resistance elements are required. moreover,
In order to increase the integration density of this type of resistor element, the element area must be the same or smaller than conventional ones, and in manufacturing,
It is now necessary to increase the layer resistance. Unlike resistance elements with low resistance values of several tens of ohms to several ohms, high resistance elements manufactured with increased layer resistance have a big problem of resistance change due to reverse bias voltage, as described above.

るためになされたものであシ、抵抗領域と島領域間の逆
バイアス電圧が小さくなる構成をとることによシ、逆バ
イアス電圧印加による抵抗変化を小さくしたところの高
抵抗で高精度の半導体抵抗素子およびその使用方法を提
供することにある。
By adopting a configuration in which the reverse bias voltage between the resistive region and the island region is small, it is possible to create a high-resistance, high-precision semiconductor that reduces the resistance change due to the application of a reverse bias voltage. An object of the present invention is to provide a resistive element and a method of using the same.

〔発明の構成〕[Structure of the invention]

本第1の発明の半導体抵抗素子は、絶縁分離された一導
電型の高値域内に形成された反対導電型領域からなる半
導体抵抗素子において、両端間に印加される電圧が等し
い前記半導体抵抗素子のみを複数個一つの前記島領域内
に形成したことから構成される。
The semiconductor resistance element of the first aspect of the present invention is a semiconductor resistance element consisting of an opposite conductivity type region formed in a high voltage range of one conductivity type which is insulated and separated. A plurality of these are formed within one island region.

又、本第2の発明の半導体抵抗素子の使用方法は、前記
本第1の発明の半導体抵抗素子を、この半導体抵抗素子
の両端間に印加される電圧と等しい電圧を前記島領域に
印加して使用することから構成される。
Further, a method of using the semiconductor resistance element of the second invention includes applying a voltage equal to the voltage applied across the semiconductor resistance element of the first invention to the island region. It consists of the following:

〔実施例の説明〕[Explanation of Examples]

以下、本発明の実施例について、図面を参照して詳細に
説明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第2図は本第1の発明の一実施例の配列を示す平面図で
ある。
FIG. 2 is a plan view showing an arrangement of an embodiment of the first invention.

なお本実施例は第1図(a)、(b)の従来例に対応し
て行なわれたものであシ、同一のものには同一参照数字
を付しである。
It should be noted that this embodiment was carried out in correspondence with the conventional examples shown in FIGS. 1(a) and 1(b), and the same parts are given the same reference numerals.

本実施例は、絶縁分離されたN型半導体の島領域2′及
び2″内に形成されたP型半導体領域からなる半導体抵
抗素子3A、3B、3C,3D及び3八’、3B’にお
いて、両端間に印加される電圧が等しい抵抗素子3A、
3B、3C,3Dのグループと3A+3B’のグループ
に分けて、それぞれ別の島領域2′及び2′内に形成し
たことから構成されている。
In this embodiment, semiconductor resistance elements 3A, 3B, 3C, 3D, 38', and 3B' are composed of P-type semiconductor regions formed in isolated N-type semiconductor island regions 2' and 2''. a resistive element 3A with equal voltage applied across both ends;
It is divided into groups 3B, 3C, and 3D and groups 3A+3B' and formed in separate island areas 2' and 2', respectively.

本実施例では、前述のように、抵抗素子3A。In this embodiment, as described above, the resistor element 3A.

3B、 3C,3Dは抵抗値は異なるけれども、それぞ
れの一端は接地されておシ、(接地配線は図示していな
い。)高電圧側の端にはそれぞれ、1ボルトの電圧が印
加されておシ、抵抗素子3八′及び3B’は抵抗値はそ
れぞれ3人及び3B’と同じで、それぞれの一端は接地
されておシ、(接地配線は図示していない。)高電圧側
の端にはそれぞれ2ボルトの電圧が印加されているもの
である。
Although 3B, 3C, and 3D have different resistance values, one end of each is grounded (the ground wiring is not shown), and a voltage of 1 volt is applied to each end on the high voltage side. The resistance values of resistance elements 38' and 3B' are the same as those of 3 and 3B', respectively, and one end of each is grounded (ground wiring is not shown). are each applied with a voltage of 2 volts.

すなわち、抵抗素子両端間に印加される電圧が同一のも
のはたとえ抵抗値が異っても同一のN型半導体領域の島
領域内に配列させ、抵抗素子両端に印加される電圧が異
なる場合は抵抗値が同一でも、別のN型半導体領域の島
領域内に配列させである。
In other words, resistive elements with the same voltage applied across them are arranged in the island region of the same N-type semiconductor region even if their resistance values are different; Even if the resistance values are the same, they are arranged in an island region of another N-type semiconductor region.

次に、本第2の発明の一実施例として、前記本第1の発
明の一実施例において、それぞれの半導体抵抗素子の両
端間に印加される電圧と等しい電圧として、島領域2′
には1ボルト、島領域2″には2ボルトの電圧を印加し
て使用する場合について説明する。
Next, as an embodiment of the second invention, in the embodiment of the first invention, a voltage equal to the voltage applied across each semiconductor resistance element is applied to the island region 2'.
A case will be described in which a voltage of 1 volt is applied to the island region 2'' and a voltage of 2 volts is applied to the island region 2''.

本実施例によると、前記のや件から、N型の島領域とP
型の抵抗領域間の逆バイアス電圧は、抵抗素子自身に印
加されている電圧による成分を除いては、常に零ボルト
となるので、大幅に逆バイアス電圧による抵抗変化が小
さくなシ、高抵抗で高精度の半導体抵抗素子を得ること
ができる。
According to this embodiment, due to the above-mentioned circumstances, an N-type island region and a P
The reverse bias voltage between the resistive regions of the mold is always zero volts, except for the component due to the voltage applied to the resistive element itself, so the resistance change due to the reverse bias voltage is significantly small, and the resistor has high resistance. A highly accurate semiconductor resistance element can be obtained.

なお、以上の説明においては、島領域をN型半導体とし
たが、これがP型半導体であっても、本発明が適用され
ることは言うまでもない。
In the above description, the island region is an N-type semiconductor, but it goes without saying that the present invention is applicable even if the island region is a P-type semiconductor.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したとおシ、本発明の半導体抵抗素子及
びその使用方法によると、抵抗素子の両端間に印加され
る電圧と抵抗素子が形成されている島領域に印加される
電圧を同電圧となしているので、島領域と抵抗素子領域
間には、抵抗素子自体に印加される電圧による逆バイア
ス成分を除いては、逆バイアス電圧が印加されることが
無くなるので逆バイアス電圧による抵抗変化が非常に小
さくなシ、高抵抗で高精度の半導体抵抗素子が得られる
As described in detail above, according to the semiconductor resistance element and the method of using the same of the present invention, the voltage applied across the resistance element and the voltage applied to the island region where the resistance element is formed are the same voltage. Therefore, no reverse bias voltage is applied between the island region and the resistive element region, except for the reverse bias component due to the voltage applied to the resistive element itself, so there is no change in resistance due to the reverse bias voltage. A very small, high-resistance, high-precision semiconductor resistance element can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は従来の半導体抵抗素子の一例の配列を示
す平面図、第1図(b)は第1図(a)のA−A′断面
図、第2図は本発明の一実施例の配列を示す平面図であ
る。 1・・・・・・絶縁分離領域(P型半導体) 、2.2
’、 2’・・・・・・島領域(N型半導体)、3A、
 3A’、 3B、 3B’。 3C,3D・・・・・・半導体抵抗素子(P型半導体領
域)。 第2図
FIG. 1(a) is a plan view showing an arrangement of an example of a conventional semiconductor resistance element, FIG. 1(b) is a sectional view taken along line A-A' in FIG. 1(a), and FIG. FIG. 3 is a plan view showing the arrangement of the embodiment. 1...Insulating isolation region (P-type semiconductor), 2.2
', 2'...Island region (N-type semiconductor), 3A,
3A', 3B, 3B'. 3C, 3D... Semiconductor resistance element (P-type semiconductor region). Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁分離された一導電型の島領域内に形成された
反対導電型領域からなる半導体抵抗素子において、両端
間に印加される電圧が等しい前記半導体抵抗素子のみを
複数個一つの前記島領域内に形成したことを特徴とする
半導体抵抗素子。
(1) In a semiconductor resistance element consisting of an opposite conductivity type region formed in an isolated island region of one conductivity type, a plurality of semiconductor resistance elements having the same voltage applied between both ends are connected to one island. A semiconductor resistance element characterized in that it is formed within a region.
(2)絶縁分離された一導電型の島領域内に形成された
反対導電型領域からなる半導体抵抗素子において、両端
間に印加される電圧が等しい前記半導体抵抗素子のみを
複数個一つの前記島領域内に形成してなる半導体抵抗素
子を、該半導体抵抗素子の両端間に印加される電圧と等
しい電圧を前記島領域に印加して使用することを特徴と
する半導体抵抗素子の使用方法。
(2) In a semiconductor resistance element consisting of an opposite conductivity type region formed in an isolated island region of one conductivity type, a plurality of semiconductor resistance elements having the same voltage applied between both ends are connected to one island. 1. A method of using a semiconductor resistance element, characterized in that a semiconductor resistance element formed within a region is used by applying a voltage equal to the voltage applied between both ends of the semiconductor resistance element to the island region.
JP13330483A 1983-07-21 1983-07-21 Semiconductor resistance element and usage thereof Pending JPS6025267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13330483A JPS6025267A (en) 1983-07-21 1983-07-21 Semiconductor resistance element and usage thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13330483A JPS6025267A (en) 1983-07-21 1983-07-21 Semiconductor resistance element and usage thereof

Publications (1)

Publication Number Publication Date
JPS6025267A true JPS6025267A (en) 1985-02-08

Family

ID=15101530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13330483A Pending JPS6025267A (en) 1983-07-21 1983-07-21 Semiconductor resistance element and usage thereof

Country Status (1)

Country Link
JP (1) JPS6025267A (en)

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