JPS60251470A - Vector data processor - Google Patents

Abstract

PURPOSE:To attain plural arithmetic executions by one vector arithmetic instruction by executing an optional arithmetic for a specific element in vector data having a long vector length in accordance with the element. CONSTITUTION:Operators such as modification bits M1-M3 of R1-R3 parts, an instruction conversion code C and a command Ci are added to the R4 part of a vector instruction. In a pipe-line operation stage, respective elements of data A and that of data B are read out from a vector register specified by the R3 part of the vector instruction and a register specified by the R2 part respectively to a stage register 1 for arithmetic stages. Then, the operator is read out from the vector register specified by the R4 part of the vector instruction to the register 1 in accordance with the element and sent to an arithmetic unt 2 and arithmetic specified by the operator is executed in accordance with respective elements.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Field of Application The present invention is directed to a vector data processing method in which a plurality of elements are sequentially processed using a single instruction, in which an arbitrary operation can be performed on each element. The present invention relates to a vector data processing device that has functions that can perform the following functions.

A general vector data processing device processes a large amount of element data using a single vector instruction.
IMD(Single In5tractton Mu
This is data processing means belonging to the ltipleData) format.

In this vector data processing method, in order to speed up processing, a vector register is provided between the main memory and the arithmetic pipeline, and an access pipeline (load/processor) is provided between the main memory and the vector register. A store pipeline) is provided, and element data to be processed is loaded from the main memory to the vector register, or processing results are stored in the main memory, independently of the processing in the arithmetic pipeline.

Actual calculations can be performed only with the vector registers using a plurality of calculation pipelines.

In such a vector data processing device, when it is necessary to repeat an operation such as executing another operation on a specific group of elements while executing a vector operation instruction on vector data with a long vector length, It was necessary to divide the data into multiple vector instructions and execute them.

On the other hand, in a normal vector data processing device, a mask register is provided for each element of the vector register, and when executing an actual vector operation,
There is a function of determining validity/invalidity of calculations for the element based on mask data for the element.

Therefore, by focusing on the masking function for each element in the vector data processing device and adding a function to perform arbitrary calculations on each element, we can simply add a function to perform arbitrary calculations on each element. In addition to masking operations, so-called MIMD (Mult
, 1ple In5truction Multipl
It becomes possible to process according to the eData) function.

With such a function, for example, in image processing that processes a large amount of element data, you may want to perform multiple different types of special processing only on pixels (elements) that meet specific conditions. It is extremely useful.

Figure 4 is a flowchart showing the process of determining the type of operation (operator) for pixels that meet specific conditions when performing image processing, and applying specific operations to each pixel using that operator. FIG. 5 is a diagram showing an example of the distribution of operators applied to each pixel, obtained by the process shown in FIG. 4.

First, the operation of each step will be explained with reference to FIG.

Step 10: Perform a specific operation on each pixel, compare the result with a predetermined constant, and determine whether it is larger, smaller, or equal to 2. If larger, proceed to step 11; if equal, The process moves to step 12, and if it is smaller, the process moves to step 13.

Step 11: Using CO as the operator, store in the position of the element in the vector register specified by the R4 part of the vector operation instruction.

Step 12: Using CI as the operator, store in the position of the element in the vector register specified by R4 Bart of the vector operation instruction.

Step 13: Set the operator to C1 and store in the position of the element in the vector register specified by R4 Bart of the vector operation instruction.

Step 14: For the total pixels, step 10 above
~At the point when the processing in step 13 is completed, the vector specified by the above R4 part is created between each element of the vector register specified by the R2 part of the vector operation instruction and each element of the vector register specified by the R3 part. The operation of the operator Ci stored in the corresponding element of the register is performed on an element-by-element basis, and the operation result is stored in the position of the corresponding element of the vector register specified by the R1 part.

FIG. 5 shows an example of the operators corresponding to each pixel obtained by the processing from step 10 to step 13 in FIG. ,
○ indicates operator C2.

There has been a need for a method for effectively executing such vector data, in which the content to be calculated for each pixel is different, with a single vector calculation instruction.

Figure 2 schematically shows vector data processing according to the conventional method, where (a) shows the instruction format and (b) shows the configuration of the arithmetic circuit.

In this figure, 1 is a stage register in the calculation stage of the calculation pipeline, and 2 is a calculation unit.

R1 to R4 parts indicate each field of the vector instruction, and in this example, the vector register element (A data) specified in the R3 part and the vector register element (B data) specified in the R2 part. ) to stage register 1,
After the arithmetic unit 2 performs the operation specified by the instruction code part of the vector instruction and stores it in the stage register 1,
A case is shown in which the vector register specified in the R1 part is stored as a stage.

The R4 part is the calculation mask M, which in the conventional system is characterized in that it is limited to the function of masking calculations for the element.

(C) Problems to be Solved by the Invention Therefore, during the execution of one vector instruction, only a common operation can be executed for each element, and a specific operation cannot be performed for vector data with a long vector length. If you want to perform any operation on the element, use
It was necessary to process it with another vector instruction.

In view of the above-mentioned drawbacks of the conventional art, the present invention performs arbitrary operations on specific elements of vector data having a long vector length, and conventionally requires starting multiple vector instructions. The purpose of this invention is to provide a method that can process such cases with a single vector instruction.

((D) Means for solving the problem and this object is that, according to the present invention, when performing arithmetic operations or logical operations between vector registers or mask registers, the above vector registers are included in one vector instruction. The R4 part is provided with operators such as instruction conversion codes and command codes that perform arbitrary operations on each element of the file or mask register, or the operator is added to each element data. This is achieved by providing a method.

+e) In other words, in the present invention, for example, an instruction conversion code C and a command code Ci are added to the calculation mask function of the conventional R4 part, and when the instruction conversion code C is "1", the vector instruction is Change the code to the command code FCi corresponding to the element, and execute the process of the command code Ci for the element,
There is an advantage that vector operations can be performed on a series of vector data in the MIMD format (that is, an operation format that processes multiple instructions and multiple data when a vector instruction is activated).

(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 schematically shows vector data processing according to the present invention, in which (a) shows an instruction format and (b) shows an embodiment of an arithmetic circuit. 1.2 is the same as that explained in FIG.

The R4 part of the vector instruction to which the present invention is applied includes ■R
1 to R3 part modification bins) Ml to M3. The key point lies in the fact that n operators such as (1) instruction conversion code C9 and (2) command code are added, and are not just a simple operation mask bit M.

The meanings of the above operators are as follows: M: Operation mask bit determines validity/invalidity of operation for each element.

M1 to M3: Whether to use the element data of each part in the modification focus for each part's element/
Decide whether to use it in reverse.

C. The instruction conversion code determines whether the vector instruction code is used as the instruction code for each element, or whether it is converted into a command code Ci.

C1: Indicates a CL command among n command codes.

Now, for vector data, Xl-AiOBi, to Here, ○ indicates an operation symbol, and C indicates an operator.

Considering the case of executing the operation shown in , first, in the operation stage of the operation pipeline, each element of data A is transferred from the vector register specified by the R3 heart of the vector instruction, and each element of data B is transferred from the vector register specified by the R3 heart of the vector instruction. The vector registers specified by the R2 part of the instruction are read to the stage register 1 of each calculation stage.

Subsequently, the above-mentioned operators necessary to implement the present invention are read from the vector register specified by the R4 bit of the vector instruction into the stage register 1 in correspondence with the above-mentioned elements, and sent to the arithmetic unit 2, The above M1 to M3 bits function as control signals for the calculation gate GM, M functions as a calculation mask bit, and C and Ci function as control signals for the calculation unit 2, and the calculation specified by the above operator is executed for each element. will be done.

When implementing the present invention, it is necessary to store the above-mentioned operators corresponding to each element in the vector register designated by the above-mentioned R4 bart before executing the vector instruction.

For example, the vector data (
^, B), by executing the vector data processing to determine the operation bits corresponding to each element, as explained in FIG. Operators corresponding to elements can be stored.

Figure 3 (a) is a time chart showing the operation when vector data processing according to the present invention is executed using such an operator, and (b) is an example of the calculation result. It is a diagram shown in correspondence with elements.

(a) In the figure, tO'' tj -tm on the horizontal axis indicates the calculation cycle corresponding to each element, and P1~Pi~P
n indicates each stage in the calculation pipeline 2.

Specifically, they are: P1 stage: R3 part read stage P2 stage: R2 part read stage Pi stage: calculation stage Pn stage; R1 part write stage.

(b) In the figure, the horizontal direction shows the vector length, and the vertical direction shows the number of elements processed in one calculation cycle. Therefore, the number of elements in the vertical direction corresponds to the number of calculation pipelines in which calculations are executed in parallel.

Also, in this figure, A = logical product OR = logical sum N-logical negation EOR - Exclusive OR TRN = movement This is an example of the above command code C3.

By writing such calculation results into the vector register specified by the R1 part of the vector instruction for each calculation pipeline, a series of vector data processing by the vector instruction is completed.

In the above embodiment, an example in which an operator specifying a command code for an operation for each element is provided in a vector register different from the vector register in which vector data is stored by the R4 part of the vector operation instruction; In other words, although we explained how to specify the operator using an address different from the data, it is also possible to insert the operator into each element data by specifying the same address as the vector data that is the object of the operation. Needless to say, it is a good thing.

Furthermore, in the above embodiments, operations between vector registers have been explained as an example, but considering the gist of the present invention, there is no need to limit operations to operations between vector registers. For example, operations between vector registers and mask registers, or operations between vector registers, Needless to say, the present invention can also be applied when vector data processing is performed between registers.

Furthermore, as an operation instruction specified by command code Ci,
Logical operation instructions (A,
OR, N, EOR, etc.), but it is obvious that it can also be applied to instructions that require repeated operations.

(gl) Effects of the Invention As explained in detail above, the hector data processing device of the present invention adds R1 to R3 bits to R4 bar 1- of a vector operation instruction in addition to the conventional operation mask bit M. It is equipped with operators such as modification bit old to old, instruction conversion code C, and command code Ci, and the processing corresponding to the operator is executed for each element of the vector derivation. With one vector operation instruction, for vector data with a vector length of
It becomes possible to perform multiple operations, and has the effect of allowing extremely detailed vector data processing to be performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing an example of vector data processing according to the present invention. FIG. 2 is a diagram schematically showing an example of vector data processing using a conventional method. FIG. 3 is a time chart showing the operation when vector data processing is executed according to the present invention. FIGS. 4 and 5 are diagrams illustrating an example of the field of application of the present invention. In the drawing, 1 is a stage register of the calculation pipeline. 2 is a computing unit. M is an operation mask bit. M1-M3 are R1-R3 bit modification bit C is an instruction conversion code, and C1 is a command code. P1 to Pn are pipeline stages. 8. OR, N, EOR, TRN are commands; L10-14 are operation steps, respectively. Jia 1 Edict 2 Zucha 3 Diagram ♀ 5 Degree 1 l 1 1 j l 1 1111111 ooooooo. lθ Q---0・,C! 0---○X:Cθ o---o o:cz C)---Q ---0 ---0 ---0 0-m=〇1

Claims (1)

[Claims] (11) A vector register and/or a mask register that allows one or more banks to be accessed simultaneously;
In a vector data processing system equipped with one or more arithmetic pipelines that execute arithmetic operations between vector registers or mask registers, when executing in the arithmetic pipeline, 9. When sequentially performing operations on each element, an operator for performing arbitrary operations on each element is provided in the vector register or mask register, and N (≧1) elements are provided. A vector data processing device characterized by being able to process data as a single unit. (2) In order to perform arbitrary operations on each of the above elements, specify the operator in a vector register or mask register with an address different from the data and store it in a part of the vector register or mask register. 2. The vector data processing device according to claim 1, wherein the vector data processing device is configured to have a vector data processing device corresponding to an element by specifying the same address as the data. (3) The vector data processing device according to claim 1, wherein one or more types of codes can be specified as the operator.