JPS60247962A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a rewritable nonvolatile memory, which has high density feeling and a large area and cost thereof is low, by forming a diode connected in series with a memory cell by thin-film silicon into which not more than 50 atomic ppm boron is doped. CONSTITUTION:A wiring 32 functioning as a lower electrode in combination and amorphous silicon layers 33, 34, 35 are shaped onto an insulating substrate 31. An insulating layer 36, an electrode 37, a memory 38 and a wiring 39 functioning as an upper electrode in combination are formed onto the layer 35. An amorphous silicon layer in 100Angstrom -1mum into which not less than 500 atomic ppm phosphorus or arsenic is doped is used as the layer 33, and an amorphous silicon layer in 1,000Angstrom -10mum into which not more than 50 atomic ppm boron is doped, or not more than 50 atomic ppm phosphorus or arsenic is doped or no impurity is doped is employed as the layer 34. An amorphous silicon layer of 100Angstrom -1mum into which not less than 100 atomic ppm boron is doped is used as the layer 35.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a chalcogenide memory element utilizing a crystal-amorphous phase transition, published patent publication (A) 1987-9070.
The memory switch (hereinafter abbreviated as M-SS memory) and the MNOS diode memory (IEICE technical report, 5SD85-28, 25 (1985)), etc., are electrically connected in series with the memory element. The present invention relates to a matrix array semiconductor device in which one element is a diode.

[Prior art]

Conventionally, a chalcogenide memory matrix array is composed of a matrix in which one element is the memory and a gouiode connected in series with the memory.
Further, the MEC SS memory has a matrix array configuration in which one element is the memory and a semiconductor switch such as an MO8 type switch connected in series with the memory. Figure 1 shows chalcogenide memory (M) in the memory element.
and a 4x4 matrix circuit of diodes. Conventionally,
The cross section of one element of the chalcogenide memory and diode matrix array is shown in FIG. 2, as shown in FIG. f& type layer 24 forming a PN junction diode. P layer 25. P type car L26 for isolating each element. Insulating layer 26. Chalcogenide memory electrode 27. Chalcogenide memory 28. It consists of wiring 29. A 4-element circuit is shown at the top of Figure 2.

In the chalcogenide memory matrix array, diodes and chalcogenide memories are arranged in a plane, so each element occupies a large area, making it difficult to achieve high integration.
5) The process is complicated.

In addition, since the polarity of electric signals for writing and erasing data in the memory is opposite to the polarity of MEC SS memory, it has been considered difficult to use a matrix array using diodes.

The present invention eliminates such drawbacks by using a diode made of amorphous silicon containing 1 to 30 atomic percent of hydrogen or halogen formed by plasma CVD method. The structure in which the diodes are stacked constitutes one element of a matrix array, and the area occupied by the element is reduced. At the same time, the diode can be formed at low cost, and each element can be easily isolated. , is intended to provide a matrix array of MISS memory and diodes.

Hereinafter, the present invention will be explained in detail using Examples 1 and 2.

FIG. 5(α) shows a cross-sectional view of one element of the chalcogenide memory matrix array of Example 1 of the present invention. 51 is an insulating substrate made of glass, quartz, ceramic, plastic, etc.; 32 is an aluminum (At) chromium (Cr) substrate;
) *Molybdenum (Mo), Tungsten (W)l Nichrome (N1-Or), Aluminum Silicon (At-st
).

Aluminum silicon IRCAt-8i-Ou) 9
Tin oxide (s no 2), indium tin oxide (T
.

), lower electrode/wiring made of conductive material such as gold (Au), platinum (PT), etc., 55, 54.55 is plasma OV
D, an amorphous silicon layer formed in the same process by sputtering etc., 35 is an amorphous silicon layer (hereinafter referred to as n layer) of 1ooX to 1μ doped with phosphorus or arsenic at 500 atoms PPm or more; 64 is Boro 7f50 atom #'i P
Doped with P m or less or Su/or Arsenic 5
65 is an amorphous silicon layer (hereinafter abbreviated as 1 layer) every 1000λ to 10μ doped with 0 atoms P'Pm or less, or doped with phosphorus or arsenic 50 atoms PPm or less, or undoped. Boron 100JJX child number P
An amorphous silicon layer of 100^ to 1 μm doped with Pm or more (hereinafter abbreviated as P layer), 36 is an insulating layer of silicon oxide, silicon nitride, polyimide, etc., 37 is AZ+cr+
Ni-0r, Mo, W.

At-8i, At-5i-Ou, SnO2, ITO
, Au, Pt, etc., 38 is a chalcogenide memory, 39 is At, Or.

Ni-0r, Mo, w, A7-8i, At-8i
-Ou, 5n02. Engineering': [' Old conductive forest materials such as O, Au, Pt, etc.! Raimu time threat V Nishikiyako Z T7 t K
The f-P layer 55 may be an n layer. In addition, the P layer and the outer layer may be made of amorphous silicon carbide, microcrystalline silicon, etc. instead of amorphous silicon, and the P layer may be made of 10 to 5 ooX.
Silicon oxide or silicon nitride may also be used. Also, the electrode is A
If the electrode forms a Schottky junction with amorphous silicon such as u, Pt, etc., the P layer may be omitted. Further, the wiring may be made of a conductive material different from that of the upper and lower electrodes. In addition, the equivalent circuit is shown in (i) of FIG.

The semiconductor device of the first embodiment has an area of 1/~'/10 compared to the conventional single element shown in FIG. 2, so that it can be highly integrated and a high-density memory can be created. or,
Since the P-knee outer layer of the diode can be manufactured in the same process, a large number of process steps can be reduced. Furthermore, since an insulating substrate is used, it has excellent characteristics such as easy isolation.

FIG. 4(α) shows a cross-sectional view of one element of the 1 m long SS memory matrix array according to the second embodiment of the present invention.
6′, 46 is a P layer, 44 is 1
layer, 45 is a % layer, 46 is an electrode/wiring, 46' is an electrode electrically connected to 42', 47 is an M SS memory,
In this example, an amorphous silicon layer doped with boron (104 atoms PPm), an amorphous silicon layer doped with phosphorus (104 atoms PPm), and an undoped amorphous silicon layer were sequentially stacked by plasma OVD.

48 is an insulating layer, and 49 is an electrode/wiring. Cb in Figure 4
) shows the equivalent circuit. FIG. 5 shows a matrix circuit of Example 2. Two diodes with different current directions are connected to each M-SS memory M', and the addressed memory, for example, the memory at address (k, kl), has the wire A connected to a positive potential or By setting the wiring No. 2 to a negative potential, operations such as writing and erasing can be performed. At this time, the other diodes act as short-circuit prevention diodes.

According to Embodiment 2, writing is performed using a conventional semiconductor switch or the like to an M-type SS memory that performs addressing by connecting two diodes of the present invention in series to the M-type SS memory.
It is possible to provide a memory matrix capable of operations such as erasing and reading, and at the same time, it is possible to greatly reduce the number of steps as in the first embodiment, and it is possible to provide an inexpensive, high-density memory that is easy to isolate.

Furthermore, in the memory diode matrix array of the embodiment, the breakdown voltage of the diode must naturally be higher than the threshold voltage of the memory-V-. The breakdown voltage of the diode of the present invention is usually about 5 to 3 QV, but when operating the memory at high speed or when applying a voltage higher than this during 7-ohming of the M-SS memory, the breakdown voltage is as shown in Fig. 6. 2 layers 1.1 layers 2. By repeatedly stacking amorphous silicon layers made of kJf@5, the breakdown voltage can be increased. FIG. 7 shows the rectification characteristics of a P layer amorphous silicon diode A, a P layer PIN amorphous negative silicon diode B, and a P layer P layer P layer N amorphous silicon diode C. Although P-N amorphous silicon having a breakdown voltage of -10 V is used in this embodiment, it is clear that the breakdown voltage can be increased by repeating P-layers.

Furthermore, the present invention has achieved similar effects in MNOS diode memories.

As described above, according to the amorphous diode Q of the present invention, it is possible to provide a diode having a structure in which the breakdown voltage of the diode can be changed in accordance with the threshold voltage of the memory, and at the same time,
By stacking the voice memory and the diode, a high-density, large-area, inexpensive, rewritable,
A unique memory matrix array can be provided, and the memory matrix array can be usefully used as a computer storage device, a single character image file, and the like.

[Brief explanation of the drawing]

Figure 1 shows a conventional memory matrix circuit. FIG. 2 is a cross-sectional view of one element of a memory matrix array using conventional chalcogenide memory and diodes. FIG. 3 is a sectional view of the chalcogenide memory of Example 1 according to the present invention. FIG. 4 is a sectional view of an M-type SS memory according to a second embodiment of the present invention. FIG. 5 shows the M Engineering SS memory matrix array of Example 2. FIG. 6 is a cross-sectional view of the stacked diode of the present invention. FIG. 7 shows the rectification characteristics of the laminated diode of the present invention. 24...N well 25...P well 28.58...Chalcogenide memory 52,
"r9.42, 46.49... Electrode and wiring 35
．． 45...P layer 34.44...1 layer 53.45...tL layer 47...M engineering SS memory 42', 46'... ...Electrode 36.48...Insulating layer Fig. 1 Fig. 3 Fig. 5 Fig. 6 Fig. 7

Claims (1)

[Claims] (1) In a memory device consisting of a memory element and a diode connected in series with the memory element, the diode is doped with boron of 5°0 atoms PPm or less, or doped with phosphorus or arsenic of 50 atoms PPm or less. , or a semiconductor device characterized by being made of non-doped thin film silicon. (2. A semiconductor device characterized by being formed by stacking a plurality of diodes as set forth in claim 1)