JPS60247333A - Expansion processing circuit - Google Patents

Abstract

PURPOSE:To improve the resistance to repetition of the analog/digital and digital/analog conversions in a dubbing mode and to reduce the deterioration in S/N and a distortion factor with record and reproduction outputs, by securing the optimum key value in an expansion mode. CONSTITUTION:The reproduced 8-bit data received an error correction is supplied through an input terminal 11 in the form of parallel data. In this case, the higher 5 bits of the data are supplied to a rank deciding circuit 12. The circuit 12 discriminates ranks according to the information on these bits and transmits the control signals to an adder circuit 13 and a control circuit 14. The circuit 13 substracts the corrected number applied in a compression mode from the input data; while the circuit 14 controls switches SW1-SW10 according to the control signal given from the circuit 12 and adds the omitted bits to obtain again the digital data of 10 bits. In this case, the MSB of a bit train to be added is set at ''1'' with the bits smaller than ''1'' set at ''0''. Thus the key value of a ''group'' is set at the carry value closest to the mean value of said ''group''.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a PCM decoding circuit that decodes a pulse code modulation (hereinafter referred to as PCM) signal compressed from 10 bits to 8 bits by polygonal processing, and particularly relates to The present invention relates to an expansion processing circuit for expanding an 8-bit PCM signal to a 10-bit PCM signal.

[Technical background of the invention]

In a helical scan video tape recorder (hereinafter referred to as a VTR) that uses a magnetic tape with a tape width of about 8 IIm, so-called 8 mm VTR, PCM
Recording of encoded audio signals is considered as an option. In this case 1. The PCM audio signal is recorded on an extension of the video track. In other words, the winding angle of the tape around the cylinder is greater than the angle of one head9, a period is provided in which multiple heads are in contact with the tape at the same time, and a PCM audio signal is recorded during this period. There is.

The audio signal recorded on magnetic tape is 8 bits, but
By companding conversion using broken line processing, the
It has a dynamic range of

FIG. 2 is a circuit diagram showing the digital processing part of the recording and reproducing system of the audio code recorded in PCM.

In FIG. 2, the recording system circuit will first be explained. An analog audio signal applied to a terminal 21 is input to an analog/digital conversion circuit 22 and converted into 10-bit digital data.

Then, it is compressed into 8-bit digital data by a 10-bit/78-bit polygonal compression processing circuit 23. This 8-bit digital data is subjected to interleaving and error correction detection code addition processing in the recording processing circuit 24, and then subjected to predetermined modulation according to the tape format.

This signal is amplified by a recording amplification circuit 25, and recorded on a magnetic tape 27 by a head 26 at an optimum recording current.

Next, the circuit of the reproduction system will be explained. The electric signal taken out from the head 26 is amplified by the reproduction amplification circuit 28.

The data is then subjected to demodulation, dinterleave, and error correction in the reproduction processing circuit 29, and then extracted as 8-bit digital data. This 8-bit digital data is returned to 10-bit digital data by an 8-bit/10-bit decompression processing circuit 30. This data is digital/
It is converted into an analog signal by the analog conversion circuit 3Z,
It is led to the terminal 32.

8-bit and 10-bit companding processing is performed as follows. 10-bit digital data is expressed as (-
Numerical information of i-511 to -512 can be expressed. In order to represent this in 8 bits (+127 to -128), the entire data is divided into seven ranks and the companding process is performed. The closer the companding ratio is to 4, the smaller it is, and the farther it is from 0, the larger it is. The basic compression method is to truncate and discard the lower digits when the binary number has a large number of digits, resulting in 8 bits. Here, -3 to +3 (including O) from the minimum value are named 7 ranks.

First, compression processing during recording will be explained. 0 rank is -16~+
15 (1111110000~000000111
In the range 1), the lower 8 bits of the numerical value between the lines are simply output and are not subjected to any processing. Therefore, even with 8 bits,
-16~+15 (11110000~0000111
1).

+1 rank is +16 to 4-63 (000001000
0 to 0000111111), here LSB
is cut off and discarded. When truncating and outputting the lower 8 bits, +16 becomes +8, which is the same data as O rank. To prevent this and make full use of 8-bit data, 8 is added as a correction number.

Therefore, an 8-bit digital signal is +16 to +39 (
00010000~00100111), −
1 rank is -17~-64 (1111101111~
1111000000) and undergoes the same processing as the half-1 rank except that the correction number is -8. Therefore, the output is -17 to -40 (11101111 to 11011000
).

+2 rank is +64 ~ +319 (000100000
0 to 0100111111), in which the lower two bits are discarded. The number of corrections added is 24, and the resulting 8-bit data is +40 to +1.
03 (00101000 to 01100111). -2 rank is -65 to -320 (111011111
1 to 1011000000), the processing here is the same as the processing for +2 rank except that the correction number is -24. Therefore, the output 8-bit data is -41
~-104 (11010111 to 10011000).

+3 rank is +320~+511 (01010:00000~0111111111)
In the range, the bits to be discarded are the lower three digits, and the number of corrections is also large, +64. As a result, the output 8-bit data is +104 to +127 (01101000 to 0
J111111). -3 rank is -321 to -5
12 (1010111111~1000000000
), and undergoes the same processing as +3 rank except that the correction number is -64. Therefore, the output 8-bit data is -105 to -128 (100101'll to 10000
00).

During playback, the reverse processing to that during recording is performed. That is, the correction number is subtracted and a carry is performed. In this case, since it is not possible to reproduce the lower bits that have been truncated from the null information, all 0s are set and reproduced for these truncated bits.

[Problems with background technology]

However, the above processing method has the following problems. That is, the lower bits discarded by the compression process are reproduced so that the data in that part becomes all 0 during the expansion/contraction process. As a result, in the +3 rank with the highest companding ratio, the lower three digits are all '000'.
”. For example, 320 (01010000
00) is also 320 during playback, but 327 (0101
000111) also becomes 320 during playback.

Here, if a set of lO bit data that becomes the same value through this companding process is called a "group", the representative value of this group will always be set to the minimum value of that group. Therefore, when dubbing is repeated, the probability that a value in a certain group will move to an adjacent lower group due to the incorporation of noise signals or mismatch in the characteristics of the analog/digital conversion circuit 12 and digital/analog conversion circuit 21 increases. is extremely high, and is a major cause of deterioration of the S/N ratio and distortion rate.

Also, if we look at the upper and lower groups whose ranks change,
The difference between the group before the rank changes (for example, the top group 76 of +2 rank represented by 316) and the next group's representative value (320 in this example) is equal to the difference in the previous rank (this In case 4), the difference from the representative value of the next group is the difference in the next rank (in this case, 328
(The difference is 8), the reproduced data between the upper and lower levels where the rank changes will change considerably.

[Purpose of the invention]

This invention was made to deal with the above situation, and by optimizing the representative value during decompression, it is resistant to repeated analog/digital conversion and digital/analog conversion during dubbing, and is resistant to recording and playback. It is an object of the present invention to provide an expansion processing circuit that has extremely little deterioration in the S/N ratio and distortion rate in the output and can smooth changes in the reproduced output.

[Summary of the invention]

In this invention, when a bit string with the same number of lower bits as the number of lower bits cut off during compression is added to the lower order of 8-bit digital data and carried, the MS of the added bit string is
By closing B to 1# and setting the bits below it to 0'', the representative value of the ``group'' is made the closest value to the average value of that ``group.''

For example, 320 (0101000000) to 327
A group of (0101000111) is converted to 104 (01101000) during 8-bit compression, but when decompressed, the group that was 320 (0101000000) in the conventional circuit is converted to 324 (
0101000100).

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of one embodiment.

In FIG. 1, error-corrected reproduced 8-bit data is input to an input terminal 11 as 8-bit no-clarity data. Among them, the upper five bits are input to the rank determination circuit 12, and it is determined to which rank the data belongs. The rank determination circuit 12 determines the rank based on the information of these bits, and sends a control signal to the adder circuit Z3 and the control circuit I4.

In the adder circuit Z3, upon receiving this signal, "-3 rank; +
64, -2 rank; +24, -1 rank; +8.0 rank; O1 +1 rank - -8,, +2 rank; -24, +
3rd rank: Generate a numerical value of -64J and add it to the input data. In other words, the adder circuit 13 performs a process of subtracting the correction number added during compression from the input data. In the subsequent selection circuit 14, the movable segments (e) of the switches SW, -sw, and O are selectively connected to the fixed terminals (a) to (d) in accordance with the control signal from the rank determination circuit I2. in this case,
The movable intercept (e) is "0 rank; terminal (,), ±1 rank; terminal (b), ±2 rank; end mark (C), +3 rank;
terminal (d). The 8-bit digital data that has been subjected to addition correction by the addition circuit I3 has bits that had been discarded added thereto by this selection circuit 14, returns to 10 bits of digital data, and is sent to the output terminal Z.
5.

Here, the configuration of the selection circuit I4 will be explained in more detail.

The MOB data of the 8-bit input data that has been added and corrected is sent to terminals (a) to (C) of switch 5Wto and switch S.
It is input to the terminals (a) and (b) of W@ and the terminal (a) of the switch SWs. The data of the 7th bit is switch 5
Wto terminal (d), switch Ogi terminal (C), switch SWI terminal (b), switch SWy terminal (&)
given to. Similarly, each bit of data from the 1st 6th pit to the LSB is input to the four switches corresponding to the bit 1 bit lower in the 10-bit data led to the terminal I5 each time the bit decreases by one. .

Then, the terminal (d) of the switch SW3 corresponding to the third bit of the 10-bit data, the terminal (c) of the switch SWz corresponding to the second bit, and the terminal (b) of the switch SWi corresponding to the LSB are connected. is always input with the logic "1", and the terminal (a) of the switch SW corresponding to the second pit, LS
Terminals (d), (e) of switch SWt corresponding to H
Data "0#" is always input to the field.

In such a configuration, when the input data is O rank, the switches SW, -, -8W1 . Each movable contact piece (e)
is connected to the terminal (,), the 8-bit data that has been added and corrected is output as is as the lower 8-bit data of the 10-bit data, and the upper 2-bit data is as follows.
The MSB data of the above 8 pits τ is given. This process is performed because binary numbers are numeric information (for example, "7#" is "111" and the lower three digits are numeric information).If the digits are positive, This is because they are all 0#, and when they are negative, they are all "1".

When the input data is ±1 rank, switch SWt −
The movable contact piece (,) of 5w1 can be connected to the terminal 6). Therefore, the 8-bit bit data subjected to the addition correction is used as the pit string data from the 9th bit to the 2nd pit of the 10-bit data.

The MSB of the 10-bit data is given the MSB of the 8-bit data as in the case of 0 rank. Since the LSB of 10-bit data is the MSB of the lower pit string (in this case, 1 bit) that is discarded during compression, a logic "1" is given.

When the input data is ±2 ranks, switch 5Wi-8
The movable contact piece (•) of Wto is connected to the terminal (c). Therefore, the 8-bit data that has been added and corrected is used as data for the upper 8 pit rows. Since the lower two bits of the 10-bit data are pit strings that are cut off and discarded during compression, the MOB is given logic "l#" and the LS
B is given logic "0".

When the input data is ±3 ranks, switch SW I
-8W+o movable contact piece (e) is connected to terminal (d). Therefore, the data of the lower 7 bits of the 8-bit data that has been added and corrected is used as the data of the upper 7 bits of the pit string of the 10-bit data. Then, 100# is added to the lower 3 bits, the lower 3 bits of the MOB that were discarded during compression are set to 1', and the lower 2 bits are set to 1ol.
11 processing is achieved. In this ±3 rank input data decompression process, the MSB of the addition-corrected 8-bit data is truncated because the input data is compressed by truncating the lower 3 bits, leaving it as 7 bits. This is because the MSB of data does not contain information.

According to this embodiment described in detail above, the representative value of each group output during reproduction is the value closest to the average value of that group. Therefore, in processing that repeatedly performs analog/digital conversion and digital/analog conversion, such as general dubbing other than digital dubbing, noise may be added to the signal in the analog section, or analog /Even if there is a mismatch in the characteristics of the digital conversion circuit and the digital-to-analog conversion circuit, there is a margin above and below the representative value, so it is difficult to move to an adjacent group during compression. In particular, since the probability of data moving to a lower group is lower than in the conventional circuit, it is extremely effective in preventing deterioration of the 87N ratio and distortion rate.

Further, the change in the representative value between the top and bottom where the companding process rank is switched becomes smooth. For example, from +2 rank +
The representative value of the part that moves to 3rd rank is r 314 (010
01110 Dan), 318 (01001111 Dan),
324 (01010001 (4).

332 (mountain 0101001)'', the difference between each representative value is 4.6.8, and the change is smooth.

In addition, the configuration focuses only on the value that should be output during playback, and there is no change in the recording system, so it is compatible with existing recorded tapes and can exhibit exactly the same performance.

The present invention is of course applicable not only to the decompression processing circuit in the PCM processing circuit of the 73m1 VTR (but also to general decompression processing circuits in the PCM processing circuit that performs 1078-bit companding conversion on PCM data).

[Effect of the temple]

As described above, the present invention is resistant to repeated analog/digital conversion and digital/analog conversion associated with repeated companding processing, and does not cause deterioration of the S/N ratio or distortion rate in the compressed/expanded output. It is possible to provide a decompression processing circuit that is extremely small in number and can smooth changes in the decompression output.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a digital processing part of a recording and reproducing system for audio signals recorded in a CM. 11.15...Terminal, Z2...Rank judgment circuit, 13
... Addition circuit, 14... Selection circuit.

Claims (1)

[Claims] The lower part of the i4rus code modified signal compressed from 10 bits to 8 bits by line-breaking processing has the same number of lower bits as the number of lower bits cut off during compression, and the most significant bit is ``1#''. 1. An expansion processing circuit characterized in that the 8-bit .9 pulse code modulated signal is expanded to 10 bits by adding a bit string in which the following bits are "0".