JP2855838B2 - Magnetic playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of the invention C Conventional technology D Problems to be solved by the invention E Means for solving the problem (FIG. 1) F function (FIG. 1) G embodiment (FIG. 1 to FIG. 1) (Fig. 4) (G1) Configuration of the embodiment (Figs. 1 to 4) (G2) Operation of the embodiment (G3) Effects of the embodiment (G4) Other embodiments Effects of the H invention A Industrial use BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic reproducing apparatus, and can be applied to, for example, a video tape recorder adapted to convert a video signal into a digital signal for recording and reproducing.

B. Summary of the Invention In the present invention, in a magnetic reproducing apparatus, the number of bits of a Viterbi decoding circuit is set so that an error rate becomes a desired value, and a reproduction signal is processed with the number of bits from an analog digital conversion circuit to a Viterbi decoding circuit. This makes it possible to reliably demodulate the reproduced signal with a simple configuration.

C Prior Art Conventionally, in this type of video tape recorder, there is a video tape recorder which converts a video signal into a digital signal and performs recording and reproduction.

In such a video tape recorder, even if dubbing is repeated, image quality degradation can be effectively avoided.

D Problems to be Solved by the Invention By the way, in this type of video tape recorder, if a video signal is recorded and reproduced by applying a class IV partial response system which is one of the high-efficiency encoding systems, an electromagnetic conversion system is required. It is considered that the video signal can be recorded and reproduced efficiently by effectively utilizing the frequency characteristics.

Furthermore, if the class IV partial response method is applied, it can be considered that the video signal can be reliably reproduced using the Viterbi decoding circuit.

However, when demodulating the reproduction signal in this manner, the overall configuration may be complicated.

The present invention has been made in view of the above points, and has as its object to propose a magnetic reproducing apparatus capable of reliably demodulating a reproduction signal with a simple configuration.

Means for Solving Problem E In order to solve such a problem, in the present invention, in a magnetic reproducing device 1 for reproducing predetermined recording data D _REC recorded on a magnetic recording medium 5 using a partial response method, magnetic head 16A, and analog-to-digital converter circuit 19 which converts the digital data y _k of the reproduced signal S _RF which is obtained through a 16B in a predetermined period, digital data
based on y _k , comprising Viterbi decoding circuits 28 and 30 for outputting decoded data D _PB , wherein the Viterbi decoding circuits 28 and 30 provide a bit error rate of the decoded data D _{PB to} a desired value.
Number of bits (6) is selected, the analog-to-digital converter 19 is a number of bits equal to number of bits of the Viterbi decoding circuit 28, 30 (6), converts the reproduced signal S _RF to digital data y _k.

Function F The number of bits (6) of the Viterbi decoding circuits 28 and 30 is selected so that the bit error rate of the decoded data D _PB becomes a desired value, and the reproduced signal is reproduced with the number of bits (6) equal to the number of bits.
Be converted to S _RF to digital data y _k, obtained constitutes the entire reproduction system in number of bits of necessary minimum, it is possible to simplify the correspondingly overall structure.

G Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

(G1) in FIG. 1 configuration of Embodiment 1 as a whole shows a video tape recorder, a subcarrier signal of four times the clock signal S analog-to-digital converter adapted to operate in _ck (A /
D) The video signal _Sv is given to 2.

Thereby, the analog digital conversion circuits 2 to 8
(Hereinafter referred to as digital video signal) quantized video signal in bits made to obtain the D _v, it compresses the digital video signal D _v to the data D _R of about 25 [MBPS] In the data compression circuit 4.

Error Collection Chillon circuit (ECC) 6 performs Shiyafuringu, the processing code addition or the like for error correction on digital video signals are data compressed D _R and digital signal processed audio signal D _A, thereby about 30 [ MBPS)
To generate the recording data D _REC .

The precoding circuit 2 sequentially records data D _REC ,
Next formula Running in represented by arithmetic processing, it converts the recording data D _REC to the pre-code data D _PR.

 Here, MOD2 represents the remainder of 2.

That is, as shown in FIG. 2, when recording / reproducing a signal on / from a magnetic tape, since the electromagnetic conversion system such as a magnetic head has a differential characteristic, the CN ratio is deteriorated when the frequency is lowered. When the ratio increases, the CN ratio similarly deteriorates due to the magnetization characteristics of the magnetic tape.

Therefore, when recording and reproducing a digital video signal, the magnetic recording and reproducing system has a characteristic that a frequency band in which a good CN ratio can be obtained is narrow.

Therefore, when recording a digital video signal, select a recording / reproducing method that concentrates the signal spectrum near the maximum CN ratio, thereby effectively avoiding the deterioration of the CN ratio of the reproduced signal. It is necessary to efficiently record and reproduce digital video signals.

Therefore, in this embodiment, the digital video signal is recorded and reproduced efficiently using the class IV partial response system.

That is, in magnetic recording / reproducing, the CN ratio is degraded at the lower and higher frequencies, and the frequency characteristic is represented by the class IV partial response (D) using the delay operator D as shown in FIG. 1-D ² ) and can be expressed in an approximate manner to the frequency characteristic H (ω).

Incidentally, the angular frequency ω ₀ at which the response is minimized is given by the following equation with respect to the delay time T represented by the delay operator D. There is a relationship.

Therefore, by selecting the delay amount represented by the delay operator D to a predetermined value, the spectrum of the signal can be concentrated near the maximum CN ratio.

The transfer function of the entire reproduction system contrast, put the following formula (1-D) · (1 + D) = 1-D 2 ...... (3), with respect to processing of the pre-code circuit 8, the recording and reproducing The transfer function can be set to 1 for the entire system, and the digital video signal can be efficiently recorded and reproduced by effectively utilizing the frequency characteristics of the magnetic recording and reproducing system.

Thus, the precoding circuit 8 outputs the precoding data D _PR
Is generated and output to the adding circuit 9 in predetermined block units.

Addition circuit 9 adds the predetermined data Dp before and after each block of the precoded data D _PR, thereby adding the data of the postamble and the preamble to the pre-code data D _PR.

Magnetic head 12A and 12B contrast, are arranged at an angular interval of 180 degrees on the rotary drum (not shown), thereby precoded data D _PR which postamble and the preamble is added, in one block units The information is sequentially recorded on the recording track.

In the preamble, the precode data D _PR
Of repetitive reference signal of a frequency 15 [M Hz] is the frequency is recorded, the frequency of the reference signal (2) is selected to be the frequency omega ₀ satisfying the equation.

Accordance connexion In this embodiment, based on the reference signal of frequency 15 obtained from the preamble [M Hz] adapted to form a reproduction clock, adapted to process the reproduced signal S _RF on the basis of the playback clock ing.

During reproduction contrast, the magnetic head 16A and 16B, and outputs a reproduced signal S _RF via the amplifier circuit 18 to the analog-to-digital converter (A / D) 19 and PLL (phase locked loop) circuit 20.

PLL circuit 20 on the basis of the reproduced signal S _RF in the preamble, generates a reproduction clock CK.

The analog-to-digital conversion circuit 19 provides the playback clock
The reproduction signal _SRF is quantized based on CK to generate 6-bit digital data y _k .

Selection circuit 21 switches the contact point based on the reproduction clock CK, and outputs the separated digital data y _k to the data of the even columns and odd columns.

The arithmetic processing circuits 22 and 23 each include an equalizer circuit 24
And 25, receive even-numbered and odd-numbered rows of digital data y _k with frequency characteristics corrected, and
Perform (1 + D) arithmetic processing on y _k .

Thus after converting the reproduced signal S _RF to digital data y _k, the arithmetic processing circuit 22 and 23, the equalizer circuit 24 and 25
, The arithmetic processing circuits 22 and 23 and the equalizer circuits 24 and 25 can be constituted by digital circuits.

Therefore, the characteristic change due to the temperature change can be effectively avoided, and the adjustment part can be omitted, whereby the configuration of the entire reproduction system can be simplified.

Also, the entire video tape recorder can be easily reduced to an integrated circuit, and the entire video tape recorder can be reduced in size accordingly.

By the way, as described above with respect to equation (3), class IV
In order to set the transfer function of the entire recording / reproducing system to 1 in the partial response, the transfer function of the reproducing system is set to 1-
It must be set to D ^2.

On the other hand, since the electromagnetic conversion system has a differential characteristic, the reproduced signal _SRF is generated by using the delay operator D (1
−D), and is represented by a frequency characteristic as shown by a broken line in FIG.

Accordingly, by performing an arithmetic processing of (1 + D) on the digital data y _k , the transfer function of the reproducing system can be set to (1-D ² ), and the transfer function of the entire recording / reproducing system can be set to 1. it can.

Thereby, the digital video signal can be recorded and reproduced efficiently by effectively utilizing the frequency characteristics of the magnetic recording and reproducing system.

However, performing the processing of (1-D ²⁾ to the reproduction signal S _RF is a magnetic head 12A, the recording signal D _R to be inputted to 12B 2
This means that arithmetic processing is performed with the clock cycle delayed.

Accordance connexion, executing arithmetic processing separates the input data y _k to the even sequence and the odd sequence (1 + D), each with respect to the recording signal D _R of the even sequence and an odd sequence processing (1-D) The executed input data y _k can be obtained.

Thus, when decoding the input data y _k that is divided for each even-numbered line and an odd sequence, the input data y _k for the recording signal D _R, y _{k + 1,} Viterbi by using the correlation of ...... (1-D) A decoding technique can be applied, whereby the reproduced data D _PB can be decoded with reduced bit errors.

That is, the Viterbi decoding circuits 28 and 30 sequentially decode the input data y _k , y _{k + 1} ,... By applying the Ferguson algorithm (FURGUSON'S ALGOLITHM) and decode the decoded data D _PB
Generate

Thus, by generating the decoded data D _PB by using the Viterbi decoding circuit 28 and 30, compared to the decoding circuit of the general in which the signal level to the reference, much to decode the small data of bit error Can be.

Therefore, when applied to a digital video tape recorder,
Digital video signals can be reliably reproduced.

By the way, as shown in FIG.
If the bit error rate is detected by switching the number of 30 bits, it is difficult to improve the bit error rate even if the number of bits is increased to 6 bits or more.

That is, in the video tape recorder, if processing a reproduced signal S _RF with 6 bits, that practically sufficient can be seen in order to demodulate the reproduced signal S _RF.

On the other hand, in a normal digital signal processing circuit, since the number of bits is selected to be 8 bits, the digital signal processing circuit is used to configure the analog digital conversion circuit 19 to the Viterbi decoding circuits 28 and 30. Then, a reproduced signal processing system is wastefully constituted by two bits.

Therefore, in this embodiment, the number of bits of the Viterbi decoding circuits 28 and 30 is selected to be 6 bits, and the analog digital conversion circuit 19, the selection circuit 21, the arithmetic processing circuits 22 and 23, and the equalizer circuits 24 and 25 are set to the number of bits. The number of bits is equal to.

As a result, a useless configuration for two bits can be omitted, the entire configuration can be simplified by that amount, and thus the reproduced signal can be demodulated simply and reliably.

In particular, if the number of bits can be reduced from 8 bits to 6 bits as described above, the integrated circuit can be simply configured by an amount corresponding to the integrated circuit.

The selection circuit 32 switches the contacts in synchronization with the reproduction clock CK, thereby mixing the even-numbered and odd-numbered decoded data output from the Viterbi decoding circuits 28 and 30 into one series of data.

Error detecting and correcting circuit 34 receives the decoded data D _PB output from the selection circuit 32, after detecting and correcting bit errors to separate the data of the audio signal S _APB and video signals.

The data decompression circuit 36 receives the video signal data separated by the error detection and correction circuit 34 and decompresses the data in a manner opposite to the data compression circuit 4.

The digital-to-analog conversion circuit 38 sequentially converts the data of the decompressed video signal into an analog signal and outputs the analog signal, whereby a reproduced video signal S _VPB can be obtained.

(G2) Operation of Embodiment With the above configuration, a video signal S _v is converted into a digital video signal D _v in the analog-to-digital converting circuit 2, the compressed data D _R of about 25 [MBPS] In the data compression circuit 4 Is done.

Compressed data D _R is Shiyafuringu with audio signal D _A with error collection Chillon circuit 6, the processing of the code addition or the like for error correction is performed, recording data D _REC 30 [MBPS]
Is converted to

Recording data D _REC is converted into precoded data D _PR and the pre-coding circuit 8 (2) calculation of formula is subjected, is recorded on the magnetic tape 14 is divided into each block,
At the same time, a preamble in which a reference signal having a frequency of 15 [M Hz] is recorded is formed.

Reproduced signal S _RF which contrast is output from the magnetic head 16A and 16B is amplified through an amplifier circuit 18, it is converted into digital data y _k of the analog digital converter circuit 19 6 bits.

The digital data y _k, after being separated into the data of the even columns and odd columns in the selection circuit 21, the equalizer circuit 24 and 25, respectively, are given to the Viterbi decoding circuit 28 via the arithmetic processing circuit 22 and 23.

At this time, the digital data y _k separated into the even columns and the odd columns are subjected to the arithmetic processing of (1 + D) by the arithmetic processing circuits 22 and 23 after the frequency characteristics are corrected by the equalizer circuits 24 and 25. digital data y _k with respect to the recording signal D _R of the even sequence and an odd sequence functions (1-D) is input to the Viterbi decoding circuit 28, 30.

Viterbi decoding circuit 28 utilizes the relationship between the (1-D), are mixed successively decodes the digital data y _k, the data of one line through the decoded data obtained as a result is a selection circuit 32 As a result, decoded data D _PB is generated.

In digital signal processing circuit in this case from the analog-to-digital converting circuit 19 to the Viterbi decoding circuit 28, 30, the number of bits is set to 6 bits, thereby demodulating the reproduced signal S _RF with practically sufficient bit error rate Can be.

Furthermore, the unnecessary configuration can be omitted to simplify the entire configuration,
A reproduced signal can be demodulated simply and reliably.

The output data of the selection circuit 32 is converted to a video signal _SVPB through an error detection and correction circuit 34, a data decompression circuit 36, and a digital-to-analog conversion circuit 38 in reverse order from that at the time of recording.

(G3) Effects of Embodiment According to the above configuration, the analog-to-digital conversion circuit 19
Up to Viterbi decoding circuits 28 and 30 by constructing in digital signal processing circuit 6 bits, it is possible to demodulate the reproduced signal S _RF with practically sufficient bit error rate by omitting useless consists, correspondingly The reproduced signal can be reliably demodulated with a simple configuration.

(G4) In other embodiments noted above embodiment, after converting the reproduced signal S _RF into a digital signal, an equalizer circuit has dealt with the case of correcting the arithmetic processing circuit, the present invention is not limited to this, After the reproduction signal _SRF is corrected by the equalizer circuit and the arithmetic processing circuit, it may be converted into a digital signal and processed.

Furthermore, in the above-described embodiment, a case has been described in which the components from the analog digital conversion circuit 19 to the Viterbi decoding circuits 28 and 30 are constituted by a 6-bit digital signal processing circuit. However, the number of bits is not limited to this and may be changed as necessary. Various values can be selected.

Further, in the above-described embodiment, the case of recording and reproducing a digital video signal has been described. However, the present invention is not limited to this, and can be widely applied to the case of recording and reproducing various digital signals.

Further, in the above-described embodiment, the case where data is recorded / reproduced on / from the magnetic tape has been described. However, the present invention is not limited to the magnetic tape and can be widely applied to a magnetic reproducing apparatus using a magnetic recording medium.

H Effects of the Invention As described above, according to the present invention, the number of bits of the Viterbi decoding circuit is set so that the error rate becomes a desired value, and the digital signal of the number of bits is transmitted from the analog digital conversion circuit to the Viterbi decoding circuit. By using a processing circuit, a magnetic reproducing apparatus capable of reliably demodulating a reproduction signal with a simple configuration can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a video tape recorder according to an embodiment of the present invention, FIG. 2 is a characteristic curve diagram showing a frequency characteristic of a magnetic recording / reproducing system, and FIG. 3 is a frequency characteristic of a class IV partial response. FIG. 4 is a characteristic curve diagram showing a bit error rate. 1 video tape recorder, 2, 19 analog digital conversion circuit, 8 precode circuit, 12A, 12B, 16
A, 16B ... magnetic head, 14 ... magnetic tape, 21, 32 ...
Selection circuit, 22, 23 ... arithmetic processing circuit, 24, 25 ... equalizer circuit, 28, 30 ... Viterbi decoding circuit.

Claims (1)

(57) [Claims] 1. A magnetic reproducing apparatus for reproducing predetermined recording data recorded on a magnetic recording medium using a partial response system, wherein a reproduction signal obtained via a magnetic head is converted into digital data at a predetermined period. An analog digital conversion circuit; and a Viterbi decoding circuit that outputs decoded data based on the digital data. The Viterbi decoding circuit reduces the number of bits so that a bit error rate of the decoded data becomes a desired value. The selected analog digital conversion circuit converts the reproduction signal into digital data with a bit number equal to the bit number of the Viterbi decoding circuit.