JPS6024635A - Parallel multiplying circuit - Google Patents
Parallel multiplying circuitInfo
- Publication number
- JPS6024635A JPS6024635A JP13261383A JP13261383A JPS6024635A JP S6024635 A JPS6024635 A JP S6024635A JP 13261383 A JP13261383 A JP 13261383A JP 13261383 A JP13261383 A JP 13261383A JP S6024635 A JPS6024635 A JP S6024635A
- Authority
- JP
- Japan
- Prior art keywords
- carry
- circuit
- ofa
- output
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
- G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本兜明は、並列乗算回路に関するものである〇〔発明の
技術的背景とその問題点〕
二進数の演算装置として、全加算器（フルアダー）にア
ンド・ゲートを組み合せた単位回路を桁数×桁数たけ、
行列状に配置し、さらに、その最終段の下に桁数個の全
加算器を配置して乗算を行なう、並列乗算回路がある。[Detailed description of the invention] [Technical field of the invention] This book relates to a parallel multiplication circuit. [Technical background of the invention and its problems] A full adder is used as a binary number arithmetic device. The unit circuit that combines AND gates is the number of digits x the number of digits,
There is a parallel multiplier circuit that is arranged in a matrix and further has full adders of several digits arranged below the final stage to perform multiplication.
第１図は、従来の並列乗算回路を示すものである。第１
図は８桁の２進数の並列乗算回路であり、８行８列に配
置された６４個の単位回路””１１ Ｊ （ｔ Ｉ Ｊ
＝ｉ ＋ ２ ＋・・・、８）と８個の全加算器にＡ
ｉ（ｉ＝ｌ、２．・・・、８）で信成されている。８桁
の乗数、被栄数をｘ８．ｘ７・・Ｘ、 、 Ｙ８． Ｙ
、・・・Ｙｌとし、その乗算結果をＰＩＱ＋ＰＣ＋・・
Ｐｌで表わしている。FIG. 1 shows a conventional parallel multiplication circuit. 1st
The figure shows an 8-digit binary parallel multiplication circuit, which consists of 64 unit circuits arranged in 8 rows and 8 columns.
= i + 2 +..., 8) and A to the 8 full adders.
It is established by i (i=l, 2..., 8). 8-digit multiplier, multiply the number of trophies by x8. x7...X, , Y8. Y
,...Yl, and the multiplication result is PIQ+PC+...
It is expressed as Pl.
第２図は、ね）１図の単位回路および最終段の全加算器
の入出力信号関係を示すもので、Ｃｉ、ｊおよびＣｉは
各セルの桁上り一人出力で・ある。FIG. 2 shows the input/output signal relationship of the unit circuit of FIG. 1 and the final stage full adder, where Ci, j and Ci are the carry single outputs of each cell.
これらのイへ号の間には、次のような論理式が成立つ。The following logical formula holds between these numbers.
この方式によれは桁上りをいわゆるリップルキャリ一方
式により行なうので、桁上は信号が最終段の全加算器に
到逐するまでに、その前のすべての単位回路を通ること
になり、極めて時間がかかる。また、この理由によって
、大きい桁数の乗算に長時間を喪する。In this method, the carry is carried out by a so-called ripple carry method, so the carry takes an extremely long time as the signal passes through all the previous unit circuits before reaching the final stage full adder. It takes. Also, for this reason, multiplication with a large number of digits takes a long time.
本発明は、上記事情を考慮してなされたもので、乗算回
路のダート数をいたずらに増大させることなく１桁送り
速度の向上を図った並列乗算回路を提供づ−ることを目
的とする。The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a parallel multiplier circuit capable of improving the feed speed by one digit without unnecessarily increasing the number of darts in the multiplier circuit.
上記目的を達成するため、本発明においては、並列乗算
回路において行列状に配置、された単位°回路の各列の
桁上げに、キャリー・スキップ方式の演算回路を結合し
たことを特徴、とするものである。In order to achieve the above object, the present invention is characterized in that a carry-skip type arithmetic circuit is coupled to the carry of each column of unit circuits arranged in a matrix in a parallel multiplier circuit. It is something.
本発明によれは、従来の並列乗算回路に比べ、下記の効
果が得られる。単位回路の各列の桁上げに、キャリー・
スキップ方式の演算回路を結合することにより、入力が
ある条件を満たす場合には、桁上１ｔｊ信号は、単位回
路を通過することなく、比較的少ないゲート数で（１１
成されるキャリーΦスキップ方式の患算回路を通過する
だけで、最終段の全加あ１、器に、４１Ｊ辿する。桁上
り信号が、キャリースキップ方式の鼠算回路を通過する
時間は、多数のＵド１位回路を通過するそれに比べて短
く、従って、桁上り一他匂伝播の高速化がＦｉｌ能であ
り、その結果、大ぎい桁敬の乗↓−４時間の短縮化が可
能となる。According to the present invention, the following effects can be obtained compared to conventional parallel multiplication circuits. A carry is added to each column of the unit circuit.
By combining skip-type arithmetic circuits, if the input satisfies a certain condition, the carry 1tj signal can be processed without passing through the unit circuit and with a relatively small number of gates (11
By simply passing through the carry Φ-skip type calculation circuit, 41J are traced to the final stage of the total summation circuit. The time it takes for a carry signal to pass through a carry-skip type mouse calculation circuit is shorter than the time it takes for a carry signal to pass through a large number of U-Do 1 circuits. As a result, it is possible to shorten the time by 4 hours.
以下、本発明を実施例により具体的に説す」する。 Hereinafter, the present invention will be specifically explained with reference to Examples.
第３図は、あ１図に於いて破線で分割された１６個の単
位回路から成る部分に、本発明の特徴とする、キャリー
・スキップ方式の１５’１． ％Ｌ回ｈ：ｉ’＋を結合
した回路を示すものである。第゛３図に於ける回路ＯＦ
Ａは、第４図にンＪ＜すように、第１必ｊに於ける従来
の単位回路に’Ａ １ 、ｊにオア・ゲートＧ、を付加
したものである。第３図の４個の力と最上列のＯＦＡ
の桁上げ入力とする５人カアンド・ゲートＧ２と、その
５人カアンド・ゲートＧ２の出力と最下列のＵＦＡの’
ｔｒｉ上け゛出力を入力とするオア・ゲートＧ、から成
るキャリーΦスキップ方式の演算回路を付加したことが
、この回路の特徴である０
このよう−にキャリー・スキップ方式の演算す路を付加
することにより、得られ暮効果を具体的に説明する。第
３図の４個のＯＦＡの縦列に於てあれは、最下列の（１
’Ａの桁上は出力は、４個のＵＦＡを通過することなく
、上述のキャリー・スキップ方式の演算回路のグー）
Ｇ ２ 、 Ｇ ｓを通過するだけで、“ｌ”が出力び
れる。この鏑件の−下では、最下列のＯＦＡの桁上は出
力は、キャリー・スキップ方式の演算回路を付加しない
場合に比して、高退化される。FIG. 3 shows a section consisting of 16 unit circuits divided by broken lines in FIG. %L times h:i'+ is shown. Circuit OF in Figure 3
A is a conventional unit circuit in the first case with an OR gate G added to 'A 1 ,j, as shown in FIG. The four forces in Figure 3 and the OFA in the top row
The 5-man AND gate G2 is used as a carry input, and the output of the 5-man AND gate G2 and the UFA in the bottom row are
The feature of this circuit is the addition of a carry-skip calculation circuit consisting of an OR gate G that receives the output of the higher value of tri. The benefits obtained will be explained in detail. In the column of four OFA in Figure 3, that is (1
'The output of the digit of A is the result of the above-mentioned carry-skip type arithmetic circuit without passing through the four UFAs)
Just by passing through G2 and Gs, "l" is output. At the bottom of this case, the output of the OFA in the bottom row is highly degraded compared to the case where no carry-skip type arithmetic circuit is added.
第３図に４くず回路を第１図の破線で分飽された１６個
の単位回路から成る４個の部分にそれぞれ適用すること
により、ＦＡｉ、８（ｉ＝１，２．・・・。By applying the four waste circuits shown in FIG. 3 to the four portions consisting of 16 unit circuits that are saturated by the broken lines in FIG. 1, FAi, 8 (i=1, 2, . . .
８）の桁上げ出力の同速化が図れ・従って乗算結果の上
位８桁Ｐｉ（ｉ＝９＋ＩＯ，・・・、１６）の出力の高
速化が￥現されるＯ
なお、上記実施例は好しい一つの実施例として挙けだも
のにすきず５本発明はこれに限定されることなく他に辿
々の態椋で実施できるものである。8) The same speed of carry output can be achieved. Therefore, the output of the upper 8 digits Pi (i=9+IO,...,16) of the multiplication result can be faster. Note that the above embodiment is preferable. Although the present invention is given as one example, the present invention is not limited thereto and can be implemented in various other ways.
第１図は、従来の並列乗算回路σ）−例を力り１−図、
第２図（ａ） 、 （ｂ）は、抛１図σ）単位回路とム
シ下段全力日、１−器の一面理と大田力を示す図、第３
１１、キャリー・スキップ方式の演算回路を第１図の回
路に結合した本発明の一天施例σ）１１号成を示１−図
、第４図は第３図のＩＬ！回路０１！’Ａσ）（；・）
成を示す図である。
ＦＡ・・・単位回路、Ｇ１・・・オア・グー）、Ｇ２・
・・アンド拳ゲート％ Ｇ３・・・オアｅケート。
出願人代理人 弁理士 鈴 江 武 彦第１ 図
罹 １ 晴 Ｒ３ＦＩ２ 吊 詔 ら
第２図Figure 1 shows an example of a conventional parallel multiplier circuit σ).
Figures 2 (a) and (b) are diagrams showing the unit circuit and the lower half of the unit circuit, the one-sided principle of the vessel, and the force of Ota, and Figure 3.
11. A one-day embodiment of the present invention in which a carry-skip type arithmetic circuit is combined with the circuit shown in FIG. Circuit 01! 'Aσ) (;・)
FIG. FA...unit circuit, G1...or goo), G2...
...And Fist Gate% G3...Or e Kate. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Haru R3FI2 Hane et al. Figure 2
Claims (1)
配置近しｔ二進数の乗算を行なう並列乗算回路において
、前記単位回路の各列の桁上げに、キャリー・ス六ツブ
方式の演算回路を結合したことを特徴とする並列乗算回
路。In a parallel multiplication circuit that multiplies binary numbers by arranging unit circuits that are a combination of a full adder and an AND gate in a matrix, a carry-strip type arithmetic circuit is used to carry each column of the unit circuits. A parallel multiplication circuit characterized by combining the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13261383A JPS6024635A (en) | 1983-07-20 | 1983-07-20 | Parallel multiplying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13261383A JPS6024635A (en) | 1983-07-20 | 1983-07-20 | Parallel multiplying circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6024635A true JPS6024635A (en) | 1985-02-07 |
Family
ID=15085419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13261383A Pending JPS6024635A (en) | 1983-07-20 | 1983-07-20 | Parallel multiplying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6024635A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61114338A (en) * | 1984-11-09 | 1986-06-02 | Hitachi Ltd | Multiplier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5731042A (en) * | 1980-07-31 | 1982-02-19 | Toshiba Corp | Multiplaying and dividing circuits |
-
1983
- 1983-07-20 JP JP13261383A patent/JPS6024635A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5731042A (en) * | 1980-07-31 | 1982-02-19 | Toshiba Corp | Multiplaying and dividing circuits |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61114338A (en) * | 1984-11-09 | 1986-06-02 | Hitachi Ltd | Multiplier |
| JPH0584530B2 (en) * | 1984-11-09 | 1993-12-02 | Hitachi Ltd |
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