JPS60246123A - Method and apparatus of analog-digital conversion - Google Patents

Abstract

PURPOSE:To obtain a quantized signal having a fairly high resolution by allowing an A-D converter to execute the A-D conversion divided into plural number of times while narrowering at any time an upper limit reference voltage and a lower limit reference voltage being converting references of the said A-D converter. CONSTITUTION:A D-A converter 4 executes D-A conversion based on digital signals D1-D4 and outputs the 1st voltage A1 corresponding to the quantized level of the said signals D1-D4 and the 2nd voltage A2 corresponding to a level lower by one quantized level than the quantized level of the said signals D1-D4. When the D-A conversion is executed, a sequence control circuit allows a selection circuit 5 to select a voltage at a B input terminal and then the A-D converter 2 uses the 1st and 2nd voltages A1, A2 being the D-A conversion output as the upper limit reference voltage UB and the lower limit reference voltage LB respectively so as to execute the A-D conversion of the said sample-and-hold signal ASH.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an A-D conversion method and device for quantizing analog signals, and particularly to a method and device suitable for improving resolution during quantization. .

[Conventional technology]

Various types of A-D converters for quantizing analog signals such as those described above have been proposed and put into practice, but all of them are limited to the desired resolution for quantization. A- with the same resolution in advance according to the
Since the D converter is selected and used,
If it is necessary to increase this resolution for some reason, it will be necessary to add an A-D converter, which will be disadvantageous in terms of space cost and power consumption. I had no choice. By the way,
Every time you try to increase the above resolution by 1 bit, the number of A-
A D converter is required.

In addition, in the case of a device that requires extremely high resolution from the beginning for the above quantization, the A-D converter used must also have a correspondingly high resolution. Naturally, it becomes large and expensive.

[Problem that the invention seeks to solve]

This invention is aimed at improving the resolution of the quantized signal when quantizing the analog signal mentioned above, or when a high-resolution quantized signal is required. This is an attempt to effectively resolve the situation where large disadvantages arise.

[Means and effects for solving the problem] In this invention,
In order to solve the above problem, the upper limit reference voltage and lower limit reference voltage used as conversion standards for one A-D converter are narrowed as needed, and the A-D conversion operation by the same A-D converter is performed multiple times. In particular, during the second and subsequent A-to-digital conversion operations, the upper limit reference voltage and the lower limit reference voltage are determined based on the previous quantized signal, and the resulting A-to-D conversion By collecting quantized signals for each operation in parallel, a quantized signal having the desired resolution, that is, a quantized signal having the desired number of zets, is obtained. This makes it possible to use an A-D converter with a resolution that is half or less than the final desired resolution.

〔Effect of the invention〕

As described above, according to the A-D conversion method and apparatus according to the present invention, even when trying to obtain a quantized signal with considerably high resolution, the A-D converter itself used for this purpose is This can be realized very advantageously in terms of space and economy since it requires only a low resolution device, that is, a small size and small capacity.

〔Example〕

FIG. 1 shows an embodiment of an &-D conversion device according to the present invention. However, this embodiment shows an example of a device that quantizes an input analog signal with 8-bit resolution based on two A/D conversion operations.

First, the functions of each block constituting the apparatus of this embodiment will be briefly explained.

The sample and hold circuit 1 is a circuit that samples an analog signal As input to an input terminal IN of the device at a predetermined timing based on a control signal 8H applied from a sequence control circuit (not shown) and holds it. This sampled and held signal ASH is input to the A-D converter 2 as a DC voltage indicating the sampling level during the hold period. In this embodiment, it is assumed that the sample-and-hold signal ASH is maintained in this hold state until the A-to-digital converter 2 executes an A-to-D conversion operation, which will be described later, twice.

The A-D converter 2 is a circuit that quantizes the input sample-and-hold signal ASH with a resolution of 4 bits. based on,
A 4-bit digital signal ~D4 corresponding to the sampling level of the sample hold signal ASH is output. Since the A-D converter 2 has a resolution of 4 bits, the voltage between the upper limit reference voltage UB and the lower limit reference voltage LB is divided into 16 quantization levels, and therefore the sample and hold signal is divided into 16 quantization levels. ASH is given a code of one of these divided quantization levels and output as the digital signals D1 to D4, but in this embodiment, the sampling of the sample hold signal ASH is It is assumed that among the quantization levels closest to the level, the code corresponding to the higher level is outputted as the digital signal ~D4.

The latch circuit 3 latches the digital signal ~D4 output from the input-D converter 2 regarding the first quantization of the sample-and-hold signal ASH based on a control signal LC applied from a sequence control circuit (not shown). This latched signal is -1),
is added to the DA converter 4.

The D-A converter 4 receives the input digital signal D1.
〜D4, an analog signal AI (hereinafter referred to as a first voltage to avoid confusion with the input analog signal) corresponding to the quantization level of the signal RI, −D, and the signal RI, 〜 These circuits each form and output an analog signal A4 (hereinafter referred to as a second voltage for the same reason as above) corresponding to a level one quantization level lower than the quantization level of D4. Voltage A1 and second voltage A2 are applied to the B input terminal of selection circuit 5.

Based on a control signal SL applied from a sequence control circuit (not shown), the selection circuit 5 selects the output voltage E of the power supply circuit 6 and the ground voltage applied to the input terminal of the person,
The first voltage A applied to the B input terminal, and the second
This circuit selectively outputs one of the voltages A and , and this selectively output voltage is applied to the A-D converter 2 as the above-mentioned upper limit reference voltage UB and lower limit reference voltage LB. In this embodiment, it is assumed that the input analog signal As changes between the value of the output voltage E of the power supply circuit 6 and the ground voltage, that is, within the range of E≧value of analog signal As≧0. .

Next, the operation of this device will be described in detail with reference to FIG.

Now, if the analog signal AS mentioned above is input to the input terminal IN, the sea case control circuit (not shown)
issues a control signal SH to the sample and hold circuit 1 at appropriate timing, and also issues a control signal SL to cause the selection circuit 5 to select the voltage of the A input terminal. As a result, the sample hold circuit 1 receives the control signal SH
The selection circuit 5 samples and holds the input analog signal As corresponding to the application timing of , and selects the output voltage E and the ground voltage of the power supply circuit 6 applied to the input terminal thereof to the upper limit reference voltage UB and lower limit reference voltage LB, respectively. It is added to the A-D converter 2 as a signal. The relationship between the sample and hold signal ASH, the upper limit reference voltage UB, and the lower limit reference voltage LB applied to the A-D converter 2 at this point is, for example, at points P, P2, and P in FIG. 2, respectively.

Suppose that it is as shown in .

In the A-D converter 2, based on the application of the above-mentioned signals, the voltage between the power supply voltage E, which is the upper limit reference voltage UB, and the ground voltage, which is the lower limit reference voltage LB, is divided into 16 levels as described above. , of which the sample hold signal ASH is
The code of the quantization level corresponding to the level of
In the example shown in the figure, the code indicating the quantization level at point P4 is output as the converted digital signals D1 to D4.

This output digital signal ~D4 is latched by a latch circuit 3 under the control of a sequence control circuit (not shown), and further inputted to a DA converter 4.

As described above, the D-A converter 4 performs D-A conversion based on the input digital signal ~D4, and converts the input digital signal ~D4 into a first voltage A1 corresponding to the quantization level of ~D4. , and the same signal, ~1 from the quantization level of D4
a second voltage A2 corresponding to a level below the quantization level;
Output each. These first and second voltages A,
and A.

In the example shown in FIG. 2, these correspond to voltages having levels indicated by points P4 and P, respectively.

When the D-A conversion is performed in this manner, the sequence control circuit then issues a control signal SL to cause the selection circuit 5 to select the voltage at the B input terminal. As a result, the A-D converter 2
are the first and second voltages A1 and A, which are the DA conversion outputs.

A-to-D conversion is performed on the sample-and-hold signal ASH by setting them as the upper limit reference voltage UB and the lower limit reference voltage LB, respectively. That is, the same A-D converter 2 is now connected to the first
and the second voltages A1 and A are divided into 16 levels, and the code of the skeletonized level corresponding to the level of the sample-and-hold signal ASH is determined according to the example shown in FIG. In other words, the code indicating the quantization level of point P is output as the converted digital signal ~D4.In order to distinguish it from the first A-D converted signal, the following will describe the same sample-and-hold signal ASH. 2
The second A-D conversion signal is converted into digital signals D1' to D4'.
shall be.

In the quantized signal processing circuit (not shown), as shown in FIG. Conversion digital signal D
, 1 to D4' as the lower 4 bits, a total of 8 bits of quantized signal is accepted as the output of the embodiment A-D converter,
The sampling level of the input analog signal A8 is determined based on the content of the doji conversion signal with 8-bit resolution. Of course, the above-described operation of the device of this embodiment is executed every time the input analog signal As is sampled and held, and the same quantization signal processing circuit also performs the following operations:
Each time the A/D conversion operation of the embodiment device is executed twice, the quantized signal consisting of 8 bits is received to grasp the change in the input analog signal.

In the above-described embodiment, the A-D converter 2 converts the code of the quantization level closest to the level of the input sample-and-hold signal ASH, corresponding to the higher level, into the digital signal, -D. , the D-A converter 4 also outputs the digital signal as the second voltage A, which corresponds to a level one quantization level lower than the gist level of ~D4. This was set as the lower limit reference voltage LB for the second A-D conversion of the A-D converter 2. However, due to the configuration of the A-D converter 2, If the code corresponding to the lower level among the quantization levels closest to the level of the hold signal ASI-1 is output as the digital signals D1 to D4, the DA converter 4 also outputs the code corresponding to the lower level. A voltage corresponding to a level one quantization level higher than the quantization level of the digital signals D1 to D4 is formed and outputted as the second voltage A2, and this is used as the second voltage A2 of the A-D converter 2. -The upper limit reference voltage UB is set at the time of D conversion.

Further, in the above embodiment, A having a resolution of 4 bits
- The case where the input analog signal As is quantized with an 8-bit resolution based on two A-D conversion operations of the D converter 2 has been shown. The setting of the number of A-D conversions is arbitrary and can be freely set depending on the final desired resolution or the situation of the installation space.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an A/D conversion device according to the present invention, and FIG. 2 is a diagram for explaining an example of the operation of the embodiment device shown in FIG. 1...Sample hold circuit, 2.A-D converter, 3
. . . Latch circuit, 4. DA converter, 5. Selection circuit, 6. Power supply circuit.

Claims (2)

[Claims] (1) An A-D conversion method of quantizing an appropriately sampled and held analog signal.The analog signal was A-D converted using two different voltages set in advance as an upper limit reference voltage and a lower limit reference voltage, respectively. After this A-D
The voltage corresponding to the quantized signal obtained by the conversion and the voltage corresponding to the signal one quantization level below or above the quantized signal are respectively defined as an upper limit reference voltage and a lower limit reference voltage, or a lower limit reference voltage and an upper limit reference voltage. An A/D conversion method, characterized in that the analog signal is A/D converted a predetermined number of times to obtain a quantized signal with a desired resolution. (2) A sample-and-hold circuit that samples and holds the input analog signal, and a sample-and-hold circuit that samples and holds the input analog signal.
- an A-D converter that performs D conversion; a latch circuit that latches the A-D converted quantized signal; and a latch circuit that corresponds to the latched quantized signal and one quantization level below or above the quantized signal. a D-A converter that converts a signal to form a first voltage and a second voltage, respectively;
At the time of A-D conversion at the first entrance of the D converter, the preset 2
applying third and fourth voltages of different types to the A-reverse converter as an upper limit reference voltage and a lower limit reference voltage, respectively;
During the second and subsequent A-D conversions of the same A-D converter, the first voltage and the second voltage are converted into the upper limit reference voltage and the lower limit reference voltage, or the lower limit reference voltage and the upper limit reference voltage, respectively. An A/D converter, comprising a selection circuit added to the A/D converter, and sequentially and parallelly samples outputs of the A/D converter to obtain a quantized signal with a desired resolution.