JPS6024603B2 - FET oscillator - Google Patents

FET oscillator

Info

Publication number
JPS6024603B2
JPS6024603B2 JP1423377A JP1423377A JPS6024603B2 JP S6024603 B2 JPS6024603 B2 JP S6024603B2 JP 1423377 A JP1423377 A JP 1423377A JP 1423377 A JP1423377 A JP 1423377A JP S6024603 B2 JPS6024603 B2 JP S6024603B2
Authority
JP
Japan
Prior art keywords
gate
changes
oscillation frequency
fet
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1423377A
Other languages
Japanese (ja)
Other versions
JPS5399857A (en
Inventor
敬郎 新川
寛治 庄山
忠一 袖山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1423377A priority Critical patent/JPS6024603B2/en
Priority to US05/873,526 priority patent/US4187476A/en
Priority to DE2803846A priority patent/DE2803846C2/en
Publication of JPS5399857A publication Critical patent/JPS5399857A/en
Publication of JPS6024603B2 publication Critical patent/JPS6024603B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/18Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/0014Structural aspects of oscillators
    • H03B2200/0024Structural aspects of oscillators including parallel striplines
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006Functional aspects of oscillators
    • H03B2200/0062Bias and operating point
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/18Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance
    • H03B5/1841Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator
    • H03B5/1847Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device
    • H03B5/1852Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising distributed inductance and capacitance the frequency-determining element being a strip line resonator the active element in the amplifier being a semiconductor device the semiconductor device being a field-effect device

Description

【発明の詳細な説明】 本発明は、ゲートに共振回路を挿入して発振させるマイ
クロ波のFET(電界効果トランジスタ)発振器の構成
及び、その発振周波数の温度補償に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a microwave FET (field effect transistor) oscillator that oscillates by inserting a resonant circuit into its gate, and to temperature compensation of its oscillation frequency.

マイクロストリップ線路を基本構成とする平面回路へF
ETを接着した発振器として、第1図に示す回路がよく
知られている。FET素子1のゲート2の希望発振周波
数のほぼき波長の長さの共振器3を接続し、このゲート
2へはチョークのバィアス回路4からゲート電圧を印加
する。また、FETIのソース5へは帰還回路6を接続
して接地し、ドレイン7へは、出力線路8とチョークの
バイアス回路9が接続され、出力線路8は容量10で直
流的に遮断されている。本構成を用いると、ソースの帰
還回路6を通してゲート2とドレィン7の間に帰還を生
じ、FETIはゲートの共振器3の周波数で発振し、発
振出力はドレィンの出力線路8から取り出される。
F to a planar circuit whose basic configuration is a microstrip line
The circuit shown in FIG. 1 is well known as an oscillator with an ET bonded thereto. A resonator 3 having a length approximately equal to the desired oscillation frequency of the gate 2 of the FET element 1 is connected, and a gate voltage is applied to the gate 2 from a choke bias circuit 4. Further, a feedback circuit 6 is connected to the source 5 of the FETI and grounded, an output line 8 and a choke bias circuit 9 are connected to the drain 7, and the output line 8 is cut off in terms of DC by a capacitor 10. . When this configuration is used, feedback is generated between the gate 2 and the drain 7 through the source feedback circuit 6, the FETI oscillates at the frequency of the gate resonator 3, and the oscillation output is taken out from the drain output line 8.

このFET発振器は発振効率がよくて出力も大きい。ま
た普通、ゲート2は負電圧で駆動し、発振周波数はゲー
トの印加電圧を変えると、変わる特徴をもつ。しかし、
本発振器の発振周波数は、ゲート2からみたFEHIの
インピーダンスと共振器3のインピーダンスによって決
まるため、複数の周波数で発振条件を満たすため、発振
周波数がジャンプして他の周波数に移ったり、温度変化
でゲート2からみたFETIのインピーダンスが変化し
て、発振周波数が変化するので、発振周波数の温度安定
度が悪い欠点をもっていた。この発振周波数の温度安定
度の実測値は、100〜20舵PM/。0である。
This FET oscillator has good oscillation efficiency and large output. Further, normally, the gate 2 is driven with a negative voltage, and the oscillation frequency has a characteristic that changes by changing the voltage applied to the gate. but,
The oscillation frequency of this oscillator is determined by the impedance of the FEHI seen from the gate 2 and the impedance of the resonator 3, so in order to satisfy the oscillation conditions at multiple frequencies, the oscillation frequency may jump to another frequency or change due to temperature changes. Since the impedance of the FETI seen from the gate 2 changes and the oscillation frequency changes, the oscillation frequency has a disadvantage of poor temperature stability. The actual value of the temperature stability of this oscillation frequency is 100 to 20 rudder PM/. It is 0.

第2図は、ドレィン7を接地して、ソース5に接続され
た出力線路11から出力するFET発振器の従来例であ
る。
FIG. 2 shows a conventional example of an FET oscillator that outputs from an output line 11 connected to a source 5 with a drain 7 grounded.

本構成では、ソース5とゲート2の間の内部帰還量が大
きいため、帰還回路を外部に形成する必要はなく、ゲー
ト2へ共振器3を取り付けると発振する。
In this configuration, since the amount of internal feedback between the source 5 and the gate 2 is large, there is no need to form a feedback circuit externally, and when the resonator 3 is attached to the gate 2, oscillation occurs.

ただし、バイアス回路4と12には負の電圧を必要とす
る。この構成の発振器においても、第1図で示した欠点
は同じである。本発明の目的は、上記した従来技術の欠
点をなくし、簡単な構成で、発振周波数のジャンプと温
度安定度を改善したFET発振器を提供するにある。
However, bias circuits 4 and 12 require negative voltage. The oscillator with this configuration also has the same drawbacks as shown in FIG. SUMMARY OF THE INVENTION An object of the present invention is to provide an FET oscillator which eliminates the above-mentioned drawbacks of the prior art, has a simple configuration, and has improved oscillation frequency jump and temperature stability.

本発明の構成は、ゲートに接続する共振器と並列にダミ
ー抵抗を接続し、このダミー抵抗と、電源とゲート間に
挿入した抵抗との分圧でゲート電圧を供給し、そのダミ
ー抵抗と、電源とゲート間に挿入した抵抗に直列にバリ
ス夕等の感V熱半導体を挿入して成るものである。
The configuration of the present invention is to connect a dummy resistor in parallel with the resonator connected to the gate, supply a gate voltage by dividing the voltage between this dummy resistor and a resistor inserted between the power supply and the gate, and connect the dummy resistor to the resistor. It is constructed by inserting a V heat-sensitive semiconductor such as a varistor in series with a resistor inserted between the power source and the gate.

これにより共振器の共振周波数以外の周波数では、ゲー
トがダミー抵抗で終端されるため発振しない。従って、
発振周波数のジャンプもないし、バイアス回路に挿入し
たバリスタ等の半導体は周囲温度が変わると端子電圧が
変化するため、ゲートの電圧も変化して発振周波数を一
定に保つ効果をもて)。
As a result, at frequencies other than the resonant frequency of the resonator, oscillation does not occur because the gate is terminated with a dummy resistor. Therefore,
There is no jump in the oscillation frequency, and since the terminal voltage of semiconductors such as varistors inserted in the bias circuit changes when the ambient temperature changes, the gate voltage also changes, which has the effect of keeping the oscillation frequency constant).

以下、本発明を図に示す実施例に従い詳細に説明する。Hereinafter, the present invention will be explained in detail according to embodiments shown in the drawings.

第3図に本発明の実施例を示す。第1図で示した従来例
のゲート2に接続した共振器13と並列に線路14を介
してダミー抵抗13(抵抗値をrとする)が接続され、
ゲートバイアスのチョーク14と電源端子間には抵抗1
7(抵抗値をRとする)とバリスタ16が直列に挿入さ
れる。共振器13の共振周波数以外では、ゲート2から
共振器13および線路14をみたインピーダンスはダミ
ー抵抗15がみえ、発振条件を満たさない。従って共振
器13の共振周波数以外では、発振しないため発振周波
数のジャンプはない。第4図に、第3図におけるゲート
電圧供V給回路を示す。
FIG. 3 shows an embodiment of the present invention. A dummy resistor 13 (resistance value is r) is connected via a line 14 in parallel with the resonator 13 connected to the gate 2 of the conventional example shown in FIG.
A resistor 1 is connected between the gate bias choke 14 and the power supply terminal.
7 (resistance value is R) and a varistor 16 are inserted in series. At frequencies other than the resonant frequency of the resonator 13, the dummy resistor 15 is visible in the impedance of the resonator 13 and the line 14 seen from the gate 2, and the oscillation condition is not satisfied. Therefore, the oscillation frequency does not oscillate at frequencies other than the resonant frequency of the resonator 13, so there is no jump in the oscillation frequency. FIG. 4 shows the gate voltage supply V supply circuit in FIG. 3.

第4図からわかるように、ゲート2の端子19に印加す
る電圧Vcは、ゲートが負電圧で駆動されるため電源端
子18の電圧を−V、バリスタ16の端子電圧をVBと
すると、(−V+VB)r VG= R+r で表わされる。
As can be seen from FIG. 4, since the gate is driven with a negative voltage, the voltage Vc applied to the terminal 19 of the gate 2 is (- V+VB)r VG=R+r.

いま、バリスタ16の端子電圧VBが周囲温度の変化で
△VB変化したとすると、ゲート電圧V′cは、V′G
=←V+V8十△VBX←V+VB)r十会≦羊R+r
= R+rとなり、ゲート電圧は合苧;だけ変化
する。
Now, if the terminal voltage VB of the varistor 16 changes by △VB due to a change in ambient temperature, the gate voltage V'c becomes V'G
=←V+V8△VBX←V+VB)rJukai≦SheepR+r
= R+r, and the gate voltage changes by the amount.

通常、バリス外ま−3机V/℃の端子電圧の変化をする
こ砂ら・ゲ‐ト電圧は諸肌v/℃の変化をする。
Normally, while the terminal voltage outside the varisse changes by -3 V/°C, the gate voltage changes by approximately -3 V/°C.

さらに、ゲート電圧VGを変えた時の発振周波数の変化
を△Lとし、周囲温度による発振周波数の変化を△f2
とすると、△f,十△f2=0となるようにゲート電圧
VGが周囲温度に対して変化すれば、発振周波数は周囲
温度が変化しても一定に保たれる。
Furthermore, the change in oscillation frequency when the gate voltage VG is changed is △L, and the change in oscillation frequency due to ambient temperature is △f2.
If the gate voltage VG changes with respect to the ambient temperature so that Δf, 0, Δf2=0, the oscillation frequency will be kept constant even if the ambient temperature changes.

1的HZ帯で行ったFET発振器の実測値は、△Lが一
5■MH区/Vであり、△f2は−0.8MHZ/00
であった。
The actual measured values of the FET oscillator in the normal HZ band are that △L is 15MHZ/V, and △f2 is -0.8MHZ/00
Met.

従って周囲温度の変化に対するゲート電圧の変化による
発振周波数の変化は篭葦MHZノ℃となり・これが△f
2と逆特性の0.8MHZ・℃と等しくなればよい。そ
こで、ゲート電圧VGの変化を大きくするには、第5図
に示すようにバリスタ16を複数個直列に挿入すれば良
い。
Therefore, the change in oscillation frequency due to the change in gate voltage with respect to the change in ambient temperature becomes MHZ no °C, and this is △f
2 and 0.8 MHZ·°C, which has the opposite characteristic. Therefore, in order to increase the change in the gate voltage VG, a plurality of varistors 16 may be inserted in series as shown in FIG.

いま、バリスタをn個使用したとすると周囲温度の変化
によるゲート電圧の変化はn倍となり、次式帯岸=o.
5M町ノ℃ が成り立つようにR,rおよびnを選ぶことにより、周
囲温度が変わっても発振周波数は変化しないFET発振
器が構成できる。
Now, if n varistors are used, the change in gate voltage due to a change in ambient temperature will be n times greater, and the following equation: O.
By selecting R, r, and n so that 5M town no.degree. C. holds true, it is possible to construct an FET oscillator whose oscillation frequency does not change even if the ambient temperature changes.

本発明は、第2図の従来例で示したドレィン接地のFE
T発振器にも同様の効果をもつことは明らかである。ま
た、第6図に示すように、容量22とチョーク21等を
用いてソース5へ正の電圧を印加すると、ゲートは正の
電圧で駆動できる。
The present invention is based on the drain grounded FE shown in the conventional example shown in FIG.
It is clear that the T oscillator has a similar effect. Further, as shown in FIG. 6, if a positive voltage is applied to the source 5 using the capacitor 22, choke 21, etc., the gate can be driven with a positive voltage.

この場合、周囲温度の変化に対して、発振周波数を一定
に保つためには、ダミー抵抗15の例にバリスタ23を
挿入しなければならない。
In this case, in order to keep the oscillation frequency constant against changes in ambient temperature, a varistor 23 must be inserted in place of the dummy resistor 15.

この時ダミー抵抗15を容量24で高周波的に接地して
もよい。
At this time, the dummy resistor 15 may be grounded using the capacitor 24 at high frequency.

この構成を用いるとこの場合のゲート電圧供給回路を示
す第7図から、ゲート電圧は周囲温度の変化に対して、
V′G=W−VB−△V8×十くV8十△V8)={S
毒害と十V8}十会≦事R+rとなり、バリス夕の端子
電圧の変化は負の係数であるため、周囲温度に対する発
振周波数の変化を打ち消すことができるのは、第3図か
ら第5図までで説明したように明からである。
Using this configuration, it can be seen from FIG. 7, which shows the gate voltage supply circuit in this case, that the gate voltage changes as the ambient temperature changes.
V'G=W-VB-△V8×10 V80△V8)={S
Poison damage and 10 V8} 10 times ≦ R + r, and the change in the terminal voltage of the varistor is a negative coefficient, so the changes in the oscillation frequency with respect to the ambient temperature can be canceled out from Figures 3 to 5. As explained in , it is from Ming.

もし、ダミー抵抗15を、発振周波数のジャンプ防止に
は小さく、発振周波数の温度補償用としては大きく取り
たい場合、第8図に示すようにダミー抵抗15を分割し
、その途中を高周波的に容量24で短絡しても、本発明
の効果は同じである。
If you want to use a small dummy resistor 15 to prevent jumps in the oscillation frequency, but a large one to compensate for the temperature of the oscillation frequency, divide the dummy resistor 15 as shown in Figure 8, and add a high-frequency capacitor in the middle. Even if 24 is short-circuited, the effect of the present invention is the same.

本実施例ではバーJスタを用いて説明したが、これに限
るものではなく、周囲の温度変化によって端子電圧が変
化する感熱半導体でも本発明の効果は同じである。
Although the present embodiment has been described using a bar J star, the present invention is not limited to this, and the effects of the present invention are the same even in a heat-sensitive semiconductor whose terminal voltage changes depending on changes in ambient temperature.

また、本実施例では、ゲートの共振器として終端開放の
線路を用いたが、これに限るものではなく、第9図に示
すようにゲートの側面から接近させて結合する共振器2
5でも本発明の効果は同じである。
Further, in this embodiment, an open-ended line is used as the gate resonator, but the line is not limited to this, and as shown in FIG.
5, the effect of the present invention is the same.

以上述べたように、本発明によれば、共振器の共振周波
数以外の周波数ではダミー抵抗とした第1の抵抗によっ
て発振しないため発振周波数のジャンプを防止でき、ゲ
ート電圧供給回路に挿入したバリスタの端子電圧が周囲
温度で変化するためゲートの印加電圧が変化して、周囲
温度の変化に関係なく発振周波数を一定に保つ効果があ
る。
As described above, according to the present invention, since oscillation is not caused by the first resistor, which is a dummy resistor, at frequencies other than the resonant frequency of the resonator, jumps in the oscillation frequency can be prevented, and the varistor inserted in the gate voltage supply circuit can be Since the terminal voltage changes with the ambient temperature, the voltage applied to the gate changes, which has the effect of keeping the oscillation frequency constant regardless of changes in the ambient temperature.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はゲートに共振器をもつソース接地のFET発振
器の従釆例を示す図、第2図はゲートに共振器をもつ、
ドレィン接地のFET発振器の従来例を示す図、第3図
は本発明の一実施例を示す接続図、第4図及び第5図は
第3図の動作を説明するためのゲート電圧供給回路図、
第6図は本発明の他の実施例の接続図、第7図及び第8
図は第6図の動作を説明するためのゲート電圧供給回路
図、第9図は本発明の更に他の実施例の接続図である。 2:FETゲート、15:第1の抵抗(ダミー抵抗)、
16:バリスタ、17:第2の抵抗、18:電源端子、
19:ゲート端子、23:バリスタ。オ′筋 オZ図 オ4図 ゲ3図 矛J図 ガム図 才ワ図 がJ図 オ?図
Figure 1 is a diagram showing a follow-up example of a source-grounded FET oscillator with a resonator at the gate, and Figure 2 is a diagram showing a follow-up example of a source-grounded FET oscillator with a resonator at the gate.
A diagram showing a conventional example of a drain-grounded FET oscillator, FIG. 3 is a connection diagram showing an embodiment of the present invention, and FIGS. 4 and 5 are gate voltage supply circuit diagrams for explaining the operation of FIG. 3. ,
Figure 6 is a connection diagram of another embodiment of the present invention, Figures 7 and 8.
This figure is a gate voltage supply circuit diagram for explaining the operation of FIG. 6, and FIG. 9 is a connection diagram of still another embodiment of the present invention. 2: FET gate, 15: first resistor (dummy resistor),
16: Varistor, 17: Second resistor, 18: Power supply terminal,
19: Gate terminal, 23: Varistor. O'muscle O Z figure O 4 figure ge 3 figure J figure gum figure talented Wa figure is J figure O? figure

Claims (1)

【特許請求の範囲】[Claims] 1 マイクロストリツプ線路を基本構成とする平面回路
にFETを設けた発振器において、上記FETのゲート
に共振回路を設け、このゲートへ上記共振回路と並列に
ダミー抵抗を接続し、このダミー抵抗を上記共振回路の
共振周波数より離れた周波数ではゲートに接続されるイ
ンピーダンスがほぼこのダミー抵抗によつて決定される
抵抗値とし、かつ、上記ゲートにバイアス電圧を供給す
るバイアス回路が上記ダミー抵抗を含めて構成されると
ともに、このバイアス回路に感熱半導体を設けたことを
特徴とするFET発振器。
1. In an oscillator in which an FET is provided in a planar circuit whose basic configuration is a microstrip line, a resonant circuit is provided at the gate of the FET, a dummy resistor is connected to this gate in parallel with the resonant circuit, and the dummy resistor is At frequencies apart from the resonant frequency of the resonant circuit, the impedance connected to the gate has a resistance value approximately determined by this dummy resistor, and the bias circuit that supplies bias voltage to the gate includes the dummy resistor. 1. A FET oscillator characterized in that the bias circuit is provided with a heat-sensitive semiconductor.
JP1423377A 1977-01-31 1977-02-14 FET oscillator Expired JPS6024603B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1423377A JPS6024603B2 (en) 1977-02-14 1977-02-14 FET oscillator
US05/873,526 US4187476A (en) 1977-01-31 1978-01-30 SHF band oscillator circuit using FET
DE2803846A DE2803846C2 (en) 1977-01-31 1978-01-30 Centimeter wave oscillator circuit with a field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1423377A JPS6024603B2 (en) 1977-02-14 1977-02-14 FET oscillator

Publications (2)

Publication Number Publication Date
JPS5399857A JPS5399857A (en) 1978-08-31
JPS6024603B2 true JPS6024603B2 (en) 1985-06-13

Family

ID=11855347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1423377A Expired JPS6024603B2 (en) 1977-01-31 1977-02-14 FET oscillator

Country Status (1)

Country Link
JP (1) JPS6024603B2 (en)

Also Published As

Publication number Publication date
JPS5399857A (en) 1978-08-31

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