JPS60244097A - Hybrid electronic circuit - Google Patents
Hybrid electronic circuitInfo
- Publication number
- JPS60244097A JPS60244097A JP59098606A JP9860684A JPS60244097A JP S60244097 A JPS60244097 A JP S60244097A JP 59098606 A JP59098606 A JP 59098606A JP 9860684 A JP9860684 A JP 9860684A JP S60244097 A JPS60244097 A JP S60244097A
- Authority
- JP
- Japan
- Prior art keywords
- built
- substrate
- capacitor
- hybrid electronic
- magnetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 本発明は混成電子回路に関する。[Detailed description of the invention] The present invention relates to hybrid electronic circuits.
電子部品の集積化に伴って、コイル、コンデンサ、抵抗
等が積層技術によって作成されるようになっている。し
かし、集積化を進めると、特に配線や電極、コイル導体
などの間で容量結合が生じて集積化の妨げとなっている
。With the increasing integration of electronic components, coils, capacitors, resistors, etc. are being manufactured using lamination technology. However, as integration progresses, capacitive coupling occurs particularly between wiring, electrodes, coil conductors, etc., which hinders integration.
本発明の目的は、集積度が高く且つ搭載または内蔵され
る素子間の容量結合が小さい混成電子部品を提供するこ
とにある。本発明の他の目的は、容量素子は誘電体基板
に、インダクタンス素子は誘電体に、それぞれ集中的に
作り込まれて集積度を高めた混成電子回路を提供するこ
とにある。An object of the present invention is to provide a hybrid electronic component that has a high degree of integration and has low capacitive coupling between mounted or built-in elements. Another object of the present invention is to provide a hybrid electronic circuit in which the capacitive elements are intensively formed in the dielectric substrate and the inductance elements are intensively formed in the dielectric, thereby increasing the degree of integration.
本発明の混成電子回路は、複数のインダクタを内蔵する
絶縁性磁性体基板と、複数のコンデンサを内蔵する誘電
体基板と、前記磁性体基板及び誘電体基板の表面に被覆
されたガラス等の絶縁層と、前記絶縁層の表面に設けら
れた抵抗体及び半導体部品等とから成る。The hybrid electronic circuit of the present invention includes an insulating magnetic substrate containing a plurality of inductors, a dielectric substrate containing a plurality of capacitors, and an insulating material such as glass coated on the surfaces of the magnetic substrate and the dielectric substrate. The insulating layer includes a resistor, a semiconductor component, etc. provided on the surface of the insulating layer.
かかる構成によると、ガラス等の絶縁層により回路部分
間の結合が避けられて集積度を上げることができる。ま
た、インダクタ部分は磁性体基板に、コンデンサ部分は
誘電体基板に、そして抵抗は絶縁層の表面に形成される
ため、集積の際の工程が著しく単純化される。According to this configuration, the insulating layer made of glass or the like prevents coupling between circuit parts, thereby increasing the degree of integration. Further, since the inductor portion is formed on the magnetic substrate, the capacitor portion is formed on the dielectric substrate, and the resistor is formed on the surface of the insulating layer, the integration process is significantly simplified.
本発明の実施例によると、磁性体基板と誘電体基板とは
平面状に並置した形を有し、それらの表面に共通のガラ
ス層等を有しても良いし、或いは磁性体基板及び誘導体
基板の各々にガラス層等を形成し、順次積層合体し、最
上面に抵抗体を形成しても良い。前者の方が表面利用率
が高いが、後者では平面投影面積が小さく、機械的強度
が高い利点が得られる。According to the embodiments of the present invention, the magnetic substrate and the dielectric substrate may have a shape in which they are juxtaposed in a plane, and may have a common glass layer or the like on their surfaces, or the magnetic substrate and the dielectric substrate may have a common glass layer or the like on their surfaces. A glass layer or the like may be formed on each of the substrates, and the substrates may be sequentially laminated and combined, and a resistor may be formed on the uppermost surface. The former has a higher surface utilization rate, but the latter has the advantage of a smaller planar projected area and higher mechanical strength.
以下本発明の実施例を図面に関連して詳しく説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
実施例1 第1図は平板形の混成電子回路の斜視図を示す。Example 1 FIG. 1 shows a perspective view of a planar hybrid electronic circuit.
本例では混成電子回路は平面型で3つの領域に区分され
ており、インダクタ内蔵磁性体基板人を含む部分、コン
デンサ内蔵高誘電率誘電体基板Bを含む部分、コンデン
サ内蔵低誘電率誘電体基板Cを含む部分及びアンテナ部
基板りより成っている。In this example, the hybrid electronic circuit is planar and divided into three areas: a part containing a magnetic substrate with a built-in inductor, a part containing a high-permittivity dielectric substrate B with a built-in capacitor, and a part containing a low-permittivity dielectric substrate with a built-in capacitor. It consists of a part including C and an antenna part substrate.
これらの基板は適当な結合用粉末を介在した状態で共焼
成したり、或いは共通の支持基板の上で共焼成するなど
の任意の方法で製造しうる。These substrates can be manufactured by any method such as co-firing with a suitable bonding powder or co-firing on a common support substrate.
基板A、B、C,Dの製造は従来知られている方法によ
り製造することができる。以下にはそれらのうち1例に
ついて説明する。The substrates A, B, C, and D can be manufactured by conventionally known methods. One example of these will be described below.
第2図はインダクタ内蔵基板Aの製造時における積層構
造を示し、電気抵抗の大きい軟磁性フェライト粉末のペ
ーストの印刷により製作された磁性薄板1.2.3.4
と、AgSAg−Pd、等の導電粉末のペーストより製
作されコイルの約手ターン分を形成するように磁性薄板
1.2.3.4の面に印刷された導体片5.6.7.8
との交互積層で積層体が形成され、その際に、点線で示
す各層の境界位置で導体片同志が重畳して電気的な接続
を行うようになっている。従って、磁性薄板積層体中で
始端8より終端Fまでの導体コイルが形成される。この
積層体を焼成し、その後8.Fのところに外部回路接続
用の外部端子を焼付けることでインダクタ基板を完成す
る。なお、第2図は便宜上単一のインダクタを内蔵する
例を示したが、一般には同様な積層技術を用いて複数の
インダクタを同時に内蔵する磁性体基板人を得るもので
ある。Figure 2 shows the laminated structure of the inductor built-in board A during manufacture, and shows a magnetic thin plate 1.2.3.4 manufactured by printing a paste of soft magnetic ferrite powder with high electrical resistance.
and a conductor piece 5.6.7.8 made from a paste of conductive powder such as AgSAg-Pd and printed on the surface of the magnetic thin plate 1.2.3.4 so as to form approximately one turn of the coil.
A laminate is formed by alternately laminating the conductor pieces, and at this time, the conductor pieces overlap each other at the boundary positions of each layer indicated by dotted lines to establish electrical connection. Therefore, a conductor coil from the starting end 8 to the ending end F is formed in the magnetic thin plate laminate. This laminate is fired, and then 8. Complete the inductor board by baking an external terminal for external circuit connection at F. Although FIG. 2 shows an example in which a single inductor is built in for the sake of convenience, a similar lamination technique is generally used to obtain a magnetic substrate in which a plurality of inductors are built in at the same time.
第3図はコンデンサ内蔵高m寛率誘電体基板2の製造例
を示す。図中10.11.12.13は高誘電率誘電体
粉末のペーストから印刷して形成される誘電体薄板を示
し、第2図に関連して述べ丸ものと同様な導体ペースト
を誘電体薄板10.11.12.15の各表面に印刷す
る仁、とにより電極薄層14.15.16.17.18
.19.20.21としたもので、電極の端部は積層体
の外周縁に引出される。上記の積層は下から上に順に行
い、その後焼結し外部端子を引出端へ焼付けてコンデン
サ内蔵誘電体基板Bとする。この基板2も一般には任意
容量及び個数のコンデンサを内蔵するように製造される
。FIG. 3 shows an example of manufacturing a high-m tolerance dielectric substrate 2 with a built-in capacitor. In the figure, 10.11.12.13 shows a dielectric thin plate formed by printing from a paste of high dielectric constant dielectric powder. 10.11.12.15 Printing on each surface, and electrode thin layer 14.15.16.17.18
.. 19.20.21, and the ends of the electrodes are drawn out to the outer periphery of the laminate. The above lamination is carried out in order from the bottom to the top, and then sintering is performed to bake the external terminals to the lead-out ends to form the dielectric substrate B with a built-in capacitor. This substrate 2 is also generally manufactured so as to incorporate a desired capacitance and number of capacitors.
コンデンサ内蔵低誘電率誘電体基板C(7)製造は第3
図に関連して述べたと同様な方法によって行う。またア
ンテナ部りは基板人に準じて製造する。Manufacturing of low dielectric constant dielectric substrate C (7) with built-in capacitor is the third step.
This is done in a manner similar to that described in connection with the figure. Also, the antenna part will be manufactured in accordance with the board design.
第1図を再び参照する。基板A、B、Cは一体に結合さ
れており、それらの表面にはさらにガラスの層りが全面
に形成される。ガラス層りは、ガラス粉末のペーストを
結合した基板A、B、Cの全面に塗布または印刷し、高
温で融着させることによって製造しうる。このガラス層
の存在は極めてM要で、基板A、B、Cの表面に塔載さ
れる各種部品との間に電磁的干渉を回避して特性を良好
に保つ役割を果たす。Referring again to FIG. Substrates A, B, and C are bonded together, and a layer of glass is further formed over their surfaces. The glass layer can be produced by applying or printing a paste of glass powder over the entire surface of the bonded substrates A, B, C and fusing at high temperatures. The presence of this glass layer is extremely important, and serves to avoid electromagnetic interference with various components mounted on the surfaces of the substrates A, B, and C, thereby maintaining good characteristics.
なお、必要に応じて基板A、B及び(又は)Cの上に塔
載すべきIC,半導体等を埋設することができるように
凹所を設け、その上に上記のガラス層りを形成すること
ができる。In addition, if necessary, a recess is provided so that ICs, semiconductors, etc. to be mounted can be buried on the substrates A, B, and/or C, and the above glass layer is formed on the recess. be able to.
第1図に示すように、インダクタ内蔵基板人の部分はト
ランス部20、中間周波トランス部21、AM光発振コ
イル22、FM発発振コイ郡部23フィルタ部24など
に区分して構成され、それらの表面のガラス層Eの上に
抵抗器、コンデンサ等が塔載され、所定のプリント配!
(図示せず)により結線され、また内部インダクタの引
出端Tは外周辺に形成される。As shown in FIG. 1, the inductor built-in board part is divided into a transformer section 20, an intermediate frequency transformer section 21, an AM optical oscillation coil 22, an FM oscillation coil group section 23, a filter section 24, etc. Resistors, capacitors, etc. are mounted on the glass layer E on the surface, and the predetermined print layout is applied!
(not shown), and the lead-out end T of the internal inductor is formed on the outer periphery.
コンデンサ内蔵基板Bはコンデンサを中心とした回路網
を構成し、ガラス層Eの表面にIC,抵抗R1コンデン
サ等、所定の部品を塔載し、所定のプリント配線を施し
たものである。コンデンサ内蔵基板Cは同様に各種部品
を塔載する。各基板B、C,D内部の回路とガラス層E
の表面とは基板周辺に形成された外部端子Tを介して行
われることは基板人に関して述べたものと同様である。The capacitor-embedded board B constitutes a circuit network centered on capacitors, and has predetermined components such as an IC and a resistor R1 capacitor mounted on the surface of a glass layer E, and predetermined printed wiring. The capacitor built-in board C similarly mounts various parts. Circuits and glass layer E inside each board B, C, D
The surface of the board is connected to the external terminal T formed around the board in the same manner as described above regarding the board.
作用効果
以上の構成によると、回路のインダクタ及びコンデンサ
は各基板内に集中化されているから、回路の製造が単純
化される。また、全基板の表面にはガラス層Eが設けら
れるため、塔載される部品との間に電気的または磁気的
な結合が大幅に減じ、回路の品質が良くなる。本発明に
よると、電子装置の小型化を極限まで行うことができる
。Advantages and Effects According to the above configuration, the inductor and capacitor of the circuit are centralized in each board, thereby simplifying the manufacturing of the circuit. Furthermore, since the glass layer E is provided on the surface of all the substrates, electrical or magnetic coupling with mounted components is significantly reduced, improving the quality of the circuit. According to the present invention, electronic devices can be miniaturized to the maximum.
実施例2
第4図は本発明の他の実施例を示す。本例は各基板がガ
ラス層を介在して重畳合体された形の高集積混成電子回
路を提供する。本例は表面の利用効率が第1図の例より
も低いが、コンパクト性ではすぐれている。Embodiment 2 FIG. 4 shows another embodiment of the present invention. This example provides a highly integrated hybrid electronic circuit in which each substrate is stacked with a glass layer interposed therebetween. Although this example has lower surface utilization efficiency than the example shown in FIG. 1, it is superior in compactness.
第4図において、A′はインダクタ内蔵磁性体基板であ
って第1実施例の基板人と同様な構成を有し B/はコ
ンデンサ内蔵高誘電率誌寛体基板であって第1実施例の
基板Bと同様な構成を有し、CIはコンデンサ内蔵低誘
電率誘電体基板であって第1実施例の基板Cと同様の構
成を有し、さらにD′はアンテナコイル内蔵磁性体であ
って第1実施例のアンテナ部りと同様な構成を有する。In FIG. 4, A' is a magnetic substrate with a built-in inductor, which has the same structure as the substrate of the first embodiment, and B/ is a high dielectric constant magnetic substrate with a built-in capacitor, which is the same as that of the first embodiment. It has the same structure as the board B, CI is a low permittivity dielectric board with a built-in capacitor and has the same structure as the board C of the first embodiment, and D' is a magnetic body with a built-in antenna coil. It has the same configuration as the antenna section of the first embodiment.
各基板A′、B′、C′及びアンテナ部D′の間にはガ
ラス層Eが介在融着されていて基板間の分離を行い、ス
ペーシングの導入によって基板間の電気的・磁気的な結
合を減じている。アンテナ部の表面にもガラス層が融着
され、その上に各種半導体IC。A glass layer E is interposed and fused between each substrate A', B', C' and antenna part D' to separate the substrates, and by introducing spacing, electrical and magnetic Reducing bonds. A glass layer is also fused to the surface of the antenna section, and various semiconductor ICs are placed on top of it.
抵抗Rなどが塔載され、同じ表面のプリント配線(図示
せず)及び外部端子T′により所定の配線が行われてい
る。A resistor R and the like are mounted, and predetermined wiring is performed using printed wiring (not shown) on the same surface and an external terminal T'.
作用効果
上記の構成によると、基板A′、B′、C′及びアンテ
ナ部D′が重畳合体されており、第1実施例と同様に高
集積性及び高作業性を提供している。Effects According to the above structure, the substrates A', B', C' and the antenna portion D' are overlapped, and as in the first embodiment, high integration and high workability are provided.
さらに、ガラス層Eの介在により、回路素子間の電磁結
合が回避されるというすぐれた効果が達成される。Furthermore, the presence of the glass layer E achieves the excellent effect of avoiding electromagnetic coupling between circuit elements.
第1図は本発明の第1実施例による混成亀子回路を示す
斜視図、第2図は同回路のインダクタ内蔵磁性基板の製
造を示す斜視図、第3図は同回路のコンデンサ内蔵誘電
体基板を示す斜視図、及び第4図は本発明の第2実施例
を示す斜視図である。
図中上な部分は次の通りである。
人、A′ :インダクタ内蔵磁性体基板、B、B’ :
コンデンサ内蔵高誘電率誘電体基板cc’:コンデンサ
内蔵低誘電率誘電体基板D、D’ :アンテナ部
E、E’ ニガラス層
1.2.5.4:磁性体薄板
5.6.7.8:導体片
10.11.12.13 :誘電体薄板14.15.1
6.17.18.19.20.21:電極第1図
八
第4図FIG. 1 is a perspective view showing a hybrid Kameko circuit according to the first embodiment of the present invention, FIG. 2 is a perspective view showing the manufacture of a magnetic substrate with a built-in inductor of the same circuit, and FIG. 3 is a dielectric substrate with a built-in capacitor of the same circuit. FIG. 4 is a perspective view showing a second embodiment of the present invention. The upper part of the figure is as follows. Person, A': Magnetic substrate with built-in inductor, B, B':
High-permittivity dielectric substrate with built-in capacitor cc': Low-permittivity dielectric substrate with built-in capacitor D, D': Antenna section E, E' Glass layer 1.2.5.4: Magnetic thin plate 5.6.7.8 : Conductor piece 10.11.12.13 : Dielectric thin plate 14.15.1
6.17.18.19.20.21: Electrode Figure 1 Figure 8 Figure 4
Claims (1)
と、複数のコンデンサを内蔵する誘電体基板と、前記各
基板の表面に被覆されたガラス等の絶縁層と、前記絶縁
層の表面に設けられた抵抗体、半導体部品等の回路部品
と、該表面に形成されたプリント配線とから成る混成電
子回路。1. An electrically insulating magnetic substrate containing a plurality of inductors, a dielectric substrate containing a plurality of capacitors, an insulating layer such as glass coated on the surface of each substrate, and an insulating layer provided on the surface of the insulating layer. A hybrid electronic circuit consisting of circuit components such as resistors and semiconductor components, and printed wiring formed on the surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59098606A JPS60244097A (en) | 1984-05-18 | 1984-05-18 | Hybrid electronic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59098606A JPS60244097A (en) | 1984-05-18 | 1984-05-18 | Hybrid electronic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60244097A true JPS60244097A (en) | 1985-12-03 |
JPH0210598B2 JPH0210598B2 (en) | 1990-03-08 |
Family
ID=14224256
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59098606A Granted JPS60244097A (en) | 1984-05-18 | 1984-05-18 | Hybrid electronic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60244097A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62279622A (en) * | 1986-05-28 | 1987-12-04 | ティーディーケイ株式会社 | Laminated lc filter parts |
JPS6437024U (en) * | 1987-08-31 | 1989-03-06 | ||
JPS6464240A (en) * | 1987-09-03 | 1989-03-10 | Tdk Corp | Ic package |
JPH01101656A (en) * | 1987-10-15 | 1989-04-19 | Tdk Corp | Laminated integrated circuit |
JPH01165216A (en) * | 1987-12-21 | 1989-06-29 | Tdk Corp | Lamination buffered delay line |
JPH02224313A (en) * | 1989-02-27 | 1990-09-06 | Murata Mfg Co Ltd | Lc composite part |
JPH03166809A (en) * | 1989-11-27 | 1991-07-18 | Mitsubishi Materials Corp | Pi type emi filter network |
JPH04105311A (en) * | 1990-08-24 | 1992-04-07 | Murata Mfg Co Ltd | Multilayered capacitor |
JP2007290883A (en) * | 2006-04-21 | 2007-11-08 | Murata Mfg Co Ltd | Ferrite ceramic composition and laminated coil component using it |
JP2010251691A (en) * | 2009-03-27 | 2010-11-04 | Kyocera Corp | Wiring board |
JP2013205427A (en) * | 2012-03-27 | 2013-10-07 | Tdk Corp | Liquid crystal lens device and control method of the same |
-
1984
- 1984-05-18 JP JP59098606A patent/JPS60244097A/en active Granted
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62279622A (en) * | 1986-05-28 | 1987-12-04 | ティーディーケイ株式会社 | Laminated lc filter parts |
JPS6437024U (en) * | 1987-08-31 | 1989-03-06 | ||
JPS6464240A (en) * | 1987-09-03 | 1989-03-10 | Tdk Corp | Ic package |
JPH01101656A (en) * | 1987-10-15 | 1989-04-19 | Tdk Corp | Laminated integrated circuit |
JPH01165216A (en) * | 1987-12-21 | 1989-06-29 | Tdk Corp | Lamination buffered delay line |
JPH02224313A (en) * | 1989-02-27 | 1990-09-06 | Murata Mfg Co Ltd | Lc composite part |
JPH03166809A (en) * | 1989-11-27 | 1991-07-18 | Mitsubishi Materials Corp | Pi type emi filter network |
JPH04105311A (en) * | 1990-08-24 | 1992-04-07 | Murata Mfg Co Ltd | Multilayered capacitor |
JP2007290883A (en) * | 2006-04-21 | 2007-11-08 | Murata Mfg Co Ltd | Ferrite ceramic composition and laminated coil component using it |
JP2010251691A (en) * | 2009-03-27 | 2010-11-04 | Kyocera Corp | Wiring board |
JP2013205427A (en) * | 2012-03-27 | 2013-10-07 | Tdk Corp | Liquid crystal lens device and control method of the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0210598B2 (en) | 1990-03-08 |
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