JPS6023982Y2 - hybrid integrated circuit - Google Patents

hybrid integrated circuit

Info

Publication number
JPS6023982Y2
JPS6023982Y2 JP10074379U JP10074379U JPS6023982Y2 JP S6023982 Y2 JPS6023982 Y2 JP S6023982Y2 JP 10074379 U JP10074379 U JP 10074379U JP 10074379 U JP10074379 U JP 10074379U JP S6023982 Y2 JPS6023982 Y2 JP S6023982Y2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
hic
terminal
pitch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10074379U
Other languages
Japanese (ja)
Other versions
JPS5619037U (en
Inventor
晃 矢野
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP10074379U priority Critical patent/JPS6023982Y2/en
Publication of JPS5619037U publication Critical patent/JPS5619037U/ja
Application granted granted Critical
Publication of JPS6023982Y2 publication Critical patent/JPS6023982Y2/en
Expired legal-status Critical Current

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  • Gas-Filled Discharge Tubes (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【考案の詳細な説明】 本考案は混成集積回路(ハイブリッドIC1以下HIC
と呼ぶ)の構造に関する。
[Detailed explanation of the invention] This invention is based on hybrid integrated circuits (hybrid IC1 and below HIC).
).

一般に、HICはセラミック等の基材にスクリーン印刷
により配線パターン及び厚膜抵抗が形成され、半導体素
子のチップ等が、配線パターンとワイヤボンディングに
より接続され、内容物を気密に保つためセラミック材の
蓋あるいはエポキシ等充填材にて覆われ、入出力端より
ピンリードが外部に引出された構造をもっている。
In general, in HIC, a wiring pattern and a thick film resistor are formed by screen printing on a base material such as ceramic, and a semiconductor chip, etc. is connected to the wiring pattern by wire bonding, and a ceramic lid is placed to keep the contents airtight. Alternatively, it has a structure in which it is covered with a filler such as epoxy and has pin leads drawn out from the input and output ends.

また、HICの用途は多岐に互っているが、特にコアメ
モリアクセス回路や、放電表示板ドライブ回路のように
、所要回路数が多い上に、大電流または高電圧出力が要
求される分野に多用されている。
HICs are used in a wide variety of applications, especially in fields that require a large number of circuits and large current or high voltage outputs, such as core memory access circuits and discharge display board drive circuits. It is widely used.

一例として、放電表示板ドライブ回路への応用をながめ
てみる。
As an example, let's take a look at its application to a discharge display board drive circuit.

放電表示板は、一枚にX電極群とY電極群がそれぞれ形
成された2枚のガラス板が、各電極群が直角に対向する
様に放電空間を介して配置され、放電空間にはネオン等
のイオン化ガスが気密封止された構造をもち、例えば、
Y電極群の各電極を1本ずつ順次電気的に勧請し、Y電
極群の1電極が勧請されているとき、この電極上の表示
点灯すべき放電セルに対応するX電極群の各電極を電気
的に勧請して放電セルを点灯せしめて表示を得る、いわ
ゆる線順次走査方法により駆動される。
The discharge display board consists of two glass plates each having an X electrode group and a Y electrode group formed thereon, arranged with a discharge space in between so that each electrode group faces each other at right angles, and neon lights are placed in the discharge space. It has a structure in which ionized gas such as
Each electrode of the Y electrode group is electrically solicited one by one, and when one electrode of the Y electrode group is solicited, each electrode of the X electrode group corresponding to the discharge cell on which the display on this electrode is to be lit is It is driven by a so-called line sequential scanning method in which a display is obtained by electrically stimulating the discharge cells to light up.

放電表示板の勧請に要する電圧は一般に150〜250
■の高電圧であって、モノリシック集積回路にてドライ
バー回路を構成することは、現在のところ技術的困難を
伴い、経済的ではない。
The voltage required for soliciting a discharge display board is generally 150 to 250
(2) Constructing a driver circuit using a monolithic integrated circuit at high voltage is currently technically difficult and uneconomical.

従って、トランジスタ、抵抗器等の単体電気素子を使っ
て、ドライバー回路を組立てることになるが、例えば、
5×7ドツトで1文字を構成するマトリックス方式で3
波字×8行(25ff字)の表示を得るためには160
本のX電極群と56本のY電極群が必要となり、単体電
気素子にて全ドライバー回路を組むことは、全く経済性
に欠けるばかりでなく、ドライバー回路部の占める容積
が大きく、スペースフイクタの悪い表示装置となってし
まう。
Therefore, a driver circuit must be assembled using single electric elements such as transistors and resistors. For example,
3 using the matrix method where one character is composed of 5 x 7 dots.
160 to obtain a display of wavy characters x 8 lines (25ff characters)
A total of 56 X electrode groups and 56 Y electrode groups are required, and constructing the entire driver circuit with a single electric element is not only completely uneconomical, but also requires a large volume of space, and This results in a poor display device.

そこで、トランジスタのチップと厚膜抵抗等で構成でき
るHICの採用は非常に有効な手段となる。
Therefore, the adoption of HIC, which can be constructed from a transistor chip, a thick film resistor, etc., is a very effective means.

放電表示板の5〜6電極分のドライバー回路を1パツケ
ージのHICに組込んだ場合、表示装置の組立工数は数
分の1、回路部容積は半分以下に改善され得るからであ
る。
This is because if driver circuits for 5 to 6 electrodes of a discharge display board are incorporated into a single HIC package, the number of man-hours required for assembling the display device can be reduced to a fraction, and the circuit volume can be reduced to less than half.

さらにHICを採用した場合、ドライバー回路部だけで
なく、論理回路TTLのチップをも同一パッケージ内に
組込めるという利点もある。
Furthermore, when HIC is adopted, there is an advantage that not only the driver circuit section but also the logic circuit TTL chip can be incorporated into the same package.

さて、放電表示板の放電セルにて構成される画素のピッ
チは0.5〜17FEIF1程度のときに最も見易い文
字の大きさが得られる。
Now, when the pitch of the pixels constituted by the discharge cells of the discharge display panel is about 0.5 to 17FEIF1, the most legible character size can be obtained.

表示板の外部へX電極及びY電極を引出す端子部のピッ
チは、X電極及びY電極は、それぞれ表示板の相対する
2辺に引出せるので、画素ピッチの2倍即ち、1〜2m
sとなる。
The pitch of the terminal parts for drawing out the X electrodes and Y electrodes to the outside of the display board is twice the pixel pitch, or 1 to 2 m, because the X electrodes and Y electrodes can be drawn out to two opposing sides of the display board.
It becomes s.

ところでドライバー用HICの出力端子ピッチが、放電
表示板の端子ピッチと一致していれば、HICの出力端
子と放電表示板の端子を直線的に配線することができる
By the way, if the output terminal pitch of the driver HIC matches the terminal pitch of the discharge display board, the output terminals of the HIC and the terminals of the discharge display board can be wired linearly.

即ち、HICの出力端子リード線を放電表示板の端子に
直接接続する等、コネクタあるいはプリント配線基板に
よるピッチの変換手段を構する必要がなくなり、安価な
表示装置を提供することが可能となる。
That is, there is no need to provide a pitch conversion means using a connector or a printed wiring board, such as directly connecting the output terminal lead wire of the HIC to the terminal of the discharge display board, and it becomes possible to provide an inexpensive display device.

しかしながら、HICの出力端子ピッチを1〜2耽のピ
ッチで取出すためには、放電表示板のl電極分のドライ
バー回路を1〜2TlrrItの幅の範囲に納めねばな
らない。
However, in order to take out the output terminal pitch of the HIC at a pitch of 1 to 2 times, the driver circuit for 1 electrodes of the discharge display panel must be within a width range of 1 to 2 TlrrIt.

ドライバー回路1回路分が数個の素子で構成されるよう
な場合には、上記範囲内に納めることは物理的に非常に
困難であるばかりでなく、ファインパターン作製時の工
数増大、歩留低下、さらには、厚膜抵抗の面積不足によ
る信頼性の低下等、多くのマイナス要因を生ずることと
なる。
In cases where one driver circuit is composed of several elements, it is not only physically very difficult to keep it within the above range, but also increases the number of man-hours and decreases the yield when producing fine patterns. Furthermore, many negative factors will occur, such as a decrease in reliability due to insufficient area for the thick film resistor.

本考案の目的は、出力端子のピッチが例えば1〜2rr
vnと非常に細かく、しかも、製作が容易で、高信頼性
を有するHICの構成を提供することにある。
The purpose of the present invention is that the pitch of the output terminals is, for example, 1 to 2rr.
The object of the present invention is to provide an HIC configuration that is extremely detailed, easy to manufacture, and highly reliable.

本考案によれば、複数の入力端子と複数の出力端子とを
有する混成集積回路に於て、少なくとも1組の入力端子
と出力端子との形成された基板を各端子の引出面が平行
で離間するように複数枚重ねて構成腰かつ各基板の各出
力端子が重ね方向から見て重ならないように1本ごとに
交互に同一方向に引き出されていることを特徴とする混
成集積回路が得られる。
According to the present invention, in a hybrid integrated circuit having a plurality of input terminals and a plurality of output terminals, the substrate on which at least one set of input terminals and output terminals are formed is spaced apart with the lead-out surfaces of each terminal parallel to each other. A hybrid integrated circuit is obtained, which is constructed by stacking a plurality of boards in such a way that the output terminals of each board are alternately drawn out in the same direction one by one so that they do not overlap when viewed from the stacking direction. .

第1図a、 bは本考案の第1の実施例であり、第1図
aは正面図、第1図すは側面図である。
Figures 1a and 1b show a first embodiment of the present invention, with Figure 1a being a front view and Figure 1A being a side view.

第1の実施例では、ドライバー回路部は2分割されてそ
れぞれ第1のセラミック基板1と第2のセラミック基板
とに形成されて、それぞれセラミック酸のM3及び4で
覆われ、第1及び第2のセラミック基板は背中合せにエ
ポキシ系接着材等にて貼合わされる。
In the first embodiment, the driver circuit section is divided into two parts, formed on a first ceramic substrate 1 and a second ceramic substrate, respectively, and covered with ceramic acids M3 and 4, respectively. The ceramic substrates are bonded back to back using an epoxy adhesive or the like.

第1のセラミック基板からの出力端子5及び第2のセラ
ミック基板からの出力端子6の端子ピッチをそれぞれ2
.54mmとし、第1のセラミック基板と第2のセラミ
ックとで1.27TIIII&ずらして形成しておくこ
とにより、貼合わせた後の出力端子ピッチは1.272
FE+71となり、これは、放電表示板の端子ピッチと
同等であって、HICの出力端子リード線を放電表示板
の端子に直接接続する手段を可能にする。
The terminal pitch of the output terminals 5 from the first ceramic substrate and the output terminals 6 from the second ceramic substrate is 2, respectively.
.. 54 mm, and by forming the first ceramic substrate and the second ceramic substrate with a shift of 1.27TIII, the output terminal pitch after bonding is 1.272.
FE+71, which is equivalent to the terminal pitch of the discharge display board and allows a means of directly connecting the output terminal leads of the HIC to the terminals of the discharge display board.

また、ドライバー回路部は、2.547FIl!+の幅
の範囲内に組込めばよく、従来の1.27mmの倍のス
ペースを使える為、配線パターンに余裕がとれ、コスト
、信頼性ともに大幅に改善される。
Also, the driver circuit section is 2.547FIl! It only needs to be assembled within the + width range, and double the space of the conventional 1.27mm can be used, allowing for extra space in the wiring pattern, and greatly improving both cost and reliability.

尚、第1図の7,8は、それぞれ、第1のセラミック基
板の入力端子及び第2のセラミック基板の入力端子であ
る。
Note that 7 and 8 in FIG. 1 are input terminals of the first ceramic substrate and input terminals of the second ceramic substrate, respectively.

第2図a、 bは本考案の第2の実施例であり、第2図
aは分野図、第2図すは組立後の側面図を示す。
Figures 2a and 2b show a second embodiment of the present invention, with Figure 2a showing a field view and Figure 2a showing a side view after assembly.

第2の実施例では2枚の基板の回路構成面がセラミック
酸の枠9を狭んで互いに向き合って組合わされた構造と
なっている。
In the second embodiment, the circuit-forming surfaces of two substrates are assembled so as to face each other with a ceramic acid frame 9 between them.

【図面の簡単な説明】[Brief explanation of the drawing]

第1回aとbは本考案の第1の実施例を示す、正面図と
側面図。 第2図a、!:bは本考案の第2の実施例を示す分解斜
視図と側面図。 1・・・・・・第1の基板、2・・・・・・第2の基板
、3,4・・・・・・蓋、5,6・・・・・・出力端子
、7,8・・・・・・入力端子、9・・・・・・枠。
Part 1 a and b are a front view and a side view showing the first embodiment of the present invention. Figure 2 a,! :b is an exploded perspective view and a side view showing a second embodiment of the present invention. 1... First board, 2... Second board, 3, 4... Lid, 5, 6... Output terminal, 7, 8 ...Input terminal, 9...Frame.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の入力端子と複数の出力端子とを有する混成集積回
路に於て、少な(とも1組の入力端子と出力端子との形
成された基板を各端子の引出面が平行で離間するように
複数枚重ねて構威し、かつ前記各基板の各出力端子が重
ね方向から見て重ならないように一本ごとに交互に同一
方向に引き出されていることを特徴とする混成集積回路
In a hybrid integrated circuit having a plurality of input terminals and a plurality of output terminals, a plurality of substrates (on which at least one set of input terminals and output terminals are formed) are arranged so that the lead-out surfaces of each terminal are parallel and spaced apart. 1. A hybrid integrated circuit characterized in that the circuit boards are stacked one on top of the other, and each output terminal of each board is alternately drawn out in the same direction so that they do not overlap when viewed from the stacking direction.
JP10074379U 1979-07-20 1979-07-20 hybrid integrated circuit Expired JPS6023982Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10074379U JPS6023982Y2 (en) 1979-07-20 1979-07-20 hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10074379U JPS6023982Y2 (en) 1979-07-20 1979-07-20 hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS5619037U JPS5619037U (en) 1981-02-19
JPS6023982Y2 true JPS6023982Y2 (en) 1985-07-17

Family

ID=29333455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10074379U Expired JPS6023982Y2 (en) 1979-07-20 1979-07-20 hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6023982Y2 (en)

Also Published As

Publication number Publication date
JPS5619037U (en) 1981-02-19

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