JPS60239126A - Josephson decoder circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation, to improve the margin and to simplify the circuit by using an OR gate of the 1st branch gate of a flip-flop so as to input an input address signal to the OR gate, inputting a reset signal to the gate of the 2nd branch so as to extract an output signal to a decoder from the 1st branch. CONSTITUTION:The 3-to-8 decoder consists of eight current F/F circuits FF1-8 as shown in Fig. in case of the decoder selecting one output among eight outputs by means of three-address inputs A, B and C. Each current F/F circuit consists of the 1st branch 1 and the 2nd branch 2 and the gate 3 of the 1st branch 1 is an OR gate. When control signals of A'+B'+C'-A+B+C are given to the eight OR gates 3 respectively, only one output is given from the decoder. In case of the reset, a reset input R is added to the gate 4 of the 2nd branch 2 and an output signal of the decoder is extracted from the 1st branch 1. The 3-to-8 decoder is constituted by one stage of F/F in the OR decoder in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to Josephson integrated circuits, and more particularly to current transfer decoders that operate at high speed using OR gates.

2. Description of the Related Art Conventionally, a current transfer type decoder circuit uses an AND gate. Figure 2 shows an example of a conventional current transfer type decoder circuit, which is a three-manpower (a btt) decoder,
This is a so-called AND type 3-to-8 decoder.

The illustrated decoder uses two stages of current transfer type F/F'' II. In principle, this could be done with one stage if gates that take the three-man power A, B, and C0 AND can be used, but the three-man power AND ' This is because the gate that takes E is not practical because it does not have enough margin.To explain Figure 2, the first stage F
/F is the second control signal line (signal R) for reset
λ, the second stage F/F has a first branch (output branch) 24 having a reset gate 29, and the first stage output A.
-B and input C are ANDed together. In this way, three-person AND is not practical because it does not have a margin.
Conventionally, a decoder has been configured in a multi-stage configuration using two-person ANDt. For example, a 4-person decoder has 3 stages of F.
/F is required.

As described above, when the number of stages increases to two or three stages, a drawback arises in that the operating speed becomes slow.

Problems to be Solved by the Invention The present invention attempts to provide a decoder that is capable of processing multiple input address signals with a single stage of current transfer circuit, and has a high speed and a large operating margin.

Means for Solving All Problems In the present invention, the OR gate has a large operating margin, and the AND
This takes advantage of the fact that more gates can be obtained than conventional gates, and one stage of current transfer circuit processes many addresses.

The present invention will be specifically described below with reference to Examples.

Embodiment FIG. 1 shows an embodiment of a 3-to-8 decoder in which one output out of eight outputs is selected by three addresses A, B, and C. In the figure, the decoder has eight currents F/
The F circuit consists of FFI to FF'8.

Each current F/F circuit consists of a first branch 1 and a second branch 2, and the gate 3 of the tenth branch 1 is an OR gate.

Then, each of the eight OR gates 3 has A+B+
A control signal of C-A+B+C is given. As a result, when the three forces of A, B, and C are determined, only one output is output from the decoder.

Resetting is performed by applying reset manual power Re to the gate 4 in the second branch 2. The output signal of the decoder is taken from the first branch 1. In this way, in the OR type decoder of this embodiment, a 3-to-8 decoder can be configured with one stage of F/F. Although the case of three-manpower is shown above, the OR gate can be used sufficiently by up to four-manpower, so a four-manpower decoder can also be constructed. In this embodiment, a shaped junction E y (shaped ju
nctlon) f was used. Shaped junctions are relatively large, with a sine-shaped or hexagonal junction, and the junction itself can be controlled by a magnetic field generated by a current flowing through a control signal line. FIG. 3 shows an example of the threshold characteristic of a forced junction gate, with the vertical axis representing the bias current IB+ and the horizontal axis representing the control current Ic. As shown in the figure, the threshold characteristic has the advantage that even if the cut portion TH is sharp and the IB varies, the threshold value remains almost the same. If another signal line is provided in addition to the control signal line and a DC offset is always applied (IOF in Figure 3), the control signal Sag
It can work extremely fast once it's ready. On the other hand, if a DC offset is not applied, it will take a long time until the control signal becomes sharp, as shown by the broken line in FIG. 3, and the operation will be relatively slow. Such a speed-up means can be further added to the OR gate of the present invention, and the F/F is 1.
Combined with the advantage of being a stage, it is possible to operate at a speed 2 to 3 times faster than the conventional method. In contrast, conventional AND gates have multiple inputs, for example input A and input B.
Since the operation exceeds the threshold when D
If a C offset is applied, a margin cannot be obtained, making it impractical. Therefore, speed-up means that applies a DC offset cannot be applied, and the delay due to the multi-stage configuration is added, so the conventional decoder cannot increase the operating speed.

Although the non-invention has been described in detail above, the present invention is not limited to the above embodiments, and can be modified in various ways, such as 5QUID
It can also be used as a gate.

As described above, according to the present invention, in a decoder using a current transfer circuit, by using an OR gate for the gate, multiple input address signals can be processed in one stage of the current transfer circuit, and the operation is improved. This has the advantage of being able to speed up the process, provide a large margin, and simplify the circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a Josephson decoder circuit according to the present invention, FIG. 2 is a circuit diagram of a conventional Josephson decoder circuit, and FIG. 3 is a diagram of a threshold characteristic of a shaped shield. (Main codes) 1... First branch (output branch), 2... Second branch, 3... OR gate, 4... Gate (for reset)
, F/F 1 to F/F 8... current flip-flop circuit. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Hisashi Tamamushi (1 other person) Figure 1/3 Figure 2 6 Figure 3

Claims (1)

[Claims] In a Josephson decoder using a current transfer type flip-flop, an OR gate is used at the gate of the first branch of the flip-flop, and the input address signal is ORed.
A reset signal is input to the gate of the second branch, and the output signal of the decoder is input to the gate of the second branch.
A Josephson decoder circuit characterized by being extracted from a branch of.