JPS60237545A - Doubling system of computer - Google Patents

Abstract

PURPOSE:To prevent abnormal operation in CPU switching by sending contents of a data and an image I/O memory from a master side to a stand-by side on every arithmetic cycle and making the memories of both CPUs periodical. CONSTITUTION:The CPUs 1a and 1b are provided with program memories 2a and 2b, arithmetic control parts 3a and 3b, data memories 4a and 4b, and image I/O memories 5a and 5b, data transmitters 6a and 6b between the CPUs 1a and 1b are provided with data receiving memories 61a and 61b, and the CPUs 1a and 1b are connected to a process input/output device 8 through a CPU switching device 7. Then, the CPU1a transfers the contents of the device 8 to the memory 5a to perform master-side processing and the result is stored in the memories 4 and 5, then transferred to the CPU1b to perform stand-by side processing; and received data from the CPU1a which are stored in the memory 61b are waited in the memories 4b and 5b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The great invention relates to a duplication system for two computers (CP[J) having image I10 memory cards.

[Prior art]

For example, in a system that uses cprr to control a process, computer failure not only leads to a decrease in process operational efficiency, but is also unacceptable from the perspective of maintaining process safety, and therefore requires high reliability. In the required process system (2), two cprIv
A redundant CPTT system is used in which one CPU is used in case the other one fails.

FIG. 3 is a block diagram showing an example of a conventional cptI duplication system of this type. In the figure, (1a) is the first CPTI unit, (1b) is the FIL 20)
CPU: S-nit, each of these CPU units has a program memory (2), an arithmetic control unit (3)
and a data memory (4). (6a)
, (6b) is a data transmission device connected to each CPr7 unit, (7) is a CP for switching between two CPU units (1 switching device% CB is a process input/output device, (9
) is the Emebus that connects each of these devices.

In the device configured in this way, the first CPU
(1a), mask CPU, second CP[J(1b)
Assuming that the CPU is the standby CPU, the CPU switching device 17) switches the 0P (J(1a) side I
J21 bus (9a)'& is selected, and the process input/output device (8) is connected to the first CPrJ (1a). The arithmetic control unit (3a) of the first CPU (1a) sequentially reads and executes the contents of the program memory (2a),
The results are output to the data memory (4a) and the process input/output device (8). In addition, in order to synchronize the first CPU (1a) and the second CPU (73CPtJ (1b)),
Standby CP from the first CPU (1a) side which is the mask CPrJ via the data transmission device (6a)
At tI, predetermined data in the data memory (4a) 2J'i is transferred to the second CPU t1b) side at 1S.

The processing order is shown in FIG. Mask CP[J (1a
) side executes the main processing and then the standby side CPU (
Data is transferred to the first eye. In addition, the standby side CPU
(1b) executes received data processing and master (CP)
(J) Store the data transmitted from (1a) in a predetermined data memory (4b) area.

In the conventional CPrJPr system with installation configured in this way, the mask side CPU (1a) becomes abnormal and when switching to the standby side CPU, input/output signals are not synchronized, and before switching The main processing result for one cycle is sent to the standby CPU (1b).
There was a problem b1 in that there was a risk that an abnormal operation would occur immediately after the switching because the data was not transmitted to the switch.

[Summary of the invention]

The present invention connects two CPUs each having an image β memory through a data transmission device, and at the end of each CPU operation cycle, the data memory and image J/P on the mask CPU side are connected.
The contents of the memory are sent to the standby CPU side, both memories are synchronized, and the device can be automatically switched to the standby CPU side in the event of an error on the mask CPU side. C that does not cause abnormal operation when switching CPUs
This provides a duplex system for PTI.

[Embodiments of the invention]

FIG. 1 is a block diagram showing an example of a device implementing the method according to the invention. In fig.

(Ia) and (Ib) are computers to be duplicated (CPrJ units), and each of these computers has a program memory (21, arithmetic control unit (3), a data memory (41) and a process input/output signal An image for synchronously performing 5■ n configured including Ushio memory
(6a) and (6b) are data forwarding devices for transferring data between the computers (1a) and (1b), and each of them has data reception memories (61a) and (61b) inside.
This is provided. σ) is a CPU switching device (9) for connecting the mask CPU side and the process input/output device (8);
1 is I/'I! which connects each device. It is an I bus. Note that the suffixes (al and (bl) ft shown in the symbols represent those on the CPU-A 1ll and CPU-B sides that are duplexed.

CPU-A (1a) and eP[J-B (1bl are CPU
It is connected to the process input/output device (8) via the switching device (71), and the same program is stored in the program memory (2) of both CPUs (11).
CPTJ-A (1a) as master CPI1. CPU-B
(1b) Standby CPry tosult.

The CPU switching device (7) is shown in Figure 1), and the CPI
The I/O bus (9a) on the J-A (Ia) side is selected and connected to the process input/output device (81 side 0) IO bus (9). The processing order is shown in Figure 11!2.

The CP (1-A (1a)) executes mask side processing.The processing order is that the input signal of the process input/output device (8) is first transferred to the image memory (51).Then, the image I/pI Main processing ?execution 12 is carried out according to signals from the memory (51) and data memory (4), and the result of the calculation is sent to the data memory (4) and image I/16 memory (51).
is stored in Next, the output signal of the image I10 memory (5) is transferred to the process input/output device (81), and then the contents of the image I/m memory (51) and a predetermined data memory (41 on the mask cpry side are transferred to the data transmission device (61). CPU-B (1
b) executes the standby side processing, and then receives the data reception completion signal from the data transmission device (6b) and transfers the received data from the mask CPU side in the data reception memory (61b) to the standby side CPU (1b). The image is stored in the 2 data memory (51) and the data memory (41) and goes into a standby state again.In this way, input/output processing is performed at the beginning and end of the program cycle via the image x7s memory (5). At the time of CPU switching, the mask side CPrJ is
Process input/output device (81
Since the CPU on the standby side always executes the pro-7 input reading process, it is possible to prevent erroneous calculations when switching CPII.

In the above embodiment, the CPrJPr method has been described, but a multiple backup method is also possible by increasing the number of CrlJs that perform backup. Furthermore, the same effect can be obtained even if the transmission method of the data transmission device is a G-back method.

〔Effect of the invention〕

According to the present invention, the standby side C
P[J is always executed from the process input reading process, and there is no risk of abnormal operation occurring when switching CPUs.
JPr system can be realized.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a device that implements the method according to the great invention, Fig. 2 is a flowchart showing the duplication processing order in the device shown in Fig. 1, and Fig. 3 is an example of a conventional method. The configuration block diagram shown in FIG. 4 is a flowchart showing the duplication processing order in the device shown in FIG. (1)...CP[J unit, (2)...Program memory, (31...CPU, (41...Data memory, (5)...Image I/Jl memory, (6)
...Data transmission device, (61)...Data reception memo IJ, (Power...CPrJ switching device, (81...Process input/output device, (9)...■Shio bus, The same reference numerals in the middle indicate the same or half of each other. Agent Patent Attorney Sanro Kimura 1 Figure 12 Figure 3 Figure tlI4 Figure

Claims (1)

[Scope of Claims] (At least two computers having 11 images and 10 memories <cpU) connected via a data transmission device. At the end of each calculation cycle of the CPU, a stamper (C
Send to Po 9t11 to cycle the memory of both CPUs and automatically standby when there is an error on the mask CPU side.