JPS60236248A - Forming layer for multilayer wirings - Google Patents

Forming layer for multilayer wirings

Info

Publication number
JPS60236248A
JPS60236248A JP59092340A JP9234084A JPS60236248A JP S60236248 A JPS60236248 A JP S60236248A JP 59092340 A JP59092340 A JP 59092340A JP 9234084 A JP9234084 A JP 9234084A JP S60236248 A JPS60236248 A JP S60236248A
Authority
JP
Japan
Prior art keywords
forming
light
resin
multilayer wiring
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59092340A
Other languages
Japanese (ja)
Inventor
Noriko Iwamoto
岩本　則子
Kenichi Takeyama
竹山　健一
Takeshi Ishihara
健 石原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59092340A priority Critical patent/JPS60236248A/en
Publication of JPS60236248A publication Critical patent/JPS60236248A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

PURPOSE:To prevent a contacting hole size from varying due to volumetric contraction upon thermal curing or crack from generating by employing a heat resistant polymer resin for an interlayer insulating film, and using a light effective to cut the bond of the resin to form the hole. CONSTITUTION:A polyamic acid is coated on a semiconductor substrate 1 formed with the first wirings 2, and thermally cured to form a polyimide 3. An excima laser is emitted through a mask 5 to form a contacting hole. The second wirings 6 are formed. Organosiloxane resin or silicone resin is used in addition to polyimide as an interlayer insulating film. A method of emitting light in active gas such as CF4, CCl4, CHF3, CHCl3, O2Cl2, F2 or a method of emitting light in steam is used for resin having a bond readily hydrated such as ester bond or imide bond as a method of accelerating the reaction.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路等の多層配線構造に関する。[Detailed description of the invention] Industrial applications The present invention relates to multilayer wiring structures such as semiconductor integrated circuits.

従来例の構成とその問題点 従来、熱硬化性耐熱高分子のパターン形成は次のような
方法で行なわれてきた。Conventional Structure and Problems Conventionally, patterns of thermosetting heat-resistant polymers have been formed by the following method.

（１）樹脂を塗布し溶媒を除去した後、ノオトレジスト
をマスクとしてウェットエツチングする方法。(1) A method in which a resin is applied, a solvent is removed, and then wet etching is performed using a nootresist as a mask.

（２）樹脂を塗布し、溶媒を除去した後、半硬化させて
フォトレジストをマスクとしＣＦ４１０２プラズマエツ
チング等の方法を用いてドライエツチングする方法。(2) A method in which a resin is applied, the solvent is removed, the resin is semi-cured, and the resin is dry etched using a method such as CF4102 plasma etching using a photoresist as a mask.

（３）樹脂に感光性機能を付与し、溶媒を除いた後、光
を用いて硬化させ現像によってコンタクト孔を形成する
方法。(3) A method in which a photosensitive function is imparted to a resin, the solvent is removed, the resin is cured using light, and a contact hole is formed by development.

（１）〜（３）の方法についてポリイミドを例に挙げ各
々第１図、第２図、第３図を用いて説明する。The methods (1) to (3) will be explained using polyimide as an example and FIG. 1, FIG. 2, and FIG. 3, respectively.

（１）基板１上にポリアミック酸３をスプレー法または
スダンコート法を有いて塗布する。低温熱処理（８０°
Ｃ〜１００°Ｃ）Ｌ溶媒を除く。塗膜上に通常のホトソ
工程を用いて、マスク４を形成する（第１図（ａ））。(1) Polyamic acid 3 is applied onto the substrate 1 using a spray method or a sudan coat method. Low temperature heat treatment (80°
C to 100°C) Remove solvent. A mask 4 is formed on the coating film using a normal photolithography process (FIG. 1(a)).

これを、ポジレジスト剥離液やヒドラジン等のアルカリ
溶液を用いてウェットエツチングしく第１図申））、レ
ジストを除去する（第１図（Ｃ））。This is wet-etched using a positive resist stripping solution or an alkaline solution such as hydrazine (Fig. 1)) to remove the resist (Fig. 1(C)).

り２）樹脂を塗布し、溶媒を除いた後さらに熱処理を行
なって樹脂を半硬化状態にする。この上部にレジストマ
スク４を形成しく第２図（ａ））、ＣＦ４と０２　の混
合ガスを用いて５Ｔｏｒｒ以下の圧力下でプラズマエツ
チングを行なう（第２図（ｂ）　、　（Ｃ）　’）。2) After applying the resin and removing the solvent, heat treatment is performed to bring the resin into a semi-cured state. A resist mask 4 is formed on top of this (FIG. 2(a)), and plasma etching is performed using a mixed gas of CF4 and 02 under a pressure of 5 Torr or less (FIGS. 2(b) and 2(C)').

０）樹脂３を基板１に塗布し溶媒を除いた（第３図（ａ
）　）　、マスク５を介して紫外線を照射しく第３図中
））、現像によりコンタクト孔を形成する（第３図（Ｃ
））。0) Resin 3 was applied to substrate 1 and the solvent was removed (Fig. 3 (a)
) ), irradiate ultraviolet rays through the mask 5 (see Figure 3)) and develop to form contact holes (see Figure 3 (C)).
)).

（１）の方法では、ウェットエツチング特有の横方向へ
のエツチングによりコンタクト孔サイズが大きくなる欠
点がある。また３方法ともコンタクト孔形成後に熱硬化
工程が入るため、体積収縮によるクラックやコンタクト
孔寸法の変化を生じやすくなり、そのため、断線やショ
ートをおこしやすく微細化が困難となる。Method (1) has the disadvantage that the size of the contact hole increases due to the lateral etching characteristic of wet etching. In addition, in all three methods, a thermosetting step is performed after the contact hole is formed, which tends to cause cracks and changes in the contact hole dimensions due to volumetric shrinkage, which makes it easy to cause wire breakage and short circuits, making it difficult to miniaturize.

発明の目的 本発明は耐熱性高分子樹脂の有する優れた平坦化特性、
簡略な製造工程という長所を活かし、上記のような欠点
をなくした層間絶縁膜を形成し、安定したコンタクトを
形成できる多層配線形成方法を捺供する。Purpose of the Invention The present invention provides excellent flattening properties of a heat-resistant polymer resin,
By taking advantage of the simple manufacturing process, the present invention provides a multilayer interconnection forming method that can form an interlayer insulating film that eliminates the above-mentioned drawbacks and form stable contacts.

発明の構成 本発明は層間絶縁膜に耐熱性高分子樹脂を用い、熱処理
によって完全に熱硬化が終了した安定な膜を形成した後
、樹脂の結合を切断し低沸点化合物を生成するに有効な
光を用いてコンタクト孔を形成することを特徴とする・ 実施例の説明 ポリアミック酸は熱によって（１）式に示す工つな、・
　、・　・・・（１） 脱水反応がおこりポリイミドになり、筐だオルガノンロ
キサン樹脂は熱によりラダー構造から網目構造となって
、電気特性、耐熱特性、耐溶媒特性、機械特性にすぐれ
た安定した膜となる。しかし、一方その優れた安定性に
より従来のエツチング方法が困難となる。Structure of the Invention The present invention uses a heat-resistant polymer resin for the interlayer insulating film, and after forming a stable film that has been completely thermally cured by heat treatment, the resin is bonded to break and the resin is effectively cured to produce a low-boiling point compound. Polyamic acid is characterized by forming contact holes using light.・Explanation of Examples Polyamic acid is formed by the process shown in formula (1) by heat.・
,...(1) A dehydration reaction occurs to form polyimide, and the organone loxane resin changes from a ladder structure to a network structure due to heat, resulting in a stable structure with excellent electrical, heat-resistant, solvent-resistant, and mechanical properties. It becomes a thin film. However, its excellent stability makes conventional etching methods difficult.

本発明は熱硬化により安定構造となった耐熱性高分子樹
脂を微細加工するため、耐熱性高分子樹脂結合を切断す
るに有効な光エネルギーを利用した。The present invention utilizes light energy that is effective for cutting the bonds of the heat-resistant polymer resin in order to microfabricate the heat-resistant polymer resin that has become a stable structure through thermosetting.

使用する光の活用方法としては■光化学反応（転位反応
、ラジカル反応等）を起こさせる方法Ｃ■光を熱に変換
し部分加熱によυ熱分解させる方法。The methods of utilizing the light used are: ■ A method of causing a photochemical reaction (rearrangement reaction, radical reaction, etc.) C. A method of converting light into heat and causing υ thermal decomposition by partial heating.

０分子の共鳴吸収エネルギーを与え電子を励起させて結
合を切断する方法がある。There is a method of applying resonance absorption energy to zero molecules to excite electrons and break bonds.

捷だ、分解反応を促進する条件下で光を照射すれば、さ
らに工程の効率化に役立つ。反応を促進する方法として
は具体的に次のような方法が挙げらｉ１ル。■ＣＦ４．
ＣＣｆ１４．ＣＨＦ３．ＣＨ（４３，０２ＣＲ２゜Ｆ２
などの活性なガス中で光を照射することにより、光エネ
ルギーだけでなく、光によって分解した活性ガスの粒子
の衝突も利用して樹脂の結合を切断する方法。■エステ
ル結合、イミド結合、など加水分解されやすい結合を有
する樹脂には、水蒸気中で光を照射することにまゆ、光
分解反応だけでなく加水分解反応を利用して結合を切断
する方法。■基板を加熱し、分子の運動を活発にして光
エネルギーによる結合の切断を容易ならしめる方法。■
減圧にして分解反応生成物である低沸点化合物を反応系
外へ取り除きやすくし、つねに新しい界面が光にさらさ
れるようにする方法。However, irradiating light under conditions that promote the decomposition reaction can further improve the efficiency of the process. Specific methods for promoting the reaction include the following. ■CF4.
CCf14. CHF3. CH(43,02CR2°F2
A method of cutting resin bonds by irradiating light in an active gas such as, using not only the light energy but also the collision of active gas particles decomposed by the light. ■For resins that have bonds that are easily hydrolyzed, such as ester bonds and imide bonds, this method uses not only photolysis reactions but also hydrolysis reactions to cleave the bonds by irradiating light in steam. ■A method in which the substrate is heated to activate the movement of molecules, making it easier to break bonds using light energy. ■
A method in which low-boiling compounds, which are decomposition reaction products, are easily removed from the reaction system by reducing the pressure, and new interfaces are always exposed to light.

次に１本発明の詳細な説明する。Next, one aspect of the present invention will be explained in detail.

第１配線２を形成した半導体基板１上にポリアミック酸
（ＰＩＱ、日立化成）を塗布し熱処理（１００°ＣＸ１
ｈ−１−２０σＣＸ１ｈ＋３５０℃Ｘ　１　ｈ　ｌｎ　
Ｎ２　）　により硬化させてポリイミド３とする。この
ポリイミドに所定のマスク５を介してエキシマレーザ−
を照射しコンタクト孔を形成する。このときのエツチン
グ速度は、１１００人／ｍｉｎ　であった。この上部に
蒸着により八２　を形成し、通常のホトン工程を用いて
レジストマスクをした後、ＣＣ２４を用いてエツチング
し、第２配線６を形成する。Polyamic acid (PIQ, Hitachi Chemical) is coated on the semiconductor substrate 1 on which the first wiring 2 is formed and heat treated (100°C
h-1-20σCX1h+350℃X 1 h ln
Polyimide 3 is obtained by curing with N2). An excimer laser is applied to this polyimide through a predetermined mask 5.
is irradiated to form a contact hole. The etching speed at this time was 1100 people/min. A layer 82 is formed on this upper portion by vapor deposition, a resist mask is applied using a normal photon process, and a second wiring 6 is formed by etching using CC24.

同様の樹脂を用いて、水蒸気中で行なうとエツチング速
度は、２４６０人／ｒｕｉｎ　となり、ＣＦ４中で行な
うと３０１０人／ｍｉｎ　となった。Using the same resin, the etching rate was 2460 etching/run in steam and 3010 etching/min in CF4.

発明の効果 本発明により、層間絶縁膜に熱硬化性耐熱高分子材料を
用いた多層配線における従来の問題点であった、コンタ
クト孔形成後の熱硬化に伴う体積収縮によって生じるコ
ンタクト孔寸法の変化やクラックの発生を防止し、高分
子材料の平坦化特性や工程の簡略さを活かした歩留りの
高い、微細加工の容易な多層配線を形成することができ
る。また、コンタクト孔形成工程を前述した条件下で行
なうことにより作業の効率を向上させることができる。Effects of the Invention The present invention eliminates the change in contact hole dimensions caused by volume shrinkage due to thermosetting after contact hole formation, which was a conventional problem in multilayer wiring using thermosetting heat-resistant polymer materials for interlayer insulating films. It is possible to form a multilayer interconnection that is easy to microfabricate and has a high yield while preventing the occurrence of cracks and cracks and taking advantage of the flattening properties of the polymer material and the simplicity of the process. Further, by performing the contact hole forming step under the above-described conditions, the efficiency of the work can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ｉａ）　−ｆｃ）　、第２図ｔａ）　−ｆｃ）、
第３図（ａ）　−ｆｃ）Ｖｉ従来のコンタクト孔形成工
程断面図、第４図（−）〜（Ｃ１は本発明の一実施例の
多層配線形成工程断面図である。 １・・・・・基板、２・・・・・第１配線、３・・・・
層間絶縁膜、６・・・マスク、６・・・・第２配線。 代理人の氏名　弁理士　中　尾　敏　男　ほか１名第　
１　図 （（］ 第２図 第３図 １ｂ）　／ 第４図 二］ヨヨ代 □□−−／ （ａ） ＮＪＪＪ −と ｙ’　２ 一二亮６ □−（ ｔｃ） ９〇八 Ｗ″ ！ ／ 」 ！ Ｌ″Figure 1 ia) -fc), Figure 2 ta) -fc),
FIG. 3(a)-fc)Vi is a sectional view of a conventional contact hole forming process, and FIGS. 4(-) to (C1 are sectional views of a multilayer wiring forming process of an embodiment of the present invention. 1...・Substrate, 2...First wiring, 3...
Interlayer insulating film, 6... mask, 6... second wiring. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure ((] Figure 2 Figure 3 1b) / Figure 4 2] Yoyodai □□--/ (a) NJJJ - and y' 2 Ryo 12 6 □-(tc) 908W''! ／ ”! L″

Claims (1)

【特許請求の範囲】 （１）多層配線構造を形成するに際し、配線間を分離す
る層間絶縁膜に熱硬化性耐熱高分子材料を用い、前期樹
脂を基板上に塗布する工程、前記樹脂を加熱硬化させる
工程、硬化後の耐熱高分子材料の結合を切断し低沸点化
合物を生成するに有効な波長を有する光を用いて前期層
間絶縁膜に：ｊノンタクト孔形成する工程を有すること
を特徴とする多層配線形成方法。 ？）層間絶縁膜にポリイミドを用いることを特徴とする
特許請求の範囲第１項記載の多層配線形成方法。 （３ン　層ｒ！１ｊＪｅ縁膜にオルガノシロキサン樹脂
またはシリコン樹脂を用いることを特徴とする特許請求
の範囲第１項記載の多層配線形成方法。 （４）所定のマスクを介して光を照射することを特徴と
する特許請求の範囲第１項記載の多層配線形成方法。 （６）光を掃引照射することを特徴とする特許請求の範
囲第１項記載の多層配線形成方法。 向　複数の異なる波長の光を用いたことを特徴とする特
許請求の範囲第１項記載の多層配線形成方法。 （′７）多層配線構造を形成するに際し、層間絶縁膜と
なる熱硬化性耐熱高分子材料を基板に塗布する工程、前
記塗布膜を加熱し硬化させ、る工程、前記樹脂の結合を
切断し低沸点化合物を生成させるに有効な光を分解反応
が促進される条件下で照射し、コンタクト孔を形成する
工程を有することを特徴とする多層配線形成方法。 ＠）活性ガス中で光を照射することを特徴とする特許請
求の範囲第７負記載の多層配線形成方法。 枠）水蒸気雰囲気中で、光を照射することを特徴とする
特許請求の範囲第７項記載の多層配線形成方法。 ０ （勃）基板を加熱しながら光を照射することを特徴とす
る特許請求の範囲第７項記載の多層配線形成方法。 （１１）減圧下で光を照射することを特徴とする特許請
求の範囲第７項記載の多層配線形成方法。[Claims] (1) When forming a multilayer wiring structure, a thermosetting heat-resistant polymer material is used as an interlayer insulating film that separates wiring, and a step of applying a resin on a substrate, heating the resin. A curing step, and a step of forming non-tact holes in the interlayer insulating film using light having a wavelength effective for cutting bonds in the heat-resistant polymeric material after curing and generating a low boiling point compound. Multilayer wiring formation method. ? 2.) The multilayer wiring forming method according to claim 1, wherein polyimide is used for the interlayer insulating film. (3) The multilayer wiring forming method according to claim 1, characterized in that an organosiloxane resin or a silicone resin is used for the layer r!1jJe edge film. (4) Irradiating light through a predetermined mask. A method for forming a multilayer wiring according to claim 1, characterized in that: (6) A method for forming a multilayer wiring according to claim 1, characterized in that the light is irradiated in a sweeping manner. A method for forming a multilayer wiring according to claim 1, characterized in that light having a wavelength of A step of coating the substrate, a step of heating and curing the coating film, and a step of irradiating the contact hole with light effective to break the bonds of the resin and generate a low boiling point compound under conditions that promote the decomposition reaction. A method for forming a multilayer interconnection, comprising the step of forming a multilayer interconnection.@) A method for forming a multilayer interconnection according to the negative aspect of claim 7, characterized by irradiating light in an active gas. Frame) The multilayer wiring forming method according to claim 7, characterized in that light is irradiated in a water vapor atmosphere. 0. The multilayer wiring forming method according to claim 7, characterized in that the substrate is irradiated with light while being heated. (11) The multilayer wiring forming method according to claim 7, characterized in that the light is irradiated under reduced pressure.
JP59092340A 1984-05-09 1984-05-09 Forming layer for multilayer wirings Pending JPS60236248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59092340A JPS60236248A (en) 1984-05-09 1984-05-09 Forming layer for multilayer wirings

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59092340A JPS60236248A (en) 1984-05-09 1984-05-09 Forming layer for multilayer wirings

Publications (1)

Publication Number Publication Date
JPS60236248A true JPS60236248A (en) 1985-11-25

Family

ID=14051662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59092340A Pending JPS60236248A (en) 1984-05-09 1984-05-09 Forming layer for multilayer wirings

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Country Link
JP (1) JPS60236248A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0222618A2 (en) * 1985-11-12 1987-05-20 Engelhard Corporation Multilayer hybrid integrated circuit and process for producing
US4855252A (en) * 1988-08-22 1989-08-08 International Business Machines Corporation Process for making self-aligned contacts
JPH02102071A (en) * 1988-10-11 1990-04-13 Olympus Optical Co Ltd Manufacture of ion flow recording head

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5969931A (en) * 1982-10-07 1984-04-20 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of etching polyimide with far ultraviolet rays

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5969931A (en) * 1982-10-07 1984-04-20 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Method of etching polyimide with far ultraviolet rays

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0222618A2 (en) * 1985-11-12 1987-05-20 Engelhard Corporation Multilayer hybrid integrated circuit and process for producing
US4855252A (en) * 1988-08-22 1989-08-08 International Business Machines Corporation Process for making self-aligned contacts
JPH02102071A (en) * 1988-10-11 1990-04-13 Olympus Optical Co Ltd Manufacture of ion flow recording head

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