JPS60236197A - Barrel shifter - Google Patents

Abstract

PURPOSE:To speed up a propagation speed between data input and output by inserting invertors to an intermediate stage of each stage of a unit shifter, etc. CONSTITUTION:Invertors 31 and 32 are inserted between shifters 2 and 3 at intermediate stages of unit shifters 1-4 and an output stage of a final stage shifter 4. Even if a bit ''1'' of input data is inverted into ''0'', and vice versa, and a propagation speed of a transfer gate of a selector is different due to bits ''0'' and ''1'', a maximum propagation period from an input to an output can be shortened by the inverter 31, and a propagation speed between data input and output can be speed up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a barrel shifter used in a numerical arithmetic processor, etc., and particularly relates to a single channel type MOS (insulated f-
} type) relates to a barrel shifter that uses a transfer dart as a selector.

[Technical background of the invention]

In general, a barrel shifter is used to shift bits of data input by a desired number of digits at a time as needed.
A barrel shifter that can be shifted with bit 1 is shown in FIG. That is, 1 is an 8-bit shifter to which data input of a predetermined number of bits is guided in parallel, 2 is a 4-bit shifter to which the parallel output of the 8-bit shifter 1 is guided, 3 is a 2-bit shifter to which the parallel output of the 4-bit shifter 2 is guided, and 4 is a 2-bit shifter to which the parallel output of the 4-bit shifter 2 is guided. This is a 1-bit shifter to which the parallel outputs of the 2-bit shifter 3 are guided.

The circuit configuration of each of the shifters 1 to 4 is based on a selector group that is controlled according to the shift control input. It is wired to output with or without shifting.

If, for example, an N-channel type MO8) transfer gate is used as a selector for selecting whether or not to perform bit shifting in each of the shifters 1 to 4, each selector is constructed as shown in FIG. That is, 21 is the non-shift side dart to which input bit B is led to one end, 22
is an input bit having a different weight of a predetermined digit (n) from the input bit BI, for example, Bi+n (in this example, n is 8°4.
2.1) a shift-side dart guided at one end;
φ is a shift signal guided to the dart electrode of the shift side gate 22; φ is an inverted shift signal guided to the dart electrode of the non-shift side gate 21;
The other ends of 2 are connected in common and serve as selector output ends.

Therefore, when the shift control signal input φ is at the "0" level (V) and φ is at the @1" level (+5V), the non-shift side gate 21 opens and the shift side gate 22 closes, so the input bit B1 is selected and appears at the output terminal 23.Contrary to the above, when φ is "1" and φ is 0#, the shift side dart 22 is opened and the non-shift side gate 21 is closed, so that the input signal Bl+. is selected and output end 2
Appears in 3.

[Problems with background technology]

The conventional barrel shifter as described above operates so that each bit signal of the data input is propagated through the selectors of each of the plurality of shift circuits while maintaining the same phase (logical level). Therefore, when an N-channel transfer dart is used as a selector, the propagation speed of the 11" bit of +5V of the data input is slower than that of the 10" bit of 0V due to its threshold characteristic.

Here, to simplify the explanation, if the "1# level propagation time in each selector is tl, the maximum propagation time to pass through four stages of selectors is 4t.Similarly, as a selector P If a channel transfer gate is used, its threshold characteristics will reduce the
The propagation time for a ``bit'' is slower than that for a 1 bit.To simplify the explanation, if we let the ``0# level'' propagation time at each selector be to, then the maximum time required to pass through four selectors is The propagation time is 4t.

However, when it is required that data input "1" and "0" bits be output at the same time, or when a high speed propagation speed between input and output is required, the conventional barrel shifter is used as is. Since this is not possible, countermeasures are strongly requested.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and it is possible to increase the propagation speed between data input and output, and it is possible to simultaneously output the ``1'' and ``0# bits of input data as necessary. This provides a high-performance barrel system that is possible.

[Summary of the invention]

That is, the present invention provides a Murrell shifter in which either an N-channel type or a P-channel type MOS transfer gate is used as a selector for each of a plurality of unit stages. It is characterized in that an inverter is inserted in at least one location.

Therefore, the "Ill#, IIQ" bits of the input data are not propagated in the "Q#, 111#" level phase in the middle stage, and the maximum propagation time between input and output is shortened.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The barrel shifter shown in FIG. 3 is different from the conventional barrel shifter described above with reference to FIG. and the 2-bit unit shifter 3), and an inverter 32 for each bit is also inserted on the output side of the final stage unit shifter 4. Since the connection points are different and the other parts are the same, the same reference numerals 6- as in FIG. 1 are given and the explanation thereof will be omitted.

If an N-channel transfer gate is used as a selector for each shifter 1 to 4, and its "1" level output is, for example, +3 V, and its "O" level output is 0 (in other words, the selector output is +3 V to OV), the inverters 31... and 32...
- Set the input threshold voltage to approximately the median value (+1.
5V). Contrary to the above, if a P-channel transfer gate is used as a selector, and its "1" level output is +5V and its "O' level output is, for example, +2V (that is, the selector output is +
When changing between 5V and +2V), inverter 3
It is assumed that the input threshold voltages of 1... and 32... are set to approximately the median value (+3.5 V) of #1 of the above change range.

In the barrel shifter with the above configuration, the 1" bit of the input data passes through the two stages of selectors 1 and 2 at the "1" level, and then is inverted by the inverter 31 and becomes "0".
level, and then set the remaining 2-stage selector 3.4 to 0.
After passing through the level, it is inverted again by the inverter 32 and output back to the original level of 1 level. Similarly,
The “O” bit of the input data is sent to the 2-stage selector 1.
, 2 at the "0# level", the inverter 31
It is inverted at the inverter 32 and becomes the 11# level, and then passes through the remaining two-stage selectors 3 and 4 at the ``IH level'', and is then inverted again by the inverter 32, returning to the original ``0# level and outputting it. .

Therefore, the ``1#'' bit of the input data.

For the 0'' bit, the number of dart propagation stages at the M11+ level between the input and output is the same, and the number of dart propagation stages at the ``0#'' level is the same, so the ``1'' bit and the 'O'' bit are will now be output.

In addition, the propagation time between the input and output of each bit is two stages of the dart propagation time t1 in which propagation at the "1" level is carried out, and
The propagation time to of the dart that propagates at the 0” level
The sum of two stages of and the inverter propagation time t is,
t<2 tx +2 t.

Therefore, it can be regarded as 2tl+2t6.

This value is 4t for propagation time at 10# level when using an N-channel gate as a selector, or 4t for propagation time at "1" level when using a P-channel dart as a selector.
This is longer than the propagation time 4tl, but it is also smaller than the maximum propagation time in the conventional example. That is, compared to the maximum propagation time of 4t in the conventional example using an N-channel gate as a selector, the propagation time in the above embodiment is 4t1 (2tx +2to)=2 (tt to)
(However, it is smaller by tt>to). Furthermore, the propagation time in the above embodiment is 4t+ - (2tt + 2to) = 2 (to tt ) compared to the maximum propagation time of 4t when a P-channel gate is used as a selector in the conventional example.
(However, only to > tx).

In addition, since the input threshold of the inverters 31 and 32 is set to approximately the 9-center value of the selector output level change range, the operating speed for the '1' and '0' levels of the selector output is They are almost equal.

In the above embodiment, an inverter is inserted between the central stages among the unit thick stages, but even if an inverter is inserted between stages other than the central stages, the maximum propagation time can be shortened. Furthermore, when the number of unit shifter stages is large, the inverter may be inserted not only between one stage but also between a plurality of stages. In this case, the number of stages propagating in the ``1'' level phase and ``
If the inter-insertion stages are determined so that the number of stages for ``0#0# level propagation is equal,''
Simultaneous output of 1'' and 02 bits becomes possible.

Further, the final stage inverter 32 may be omitted depending on the case, and another circuit may be inserted between the final stage unit shifter and the final stage inverter.

〔Effect of the invention〕

As described above, according to the barrel shifter of the present invention, by inserting an inverter between unit shifter stages, the data input/output propagation speed can be increased. 1″,’0″
Bits can be output simultaneously, and performance can be improved compared to conventional level shifters.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an example of a conventional barrel shifter,
FIG. 2 is a circuit diagram showing an example of a selector used in each unit shifter of the barrel shifter, and FIG. 3 is a configuration explanatory diagram showing one embodiment of the barrel shifter according to the present invention. 1 to 4...Unit shifter, 21.22...N channel MO8) run shifter, 31.32...Inverter. Applicant's agent Patent attorney Takehiko Suzue 11-? 21 Figure 2 田◆nBi

Claims (3)

[Claims] (1) In a barrel shifter that uses either an N-channel type or P-channel type MOS transfer dart as a selector in each of multiple stages of unit shifters, an inverter is inserted between at least one unit shifter stage. Barrel shifter featuring. (2) The inverter is characterized in that the number of stages of unit thicks that propagate in a phase with an input level of "1" is the same as the number of stages of unit shifters that propagate in a phase with an input level of 0". patent for (3) The barrel shifter according to claim 1, further comprising an inverter on the output side of the final stage of the unit shifter.