JPS60235550A - Information transmission system - Google Patents

Abstract

PURPOSE:To eliminate the need for a circuit assuring the transmittability and to attain parallel transmission through lots of lines by providing a control signal line for synchronization in addition to an information transmission line. CONSTITUTION:A transmission line 130 is twisted pair multi-core cable and 11 kinds of communication lines are formed by 11 pairs of conductors. A line RM in the transmission line 4 is called a record mark and a signal line representing a section of a transmission frame in the transmission system. A line CLK is a clock line to synchronize a transmission timing and reception timing of the information. D7-D0 are information lines forming one byte information by 8 lines, the D7 is the MSB (most significant bit) and the D0 is the LSB (least significant bit). The transmission data stored in a buffer memory 104 is transmitted to a transmission register 107 and a signal is outputted to the information lines D0- D7 and a parity line Parity of the transmission line from a transmission driver 113 in synchronizing with the rise of the clock of the line CLK.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an information transmission system, and in particular, an information transmission method in which a control line is provided for control separately from an information transmission line, and the transmitted information is synchronized by the control line. It is related to the method.

[Prior Art] In recent years, with the promotion of office automation, intelligent copying machines, facsimile machines, word processors, personal computers, and the like have spread rapidly and widely. Recently, the use of terminals for these devices has not been limited to just standalone use, but has also expanded into corporate information communication networks, so-called LA.
There has been a movement to network these using N (Local Area Network) and to realize a unique and efficient information processing system.

The configuration of a LAN is generally shown in Figure 1, in which a communication control unit called a node is connected to a transmission line that transmits information.
Various terminals A and B are installed at that node.

C and D are connected.

In FIG. 2, which shows the configuration of the Mate section in block form, a microprocessor (MPU) lOO manages transmission data sent to the transmission line through the transmission line interface 107, data received from the transmission line, and management of data received from the transmission line through the adapter interface 103. It manages information exchange with terminals. Direct memory access controller (D
MAC) 102 speeds up transmission and reception, MPU1
00 directly to the buffer memory 104 and the transmitting circuit 1
05 or the receiving circuit 10B. The buffer memory 104 is a shared memory between the node section and the terminal section, and has the role of temporarily storing transmitted and received data.

In the conventional LAN transmission mode, a single communication path, typified by a coaxial cable, is used, and an information signal modulated by a timing clock is serially transmitted (bit serial) through the communication path. As a transmission format in this case, for example, there is an HDLC (high level data link control) method that allows arbitrary bit pattern information to be transmitted by an arbitrary number of bits.

FIG. 3 is a schematic diagram of a frame, which is an HDLC transmission unit. A bit string called a flag for frame synchronization °“
01111110°° are placed at the beginning and end of the frame, and the receiving side recognizes the start and end of the frame by these flags. Note that FCS in the figure is called a frame check sequence and is a 16-bit bit string for error detection.

This scheme has the disadvantage of requiring circuitry for frame information transparency. In other words, if there is a bit string that is the same as the flag in the information, in order to prevent it from being mistakenly recognized as the end of the frame, the bit string must contain five consecutive bits.
”, the sending side always sets bit °”0 immediately after it.
It is necessary to have a circuit that inserts l bits of ``, and conversely deletes 0゛° immediately after five consecutive pids 1°' on the receiving side.This circuit is not suitable for original information transmission. Although this is an unnecessary circuit, it is an essential circuit in the HDLC system.

[Objective] The present invention recognizes the start and end of an information frame by another means, eliminates the need for the above-mentioned complicated circuit for ensuring transparency, and enables high-speed transmission using a parallel transmission method. It is.

Embodiments] Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 4, the transmission line 130 is a twisted pair multi-wire cable, and 11 types of communication paths are formed by 11 pairs of conducting wires. The line RM in the transmission line 4 is called a record mark, and is a signal path indicating the division of transmission frames in this transmission system.

Line CLK is a clock line for synchronizing information transmission timing and reception timing. D7 to Do are information lines that form 1 byte information with 8 communication paths, and D
7 is the MSB (most significant bit) and Do or LSB (least significant bit).

Parity is an error check line for 1-byte information represented by D7 to DO, and represents a vertical parity value.

FIG. 5 shows waveforms on each communication path when 8 bytes of information are transmitted. Data value t*l Expressed in hexadecimal notation, the first transmitted data number is 1111I & AA”,
"6E"", "EO", "9C", "65 II,
This is the case of l "4A", "30゛", and "93pa". Par
In this case, the even parity of each data is placed on the ity line.

FIG. 6 is a block diagram for explaining the transmission/reception operation of the node unit, and FIG. 7 is a flowchart showing the control operation of the MPU 100 during transmission. Figure 5, Figure 6 below,
The operation at the time of transmission will be explained according to FIG.

The output of the transmission driver 113 of the transmission circuit 105 becomes high impedance when not transmitting, and is connected to the RM line and the CLK
The signal line also has a low impedance. Now, in response to a transmission request from the terminal, the MPU 100 sends a signal to the signal line 122, and the RM.

Controls the CLK transmitting/receiving circuit 112 and connects the line RM before starting transmission.
, CLK are both set to "°L" level, and all transmission drivers are enabled. The transmission line 130 is now ready for transmission.

At the same time as the DMACI O2 is activated by the MPU IOO, the line RM becomes "H" level by the RM and CLK transmitting/receiving circuit 112, indicating to other nodes that the subsequent signals on the communication path will be valid, and the DMACI O2 It learns this state via the signal line 124 and starts transmission. The line RM is fixed at the "H" level until the end of transmission.

(Step 201).

The transmission data stored in the buffer memory 104 is sent to the transmission register 107, and the transmission driver 113 outputs a signal to each of the information lines DO to D7 and the parity line Parity of the transmission line in synchronization with the rising edge of the clock on the line CLK. (step 202).

Eight bits of one data and a parity pit are transmitted in one clock, and the above operation is repeated until the transmission of a predetermined number of data is completed.

When the transmission of a predetermined number of data is completed, the MPU sends a signal to the control signal line 122, and the RM and CLK transmitting/receiving circuit 112
CLK transmission is stopped, and then the RM line is set to the "L°" level to notify the receiving side of the end of transmission, indicating that all subsequent signals on the communication line will be invalid (step 204).Finally, each The output of the transmission driver 113 on the communication path is set to high impedance, and the outputs of the RM line and CLK line are also set to high impedance to complete the transmission operation.

Next, the reception operation will be explained with reference to FIG.

During reception, the RM, CLK receiving circuit 112 constantly connects the line RM.
It is monitored that the voltage remains at the "L" level for a certain period of time (step 205). When the “L” level of the line RM is detected, the “H” level of the line RM indicating that each path signal is valid is detected.
” Wait for a level signal to be detected (step 206
). When the line RM reaches the "°H" level, the receiving circuit is initialized (step 207) and waits for a change in the line CLK.

Since the transmitting side outputs the transmitted data in synchronization with the rising edge of the clock, the receiving side outputs the transmitted data in synchronization with the falling edge of the clock.
The data on the information lines D7 to Do of the transmission line H and the parity line are taken into the receiving FIFO IO 8 through the receiver 114 (step 208).

When data is stored in the receiving PIFO 108, the DMA
, start ClO2 and receive PIF0108 by DMA.
data is read out and stored in the next buffer memory 104.
will be written into. Such reception operation is performed by RM12
This continues until 0 becomes the low level and each subsequent channel signal is declared invalid (step 209).

[Effects] As explained above, according to the present invention, by providing a control signal line for synchronization separately from the information transmission line, a circuit for ensuring transparency is not required, and parallel Since data transmission is possible, high-speed data transmission is easily possible.

[Brief explanation of the drawings] Figure 1 is a LAN connection configuration diagram, Figure 2 is a block diagram of the mate section, Figure 3 is a serial transmission diagram using the HDLC method, and Figure 4 is a transmission diagram using multi-wire byte parallel transmission. , FIG. 5 is a transmitting and receiving function block diagram, FIG. 6 is a timing diagram of multi-wire byte parallel transmission, FIG. 7 is a flowchart during transmission in an embodiment of the present invention, and FIG. 8 is a reception diagram in an embodiment of the present invention. It is a flowchart of the time. Here, RM...record mark, CLK...clock, 100...MPU, 102...DMAC, 1
12...RM, CLK transmission/reception circuit, 130... Transmission line. Patent applicant: Canon Co., Ltd. Figure 6 +24 Figure 7 Figure 8

Claims (1)

[Claims] A transmission method using multi-wire transmission lines, characterized in that a control line for level signals defining the start and end of an information frame is provided separately from the information transmission line, and the transmitted information is synchronized by the control line. Information transmission method.