JPS6023552B2 - Image signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an image signal for displaying an image on a television or the like by processing a signal reproduced from a recording medium such as a cassette tape, a reel-to-reel tape, or a record. It relates to a processing device.

As this type of device, the following configuration has been proposed.

FIG. 1 shows a system diagram illustrating how the image signal processing device is used, and FIG. 2 shows a block diagram illustrating the configuration of an example of the image signal processing device. In FIG. 1, a signal reproduced from a cassette tape recorder, reel-to-reel tape recorder, record player, etc. includes an image signal and an audio signal, and the former is processed into a television signal by an image signal processing device, and then the signal is transmitted to the television. The latter is displayed in color, and the latter is amplified by an audio amplifier and made into audio by a speaker.

Note that the image signal can be made to correspond to the left channel, and the audio signal can be made to correspond to the right channel, for example. Here, it is assumed that the cassette tape, record, etc. is recorded in advance to include command data and display data as described below.
The image signal includes such command data and display data, and the image signal processing device identifies these data and stores them in the storage device as appropriate, and also reads out the contents of the storage device in a predetermined manner and processes them into a display signal, for example, a video signal. It is configured as follows so that it can be transmitted and displayed on a display device such as a television. The signal reproduced from the recording medium 1 includes:
An image signal is included, and this image signal includes command data and display data as described later. Demodulator 2
demodulates the image signal into a digital signal and removes the influence of the reproduction level of the image signal. A microcomputer (hereinafter referred to as CPU) 3 to which a digital signal is input,
The content of the digital signal is identified, and addresses are designated to the display RAM 4 and color RAM 5, which will be described later, according to the content, and the content necessary for display is output to be written. The address multiplexer 6 includes a display RAM 4,
Only when the address of color RAM 5 is specified, address bus A of display RAM 4 and color RAM 5 is set to CP.
Switch to the state where it is connected to the address bus 8 of U3. In addition, at this time, display RAM 4 and color RAM 5 are CPU
The display data from the data bus of the CPU 3 is controlled so that the address is specified by the address bus B of the CPU 3, and among the display data that is necessary for display by the CPU 3, the pattern data is stored in the display RAM 4.
Also, color data is written into the color RAM 5. Normally, when no address is specified by the CPU 3, the address multiplexer 6 connects the address bus C from the synchronization signal generation circuit 7, which will be described later, to the address bus A.
4. Specify the address of the color RAM 5.

At this time, the display RAM 4 and color RAM 5 output pattern data and color data according to the designated addresses. The display RAM 4 is a memory into which input data (pattern data) can be written or read according to a designated address, and is allocated as follows.

For example, as shown in Figure 3, a television screen is divided into 192 blocks, each vertically divided into 1 pallet and 1 cell, and each block is divided into 192 blocks, each of which is divided into 192 blocks.
It is divided into equal parts to form pixels. One bit of the display RAM 4 is allocated to this pixel.

For example, addresses (corresponding to the numbers in FIG. 3) correspond to every eight pixels arranged in the horizontal direction in each block, and eight bits of the display RAM 4 are assigned to each address. Therefore,
By specifying an address and storing 8 bits of "0" or "1" information, 1 bit corresponds to 1 pixel, and by setting each bit of the display RAM to "1" or "0", A corresponding pattern can be displayed on the television screen. The color RAM 5 writes input data (pattern data) according to the specified address,
or readable memory, allocated as follows:

For example, as shown in Figure 4, a television screen is divided vertically into 1 equal section and 12 equal parts, for a total of 192 blocks, and each block is assigned an address (the number in Figure 4). ) can be specified.

8 bits of the color RAM are allocated to this address, and these 8 bits contain color information for the back that specifies the color of the back of the block, and color information for the pattern that specifies the color of the pattern to which the block belongs. Contents. For example, when color information is expressed in 3 bits, the 8 bits are as follows: the 1st bit is an empty bit, the 2nd to 4th bits are color information for back, the 5th bit is an empty bit,
The 6th to 8th bits are assigned as color information for the pattern.

Note that the color information can be made to correspond, for example, as shown in the following table.

Table 1 Here, if it is desired to specify 8 or more colors, it goes without saying that 4 bits can be allocated to color information.

The synchronization signal generation circuit 7 generates a horizontal synchronization signal and a vertical synchronization signal, and also generates a signal specifying the address of the display RAM and color RAM corresponding to the scanning position.

The parallel-to-serial converter 8 reads the pattern data read out from the display RAM 4 whose address is specified in 8-bit parallel, and serially converts this data bit by bit in response to the signal from the synchronization signal generation circuit 7. It is output and sent to the color multiplexer 9.

The color multiplexer 9 responds to the data from the parallel-to-serial converter 8, and when it is "1", it outputs the data.
The data bus D is connected to the data bus F, and conversely, when it is "0", the data bus 8 is connected to the data bus F'.

Here, the color RAM 5 outputs pattern color information data to the data bus D and back color information data to the data bus E according to the address specification.

In this way, the data bus F of the color multiplexer 9 is
When the output of the parallel-serial converter 8 is "1", pattern color information is output from the data bus D, and when it is "0", a back synchronization signal is output from the data bus E. The color control circuit 10 receives color information from the data bus F.
Color signals corresponding to the colors specified in Table 1 are generated and sent to the mixer 11.

The mixer 11 generates a video signal by combining the color signal from the color control circuit 10 with the horizontal synchronization signal, vertical synchronization signal, etc. from the synchronization signal generation circuit 7.

The RF modulator 12 modulates the VHF wave with the video signal to obtain an RF signal.

By inputting this RF signal from the antenna terminal of a home television, it can be received on one or two channels of the television band. Note that if the video signal is input to a monitor television, it will be displayed on the television screen. As described above, the image signal processing device writes signals from the recording medium to the display RAM and the color RAM,
Or by reading it out, the content can be read from a color TV.
will be displayed.

The image signal processing device described above realizes various operations based on instruction data reproduced from a recording medium, and a specific example thereof will be explained.

Here, the command data is shown in Table 2 below, for example.

Table 2 According to this Table 2, the signal arrangement on the recording medium is made.

Here, in the case of specifying one color for the entire screen (setting the entire television screen to the same specified color), data 21 corresponding to any desired color in Table 2A, for example, blue, will be arranged.

When changing the background color (changing the background color of the image displayed on the TV to the specified color only in a specified range), changing the pattern color (changing the background color of the image displayed on the TV to the specified color) (change only the specified range to the specified color), move (move only the specified area of the image displayed on the TV in the specified direction),
According to Tables 2, 2 and 2, the data of the designated colors, for example 37 corresponding to white and 42 corresponding to green,
Data 53 corresponding to the designated direction, for example, upward, is arranged, followed by data corresponding to the designated range. The first block number (block address) to the last block number (block address) are respectively arranged. In addition, in the case of 4. Character display (characters or pictures are displayed in a specified range with one character in one block in a specified color), uppercase display (characters or pictures are displayed in a ratio of one character in every four blocks). (Display the specified range in the specified color), according to Table 2, data such as “66'' corresponding to yellow and “73” corresponding to cyan are arranged. , followed by the first block number (block address) to the last block number (block address) corresponding to the specified range,
After that, data (pattern data) necessary for displaying characters or pictures is further arranged. Therefore, the reproduced signal from the recording medium includes the data arrangement according to Table 2 as described above.

This reproduction signal is input to the CPU 3 and read.

Based on the read data, the CPU 3 controls writing to the display RAM 4 and color RAM 5 in accordance with command data. Specifically, the CPU 3 has a function to identify the data that has been taken, and a display R according to the recognition output of this recognition function.
It includes a write function unit that specifies a write address for AM4 and color RAM 5 and supplies data necessary for writing. The operation of this is roughly as follows,
For details, please refer to Patent Application 1 "Image Signal Processing Method" filed on October 4, 1973.

FIG. 5 shows a flow chart outlining the operation of the above example.

Now, when data, which is a reproduced signal, is input to the CPU 3 (step S,), in step S2, is the data greater than or equal to 20 and less than or equal to 27? is determined, and if YES, the process moves to the entire surface-color specification program, and if NO, the process proceeds to step S3.
It is determined whether the value is 0 or more and 37 or less.

If YES, the process moves to the background color change program; if NO, the process moves to the next step, ie, S4. In this way, if the determination result is NO, sequential step S5
, S6, and S7, and if the data corresponds to back color change, pattern color change, movement, lowercase letter display, or uppercase letter display, and the result is YES, the program shifts to the corresponding program, and after that, or If both are NO,
Return to step S.

In each of these programs, data corresponding to the color information shown in Table 1 is written into the color RAM 5 based on the data of the reproduced signal, roughly as follows.

For example, if the data is 21, the CPU 3 sets all the contents of the display RAM 4 to "0", backs up all the contents of the color RAM 5, and writes blue data as the data specifying the pattern color. Write 001.

<Change background color> For example, when data 37, 10, IF is input to CPU 3, block number 1 in Figure 4
In the range corresponding to IF from 0 to IF, the data of the back color designating bit in the color RAM 5 is written and changed to white, that is, "111".

<Lowercase display> For example, when 8-byte data corresponding to the character 6604,05 is input to the CPU 3, the block number 4 (
Write 8 bytes of data corresponding to the character "power" from the top to 8 bytes of display RAM 4 corresponding to addresses 4 to 47), and write pattern bits of color RAM 5 corresponding to block number 4. Write data 1, 1, 0 corresponding to yellow in the section.

In this way, while data is written to the display RAM 4 and the color RAM 5, the display RAM 4 and the color R
The contents of AM5 are addressed and read out according to the synchronization signal generation circuit 7, and a video signal is obtained as the output of the mixer 11 via the color multiplexer 9 etc., which is of course displayed on the television or monitor television. It is about.

In such a device, the contents written in the color RAM 5 are read out and displayed as they are, so if this continues for a certain period of time, the display becomes monotonous. Such monotony is caused by an accompanying signal or an externally input signal (referred to as an audio signal or the like) that is unrelated to the accompanying signal during display, such as an acoustic signal.

) can be alleviated by changing the display color depending on the level. In view of this point, it is an object of the present invention to provide an image signal processing device that can change display colors in response to the level of a signal such as an audio signal.

The present invention can be realized by including a color code changing device in an image signal processing device and controlling this by the signal level. An example of this will be explained with reference to FIG. 6.

Note that in FIG. 6, parts that are equivalent to those in FIG. 2 are indicated by the same reference numerals, and the description of these equivalent parts will be omitted below.

This color code changing device 20 obtains a digital signal by A/○ conversion of an input audio signal, etc., and uses this digital signal and a signal from the data bus F of the color multiplexer 9 to input a color changing ROM (Read0OlyMemo).
ry) and outputs color information data whose color code (color information code) has been changed according to the contents of the color changing ROM to the data bus F'.

FIG. 7 shows a block diagram illustrating one embodiment of the color code changing device.

The clock generation circuit 21 oscillates at a frequency of 10 days and supplies a clock to the D/A converter 22.

Note that this D/A converter 22 is a 3-bit D/A converter including a 3-bit counter and some resistance, and can obtain an analog signal. 23 is a comparator that compares the magnitude of the analog signal and the acoustic signal etc. from the ○/A converter 22, and the moment the level of the acoustic signal etc. becomes higher than the output of the D/A converter 22, the comparison output becomes L (low). ) to day (high) generates a rising pulse.

Reference numeral 24 is a so-called D type latch, which latches the 3-bit digital code signal from the D/A converter 22 based on the output of the comparator 23. The 3-bit digital code of the D/A converter 22 at the moment when the output (analog signal) from the A converter 22 crosses from lower to higher is latched.

In addition, 23' and 23'' are variable resistors, and the D/A
The output of the converter 22, the level of the acoustic signal, etc. can be adjusted and input to the comparator 23.

In this way, the level of the audio signal or the like is converted to a digital signal, and a simple A/O converter obtained at latch 24 is implemented.

Note that this D/A converter is controlled in response to a signal from the CPU 3 as described later. 25 is the so-called D type 3
A bit latch which receives the vertical synchronization signal from the synchronization signal generation circuit 7 as its clock input,
The latch operation is executed at that timing.

Furthermore, since this latching operation is performed using a vertical synchronization signal, the latched value does not change during the display period of the TV screen, which prevents irregular noise from occurring due to color code changes on the TV screen. ). Reference numeral 26 is a bipolar ROM in which changes for changing the color code are recorded.

That is, in the bipolar ROM 26, in this embodiment, 3 bits are allocated to a page and 3 bits are allocated to an address within a page, making it possible to change the total six-core weight.
Here, the content of the output from the A/D converter, ie, the output from latch 25, is assigned to the page, and the content of the output from data bus F is assigned to the address within the page.

Table 3 below is an example of the contents (map) of this bipolar ROM 26.

Table 3 In this case, for example, if the content of the color information from the data bus F, that is, the color code, is "0" or "7", the content of the output of the latch 25 that responds to the level of the audio signal, etc., that is, the page is 0.
,...Bipolar ROM26 regardless of 7.
"0" and "7" are output to the data bus F' which is the output of the data bus F'.

Also, if the content of the color information from the data bus F is "1", that is, the color code is "1", the content of the output of the latch 25 is "1".
That is, when the page is "1", "2" is output to the data bus F', and the content of the output of the latch 25 is "3" or "6".
In this case, "4" or "5" is output.

In this way, the content of color information from data bus F is "1".
is changed to "1", "2", . . . "6" in response to the level of the audio signal, etc., and in response to the content of the output of the latch 25, and is output from the data bus F'. Ru.

The content of the color information from the general data bus F is changed into other color information in response to the level of the audio signal, etc., and is output from the data bus F.

Colors are displayed on the TV screen in relation to this output, so the black and white parts on the TV screen do not change depending on the level of the audio signal, etc., but other color parts, such as blue parts, green parts, etc. will be changed.

Of course, the regularity of such changes allows the contents of the bipolar ROM 26 to be freely selected. 27 is a command decoding circuit consisting of a so-called 1-bit town-type latch, which receives a control signal from the CPU 3, outputs "H" when the control signal is high (high), and outputs "H" when the control signal is low (low). ), it outputs "L".

The output of this command decoding circuit 27 is input to the latch 24 of the A/D converter, and when the output is "H", the A/D converter operates to generate a digital signal corresponding to the label of the acoustic signal, etc. A code signal is output from latch 24.

Also, when the "L" output is input to the latch 24, the latch 2
Outputs ``0'' from 4.

Therefore, in the former case, bipolar ROM2
6 changes the code of the signal from the data bus F and outputs it from the data bus F'.

Conversely, in the latter case, bipolar ROM 26 is always page 0.
Since this is selected, the signal on the data bus F is outputted from the data bus F' without changing the code, and the display color is not changed depending on the level of the audio signal or the like. Here, the control signal from the CPU 3 can be obtained, for example, as follows.

This can be realized by causing the CPU 3 to switch the supply of an "H" or "L" control signal to the instruction decoding circuit 27 in response to a signal from a manual switch.

Further, for example, code change command data for instructing a color code change signal is recorded on the recording medium in advance, and the CPU 3 determines whether or not the code change command data is from the reproduced signal, and according to the output of this determination. It can also be configured such that "H" is supplied as a control signal to the instruction decoding circuit. Further, the signal from the data bus F includes a pattern color signal (color code) and a back color signal (color code), and both, or the former or the latter, may be passed through the color code changing device 20. By doing so, the data bus F′
It goes without saying that both, the former or the latter, will be output with their color code changed. For example, if only the latter is passed through, the color of the background of the television screen will be changed using an audio signal or the like.

In the above-described embodiment, various color changes can be obtained by simply replacing the bipolar ROM 26 with a different content.

In addition, as a color code changing device, a common D/A converter is used, and as a means for changing a digital code to another digital code, a common digital code converter is used. Of course, the present invention is not limited to the above embodiments, and can be modified in various ways.

[Brief explanation of drawings]

Figure 1 shows a system diagram using an image signal processing device, and Figure 2 shows a system diagram using an image signal processing device.
The figure is a block diagram of the image signal processing unit before improvement according to the present invention, FIGS. 3 and 4 are explanatory diagrams explaining the allocation of the display RAM and color RAM, and FIG. 5 is the same as the above. FIG. 6 is a block diagram of an embodiment of the image signal processing apparatus of the present invention, and FIG. 7 is a block diagram of the main parts of the same. 1: Recording medium, 2: Demodulator, 3: CPU, 4: Display R
AM, 5: Color RAM, 7: Synchronization signal generation circuit, 1
1: mixer, 12: RF modulator, 20: color code changing device. Figure Ship diagram C, ■ - Ship diagram dimensions of the ship chart - Swallow Figure 5 Figure 7 ○ Ship

Claims (1)

[Claims] 1. By reproducing the recording medium, an image signal consisting of pattern data and color data is reproduced, and at the same time, a vertical synchronization signal and a horizontal periodic signal generated from a synchronization signal generation circuit, and a color control circuit based on the above pattern data and color data are reproduced. In a device that generates a video signal from the output color signal and obtains a color image on a television screen,
means for outputting a color code change signal with content corresponding to the level when the input level of the audio signal is higher than a predetermined level; and storage means for changing the color data to one of the plurality of pre-stored color data according to the color code change signal and outputting the changed color data, the pattern data, and the vertical and horizontal synchronization signals. An image signal processing device configured to output a color signal changed from the color control circuit based on the color signal and generate a video signal.