JPS60233879A - Manufacture of semiconductor light emitting element - Google Patents

Manufacture of semiconductor light emitting element

Info

Publication number
JPS60233879A
JPS60233879A JP59089073A JP8907384A JPS60233879A JP S60233879 A JPS60233879 A JP S60233879A JP 59089073 A JP59089073 A JP 59089073A JP 8907384 A JP8907384 A JP 8907384A JP S60233879 A JPS60233879 A JP S60233879A
Authority
JP
Japan
Prior art keywords
layer
doped
gaas
grown
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59089073A
Other languages
Japanese (ja)
Inventor
Takeshi Kamijo
健 上條
Takashi Ushikubo
牛窪 孝
Akihiro Hashimoto
明弘 橋本
Masao Kobayashi
正男 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59089073A priority Critical patent/JPS60233879A/en
Publication of JPS60233879A publication Critical patent/JPS60233879A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PURPOSE:To contrive the reduction of internal strain generating by impurity doping by a method wherein the growing temperature is restricted to a specific range of temperature in growing an Si-doped GaAs active layer on a GaAs substrate. CONSTITUTION:An n type AlGaAs layer 2 is grown on an n type GaAs substrate 1, and the Si-doped GaAs active layer 3 is grown on this layer 2 at a temperature within a range of 840-940 deg.C. Thereafter, a p type AlGaAs layer 4 is grown on the layer 3. This layer 3 is doped with Si at a high concentration in order to obtain a desired band of infrared wavelength. However, the doping of high concentration impurities into a semiconductor region produces strains in a crystal lattice on account of the difference in size between the atom constituting the mother crystal and the impurity atom. A growing temperature of 840-940 deg.C can be used as a condition for the epitaxial growth of high concentration SiGa in order to inhibit said strain.

Description

【発明の詳細な説明】 (発明の技術分野) この発明は赤外域半導体発光素子の製造方法に関する。[Detailed description of the invention] (Technical field of invention) The present invention relates to a method for manufacturing an infrared semiconductor light emitting device.

(背景技術の説明) 発光ダイオードとか半導体レーザダイオードを含む多く
の赤外域半導体発光素子が提案されている。これら赤外
域発光素子の形成するに当り、活性領域として高濃度に
不純物をドープしたGaAsを用いる方法がある。この
ような高濃度不純物半導体はいわゆる縮退半導体となり
1発光波長におけるバンド端吸収を生じないため、高い
外部量子効率が期待出来ると共に、レーザダイオードの
光学的端面損傷(Catastrophic Degr
adation)の防止にも有効である。
(Description of Background Art) Many infrared semiconductor light emitting devices including light emitting diodes and semiconductor laser diodes have been proposed. In forming these infrared light emitting devices, there is a method of using GaAs doped with impurities at a high concentration as an active region. Such a high concentration impurity semiconductor is a so-called degenerate semiconductor and does not cause band edge absorption at one emission wavelength, so high external quantum efficiency can be expected and it also prevents optical edge damage (catastrophic degr.) of the laser diode.
It is also effective in preventing adduction.

(解決すべき問題点) しかしながら、半導体領域への高濃度の不純物のドーピ
ングは、母体結晶を構成する原子と、不純物原子とのサ
イズの相違に起因して、結晶格子に歪が生じる。この歪
はポテンシャルのゆらぎや、局所的な電場を生じる(文
献: rPhysicalReview BJvol、
213No、2(1884)、p802〜p807記載
のPeter A、 Fedders等の論文)、さら
に、これらゆらぎや、局所的な′電場は、外部的な電界
の印加により、局所的な原子サイズレベルの電界集中や
、電子エネルギーレベルの局在化を生じるため、素子寿
命や、内部発光効率を悪くするという欠点を有していた
(Problems to be Solved) However, doping a semiconductor region with impurities at a high concentration causes distortion in the crystal lattice due to the difference in size between the atoms constituting the host crystal and the impurity atoms. This strain causes potential fluctuations and local electric fields (References: rPhysical Review BJvol,
213 No. 2 (1884), p. 802-p. 807), these fluctuations and the local electric field can be reduced by applying an external electric field to a local electric field at the atomic size level. Since concentration and localization of the electron energy level occur, it has the disadvantage of deteriorating the device life and internal luminous efficiency.

(発明の目的) この発明の目的は、高濃度不純物半導体中での、不純物
ドーピングに起因する内部歪を低減出来る半導体発光素
子の製造方法を提供することにある。
(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device that can reduce internal strain caused by impurity doping in a highly doped semiconductor.

(問題点を解決すべき手段) この目的の達成を図るため、このi明においては1発光
素子を形成している高濃度不純物半導体層の成長を、不
純物ドーピングによる内部歪を低く抑えた条件で行うこ
とを要旨とする。
(Means to solve the problem) In order to achieve this objective, in this i-mechanical method, the growth of a highly-concentrated impurity semiconductor layer forming one light-emitting element is carried out under conditions that suppress the internal strain due to impurity doping. The gist is what to do.

従って、この発明においては、 GaAs基板の上側に
SiドープGa1g活性層を成長させて半導体発光素子
を製造するに当り、このSiドープGaAs活性層を液
相エピタキシャル成長法を用いて840〜840℃の温
度範囲で成長させることを特徴とする。
Therefore, in the present invention, when manufacturing a semiconductor light emitting device by growing a Si-doped Ga1g active layer on the upper side of a GaAs substrate, the Si-doped GaAs active layer is grown at a temperature of 840 to 840°C using a liquid phase epitaxial growth method. It is characterized by growing within a range.

(作用) このような成長温度範囲でSiドープGaAs活性層を
液相エピタキシャル成長させると、Siの゛配位の分配
・を極力均一化するこたが出来、これがため、内部応力
の低減を図ることが出来る。
(Function) When the Si-doped GaAs active layer is grown by liquid phase epitaxial growth in such a growth temperature range, it is possible to make the coordination distribution of Si as uniform as possible, thereby reducing internal stress. I can do it.

(実施例の説明) 以下、図面を参照してこの発明の実施例につき説明する
(Description of Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図はこの発明の説明に要する液相エピタキシャル成
長温度(横軸)と、縦形光学(LO)フォノンモード(
縦軸)と、これに対応する内部応力との関係を示す特性
曲線図であり、第2図はこの発明の詳細な説明に供する
#GaAs/GaAsダブルへテロレーザダイオードの
一例を示す断面図である。尚、この断面図において、一
部分を除き、断面を表わすハツチングを省略して示しで
ある。
Figure 1 shows the liquid phase epitaxial growth temperature (horizontal axis) and the vertical optical (LO) phonon mode (
2 is a characteristic curve diagram showing the relationship between the vertical axis) and the corresponding internal stress, and FIG. be. In this sectional view, hatching representing the cross section is omitted except for a portion.

第2図において、lはn型GaAs基板、2はn型Al
lGaAs層からなる第一クラッド層、3はGaAs活
性層、4はp型AQGaAs層からなる第二クラッド層
、5及び6はオーム性電極である。
In Figure 2, l is an n-type GaAs substrate, 2 is an n-type Al
A first cladding layer made of a lGaAs layer, 3 a GaAs active layer, 4 a second cladding layer made of a p-type AQGaAs layer, and 5 and 6 ohmic electrodes.

このGaAs活性層3には、所望の赤外波長域を得るた
めに、高濃度にSiのドーピングが行なわれている。こ
のドーピングにより、前述したように、内部歪、す崖わ
ち、GaAs結晶の格子に歪が生じてしまう。
This GaAs active layer 3 is heavily doped with Si in order to obtain a desired infrared wavelength range. As described above, this doping causes internal strain, that is, strain in the lattice of the GaAs crystal.

一方、StはGaAs中で両極性不純物として振る舞う
。つまり、SiはGa−格子点及びAs−格子点に配位
することが可廓又多、す、それぞれ電気的にはド十−或
いはアクセプタとして振る舞う、さらに、各格子点への
Siの配位と分配は、通常、半導体レーザ形成に用いて
いる液相エピタキシャル成長法においては、主として成
長温度に比例することが知られている(文献: rJo
urnal of Physics &Chemist
ry of 5olidtJ vol、38 pp 1
041〜1053゜(18?5) 、口、J、Ashe
n等の論文に記載されている)。そして、このSiの配
位の分配によって格子歪の大きさが決まる。この歪は格
子振動における縦形光学振動を反映している縦形光学(
LO)フォノンの半値幅から知ることが出来る。すなわ
ち、この半値幅は格子に加えられた歪を反映する。
On the other hand, St behaves as an ambipolar impurity in GaAs. In other words, Si can be coordinated to Ga-lattice points and As-lattice points, and each behaves electrically as a lattice point or an acceptor. It is known that the distribution is mainly proportional to the growth temperature in the liquid phase epitaxial growth method normally used to form semiconductor lasers (Reference: rJo
Urnal of Physics & Chemist
ry of 5olidtJ vol, 38 pp 1
041~1053゜(18?5), Mouth, J, Ashe
n et al.). The magnitude of lattice strain is determined by the distribution of this Si coordination. This distortion reflects the vertical optical vibration in the lattice vibration (
LO) can be determined from the half-width of the phonon. That is, this half-width reflects the strain applied to the grid.

従って、この縦形光学フォノンモードの半値幅と液相エ
ピタキシャル成長温度の関係を調べれば、発生する歪の
変化の温度依存性を知ることが出来、この関係から歪の
発生を低減出来る成長温度範囲を知ることが出来る。
Therefore, by examining the relationship between the half-width of this vertical optical phonon mode and the liquid phase epitaxial growth temperature, it is possible to know the temperature dependence of changes in the generated strain, and from this relationship, the growth temperature range in which the generation of strain can be reduced can be determined. I can do it.

そこで、この出願の発明者等は、GaAsにドーピング
するSiの濃度を10 c鵬−3の後半から10 c■
−3の前半、特に、〜10 c層−3とした場合につき
、Siの配位により生ずる内部歪の変化をラマン散乱分
光法により評価した。その実験結果を第1図の特性曲線
図に特性曲線■及びIで示す。この第1図には、左側の
縦軸にラマン散乱スペクトルに現われる縦形光学フォノ
ンモードの半値幅を、右側の縦軸に対応する内部応力を
それぞれ成長温度との関係で示しである。
Therefore, the inventors of this application changed the concentration of Si doped into GaAs from the latter half of 10 c-3 to 10 c-3.
For the first half of Layer-3, particularly for the ~10c layer-3, changes in internal strain caused by coordination of Si were evaluated by Raman scattering spectroscopy. The experimental results are shown in the characteristic curve diagram of FIG. 1 by characteristic curves ■ and I. In FIG. 1, the vertical axis on the left shows the half-value width of the vertical optical phonon mode appearing in the Raman scattering spectrum, and the vertical axis on the right shows the corresponding internal stress in relation to the growth temperature.

この実験結果から、歪は、特性曲線Iからも明らかなよ
うに、成長温度が約880℃まではこの成長温度の上昇
とともに減少し、さらに、成長温度が上昇すると、特性
曲線■からも明らかなように、再び増加するという傾向
が伺える。
From this experimental result, as is clear from the characteristic curve I, the strain decreases as the growth temperature increases up to about 880°C, and as the growth temperature further increases, it is clear from the characteristic curve As such, there is a tendency for the number to increase again.

ところで、不純物を含まないGaAsのLOフォノンの
半値幅は4cm−”であり、また、半値幅の拡がり1c
m−”は外部から加えられた応力の大きさ0.113X
 109dyn/c+w2に対応する。それ故、上述の
実験結果による特性曲線I及びIから、SiドープGa
Asにおいては、800℃における内部応力は0.7X
 109dyn/cm2テあり、840℃では0.5X
109dynlCII2であり、その後、温度上昇に伴
ない内部応力はさらに低減し、さらに温度上昇する之応
力は再度増加に転じて、940℃では0.5 Xl09
dyn/cl12となることが分かる。
By the way, the half-width of the LO phonon in GaAs that does not contain impurities is 4 cm-'', and the spread of the half-width is 1c.
m-” is the magnitude of externally applied stress 0.113X
Corresponds to 109dyn/c+w2. Therefore, from the characteristic curves I and I according to the above experimental results, it is clear that Si-doped Ga
In As, the internal stress at 800°C is 0.7X
109dyn/cm2 Te, 0.5X at 840℃
109dynlCII2, and then the internal stress further decreases as the temperature rises, and as the temperature rises, the stress starts to increase again and becomes 0.5Xl09 at 940°C.
It can be seen that dyn/cl12.

一般に、ヘテロ接合から生ずる内部応力は約108d7
n/c■2程度の値であるので1発光素子への影響を考
えると内部応力をこの値と同等以下に抑える必要がある
Generally, the internal stress resulting from a heterojunction is approximately 108d7
Since this value is approximately n/c 2, it is necessary to suppress the internal stress to a value equal to or less than this value when considering the influence on one light emitting element.

従って、この条件を満たすようにするため、こに発明に
よる方法においては、液相エピタキシャル成長法で高濃
度SiドープGaAsを成長させる条件として、840
〜840°Cの成長温度範囲を用いれば良い。
Therefore, in order to satisfy this condition, in the method according to the present invention, 840% Si-doped GaAs is grown using the liquid phase epitaxial growth method.
A growth temperature range of ~840°C may be used.

既に説明したようにここに示された内部応力の低減方法
は、 SiのGa−格子点とAs−格子点への配位の分
配を極力均一化して行われるものであり、また、この分
配比は成長温度で決定されるのであるから、5iil1
度が10”cm−3以外であっても、この分配比は保存
される。従って、液相エピタキシャル成長法でSiドー
プGaAsを成長させる際に成長温度範囲を840〜8
40 ’0程度に設定すれば、このような歪の低減を果
すことが出来ることとなる。
As already explained, the internal stress reduction method shown here is carried out by making the distribution of coordination between the Ga-lattice points and the As-lattice points of Si as uniform as possible, and also by adjusting this distribution ratio. is determined by the growth temperature, so 5iil1
This distribution ratio is preserved even if the temperature is other than 10"cm-3. Therefore, when growing Si-doped GaAs by liquid phase epitaxial growth, the growth temperature range is 840-840cm-3.
If it is set to about 40'0, such distortion can be reduced.

次に、第2図に示すAQ GaAa / GaAsダブ
ルへテロレーザダイオードの製造例につき簡単に説明す
る。液相エピタキシャル成長法を用い、先ず、n型Ga
Ag基板上1にn型N)GaAs層を成長させてこれを
第一クラッド層2とし、次に、この第一クラッド層2上
に、840〜880℃の温度範囲の適当な温度でSiド
ープGaAs活性層3を成長させ、その後に、この活性
層3上に、p型AQGaAs層を第二クラッド層4とし
て成長させる。そして、最終的にP側及びn側オーム性
電極5及び6を蒸着してこのレーザダイオードを得る。
Next, a manufacturing example of the AQ GaAa/GaAs double hetero laser diode shown in FIG. 2 will be briefly described. First, using liquid phase epitaxial growth method, n-type Ga
An n-type N)GaAs layer is grown on the Ag substrate 1 to serve as the first cladding layer 2, and then Si-doped is formed on the first cladding layer 2 at an appropriate temperature in the temperature range of 840 to 880°C. A GaAs active layer 3 is grown, and then a p-type AQGaAs layer is grown as a second cladding layer 4 on this active layer 3. Finally, P-side and n-side ohmic electrodes 5 and 6 are deposited to obtain this laser diode.

この場合、成長温度範囲を840〜880℃としたが、
この温度範囲であると、Siはp型不純物として振る舞
い、p型GaAs活性層3が得られる。これに対し、こ
の成長温度範囲を880〜940℃とすると、n型Ga
Ag活性層を得ることが出来る。従って、所要に応じて
840−840℃の温度範囲内の適切な温度でSiドー
プGaAsの液相エピタキシャル成長を行なえば良い。
In this case, the growth temperature range was 840-880°C,
In this temperature range, Si behaves as a p-type impurity, and a p-type GaAs active layer 3 is obtained. On the other hand, if this growth temperature range is 880 to 940°C, n-type Ga
An Ag active layer can be obtained. Therefore, liquid phase epitaxial growth of Si-doped GaAs may be performed at an appropriate temperature within the temperature range of 840-840° C. as required.

尚、上述の実施例においてはドープするSiの濃度を〜
10I910l9としたが、これは1G”cm−3(7
)後半から10”cm−3の前半の範囲で選定すること
が出来る。
In addition, in the above-mentioned example, the concentration of doped Si is ~
10I910l9, which is 1G”cm-3 (7
) can be selected within the range from the latter half to the first half of 10"cm-3.

また、上述した実施例では、この発明の方法をタプルへ
テロ接合のレーザダイオードに適用した場合につき説明
したが、この発明の方法は、他の発光素子、例えばバイ
ポーラダイオードにも適用出来ること明らかである。そ
の場合には、GaAs基板上に上述した成長条件でSi
ドープGaAs活性層を成長させ、次いで、この活性層
上に反対導電型のAQGaAs層を成長させた後、所要
の電極を被着形成すれば良い。
Further, in the above embodiments, the method of the present invention is applied to a tuple heterojunction laser diode, but it is clear that the method of the present invention can also be applied to other light emitting devices, such as bipolar diodes. be. In that case, Si is grown on the GaAs substrate under the above-mentioned growth conditions.
After growing a doped GaAs active layer and then growing an AQGaAs layer of the opposite conductivity type on the active layer, the required electrodes may be deposited.

さらに、この半導体発光素子の製造に際する他の諸条件
は、製造しようとする素子に適合した任意好適な条件を
設定すれば良い。
Furthermore, other conditions for manufacturing this semiconductor light emitting device may be set to any suitable conditions suitable for the device to be manufactured.

(発明の効果) 上述した説明からも明らかなように、半導体発光素子の
製造に際し、GaAs中にSiをドーピングする場合、
成長温度を制限することにより、ドーピングにより生じ
る内部歪を低減することが出来る。これがため、格子歪
により生ずる原子サイズレベルの電界集中や、電子エネ
ルギーレベルの局所化を抑えることが出来るので、高効
率で、しかも、長寿命の半導体発光素子を簡単、かつ、
容易に製造することが出来る。
(Effects of the Invention) As is clear from the above description, when doping Si into GaAs when manufacturing a semiconductor light emitting device,
By limiting the growth temperature, internal strain caused by doping can be reduced. This makes it possible to suppress electric field concentration at the atomic size level and localization of electron energy levels caused by lattice distortion, making it possible to easily create highly efficient and long-life semiconductor light-emitting devices.
It can be easily manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の半導体発光素子の製造方法の説明に
供する。 SiドープGaAsの液相エピタキシャル成
長温度(’0)と、縦形光学フォノン線の半値(cm−
’ )幅と、それに対応した内部応力の(109dyn
/c■2)関係を示す特性曲線図、第2図はこの発明の
半導体発光素子の製造方法により製造されたダブルへテ
ロ半導体レーザの一例を示す路線的断面図である。 !・・・GaAs基板、 2・・・第一クラッド層(n型AQGaAs層)3 ・
・・GaAs活性層(SiドープGaA+活性層)4・
・・第二クラフト層(P型Al)GaAs層)5.6・
・・オーム性電極。 「、続祁jj、F J) 昭和80年7月22日 2特許の名称 1(導体発光素子−の製造方法 3補正をする者 事件との関係 特許出願人 住所(〒−105) 東京都港区虎ノ門1丁目7番12号 名称(o29)沖電気■業株式会社 代表者 橋本 南海男 4代理人 〒170 廿(988)5563住所 東京
都豐島区東池袋1丁目20番地5池袋ホワイトハウスビ
ル905号 明m書の発明の詳細な説明の欄、図面の簡単な説明の欄
及び図面の第2図 (1]、明細書、第1頁第17行「発光素f−の形成す
る」を「発光素fを形成するAと訂正する。 (2〕、同、第2頁第3行1[atastrophic
 DegradationJをIl’GataStro
phic 0ptical Degradation、
lと訂正する。 (3)、同、第3頁第15行rsiの配位」をff5i
のGaおよびAs格子位置への配位」と訂正する。 (4〕、同、第3頁第16行[均・化するこたJt−4
均・化すること」と訂正する。 (5〕、同、第4頁第2行〜第3行[(横軸)と、・・
φeフォノンモード(縦軸)」を「(横軸)と、S1ド
ープGaAsより得られたラマンスペクトル中の縦形光
学(LO)フォノンモードの半値巾(縦軸)Jと訂正す
る。 (6)、同、第7頁第9行「に発明による」をrの発明
によるJと訂正する。 (、?)、同、第10i第11行「半414 Ccm−
’) %iJ ヲF芋値幅(cm−リJと訂正する。 (8)1図面第2図を、添付した訂止図の通り訂正する
。 第2図 IオーA1戊電掻 6、t〜ムナ1輸ル
FIG. 1 serves to explain a method for manufacturing a semiconductor light emitting device of the present invention. The liquid phase epitaxial growth temperature ('0) of Si-doped GaAs and the half value of the vertical optical phonon line (cm-
) width and the corresponding internal stress (109dyn
/c■2) Characteristic curve diagram showing the relationship. FIG. 2 is a line sectional view showing an example of a double hetero semiconductor laser manufactured by the method for manufacturing a semiconductor light emitting device of the present invention. ! ...GaAs substrate, 2...first cladding layer (n-type AQGaAs layer) 3.
・・GaAs active layer (Si-doped GaA+active layer) 4・
・Second kraft layer (P-type Al) GaAs layer) 5.6・
...Ohmic electrode. ``, Tsuzuki JJ, F J) July 22, 1980 2 Title of patent 1 (Conductor light emitting device - manufacturing method 3 Relation to the case of person making amendments Patent applicant address (〒-105) Port of Tokyo 1-7-12, Toranomon, Ward Name (o29) Oki Electric Industry Co., Ltd. Representative Nankai Hashimoto 4 Agent 170-5563 Address 905 Ikebukuro White House Building, 1-20-5 Higashiikebukuro, Toyoshima-ku, Tokyo In the Detailed Description of the Invention column, Brief Description of the Drawings and Figure 2 (1) of the Specification, page 1, line 17 of the specification, ``Formation of a light-emitting element f-'' has been changed to ``Light-emitting element f-''. Correct A to form the element f. (2), same, page 2, line 3, 1 [atastrophic
Il'GataStro DegradationJ
phic 0ptical degradation,
Correct it as l. (3), page 3, line 15, rsi configuration” as ff5i
``coordination to Ga and As lattice positions''. (4), page 3, line 16
"to equalize and equalize." (5), page 4, lines 2-3 [(horizontal axis) and...
(6) Same, page 7, line 9, ``Invented by'' is corrected to ``J by invention of r''. (,?), same, 10i, line 11 “Half 414 Ccm-
') %iJ ヲF potato price range (cm-riJ) (8) Correct 1 drawing, Figure 2, as shown in the attached correction diagram. Muna 1 import

Claims (1)

【特許請求の範囲】[Claims] GaAs基板の上側にSiドープGaAs活性層を成長
させて半導体発光素子を製造するに当り、前記Siドー
プGaAs活性層を液相エピタキシャル成長法を用いて
840〜940°Cの温度範囲で成長させることを特徴
とする半導体発光素子の製造方法。
When manufacturing a semiconductor light emitting device by growing a Si-doped GaAs active layer on the upper side of a GaAs substrate, the Si-doped GaAs active layer is grown at a temperature range of 840 to 940°C using a liquid phase epitaxial growth method. A method for manufacturing a semiconductor light emitting device characterized by:
JP59089073A 1984-05-02 1984-05-02 Manufacture of semiconductor light emitting element Pending JPS60233879A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59089073A JPS60233879A (en) 1984-05-02 1984-05-02 Manufacture of semiconductor light emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59089073A JPS60233879A (en) 1984-05-02 1984-05-02 Manufacture of semiconductor light emitting element

Publications (1)

Publication Number Publication Date
JPS60233879A true JPS60233879A (en) 1985-11-20

Family

ID=13960675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59089073A Pending JPS60233879A (en) 1984-05-02 1984-05-02 Manufacture of semiconductor light emitting element

Country Status (1)

Country Link
JP (1) JPS60233879A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281384A (en) * 1986-05-29 1987-12-07 Oki Electric Ind Co Ltd Semiconduvctor laser element and manufacture thereof
EP0461766A2 (en) * 1990-06-12 1991-12-18 Amoco Corporation Silicon-doped In y Ga 1-y As laser

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934275A (en) * 1972-07-28 1974-03-29

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934275A (en) * 1972-07-28 1974-03-29

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281384A (en) * 1986-05-29 1987-12-07 Oki Electric Ind Co Ltd Semiconduvctor laser element and manufacture thereof
EP0461766A2 (en) * 1990-06-12 1991-12-18 Amoco Corporation Silicon-doped In y Ga 1-y As laser
EP0461766A3 (en) * 1990-06-12 1992-07-01 Amoco Corporation Silicon-doped in y ga 1-y as laser

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