JPS60231350A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60231350A
JPS60231350A JP59086317A JP8631784A JPS60231350A JP S60231350 A JPS60231350 A JP S60231350A JP 59086317 A JP59086317 A JP 59086317A JP 8631784 A JP8631784 A JP 8631784A JP S60231350 A JPS60231350 A JP S60231350A
Authority
JP
Japan
Prior art keywords
fuse
electrodes
semiconductor device
groove
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59086317A
Other languages
Japanese (ja)
Inventor
Nobuyuki Kajiwara
梶原　信之
Soichiro Hikita
匹田　聰一郎
Yoshihiro Miyamoto
義博 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59086317A priority Critical patent/JPS60231350A/en
Publication of JPS60231350A publication Critical patent/JPS60231350A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make it possible to ensure the cutting of conduction between electrodes at both ends, by providing a groove on a substrate directly under a fuse, so that the fuse is dropped into the groove when the fuse is melted. CONSTITUTION:In a silicon oxide film 11 on the surface of a silicon substrate 10, a square goove 12 is formed by using a photolithography technology. The terminal parts of electrodes 13 and 14 made of gold or aluminum are connected by a bridge shaped fuse 15. The fuse 15 is formed by evaporating indium, lead or the like. When an excessive current flows, the fuse is melted and dropped into the groove, and the two electrodes are completely cut OFF.

Description

【発明の詳細な説明】 （Ｍｌ　発明の技術分野 本発明は、半導体装置に係り、特に半導体装置に使用さ
れるフユーズの溶断を容易■、つ確実に実施できる構造
に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure that can easily and reliably blow out a fuse used in a semiconductor device.

（ｂ）　技術の背景 近年、半導体装置の用途の拡大に伴い、半導体装置相互
、又は回路装置との関連で、−個の半導体装置の故障の
ために、他の半導体装置や回路装置がその影響を受けて
高価な半導体装置が故障するということが発生する。(b) Background of the technology In recent years, with the expansion of the applications of semiconductor devices, in the relationship between semiconductor devices or circuit devices, if one semiconductor device fails, other semiconductor devices or circuit devices are affected by the failure. As a result, expensive semiconductor devices may break down.

例えば大電流ＭＯ３，ＦＥＴ等の場合には屡々経験する
ことであり、このような特別の半導体装置には、成る一
定電流以上の電流が流れると溶断するフユーズを用いら
れるが、従来の構造ではフユーズが平坦な絶縁板上に形
成されているため、過大電流のためにこのフユーズが溶
断しても、熔解するだ番ノで回路を切断することが出来
なかったり、又溶解するのに時間がかかって、半導体装
置が先に故障するという欠点があった。For example, this is often experienced in the case of large current MO3, FET, etc., and such special semiconductor devices use fuses that melt when a current exceeding a certain current flows, but in conventional structures, fuses are Since the fuse is formed on a flat insulating plate, even if the fuse blows due to excessive current, it may not be possible to disconnect the circuit before it melts, or it may take a long time to melt. However, there was a drawback that the semiconductor device failed first.

このようなことから確実に回路を遮断できる半導体装置
のフユーズが要望されている。For this reason, there is a need for a fuse for semiconductor devices that can reliably interrupt the circuit.

（Ｃ１従来技術と問題点 第１図は従来の半導体装置のフユーズの部分の断面図で
ある。(C1 Prior Art and Problems) FIG. 1 is a sectional view of a fuse portion of a conventional semiconductor device.

１は半導体装置のシリコン基板であり、２はシリコン絶
縁膜、３は一方の電極、４は３の電極と接続される他方
の電極であるが、この両電極の間をフユーズ５によって
接続されている。1 is a silicon substrate of a semiconductor device, 2 is a silicon insulating film, 3 is one electrode, 4 is the other electrode connected to the electrode 3, and these two electrodes are connected by a fuse 5. There is.

一般に、電極はアルミニューム（ＡＩ）又は謹（Ａｕ）
等によって形成され、フユーズはインジューム（Ｉｎ）
又は鉛（Ｐｂ）等を蒸着することによって形成されてい
る。Generally, the electrodes are made of aluminum (AI) or aluminum (Au).
etc., and the fuse is indium (In)
Alternatively, it is formed by vapor depositing lead (Pb) or the like.

このような構造の半導体装置のフユーズでは、規定以上
の過大電流が流れてフユーズが溶融しても、溶融したフ
ユーズが、フユーズの下面にある平滑なシリコン絶縁膜
上に溶融したままの状態で残り、両電極の３と４との両
方に接続されたまま溶融状態になっていることがあるた
め、フユーズが溶融しても回路が切断できないままにな
っていて、保護すべき半導体装置が招傷することが屡々
発生ずる。In semiconductor device fuses with this structure, even if an excessive current exceeding the specified value flows and the fuse melts, the melted fuse remains in a molten state on the smooth silicon insulating film on the underside of the fuse. , since the fuse may remain connected to both electrodes 3 and 4 and remain in a molten state, the circuit may not be cut even if the fuse melts, causing damage to the semiconductor device that should be protected. This often happens.

又フユーズが下面の平滑なシリコン絶縁膜−１−に直接
形成されているため、フユーズそのものが、熱容量が増
加したことになり、規定以上の過大電流が流れても、フ
ユーズが溶解するまでに時間がかかり、その間に半導体
装置が損傷することもある。In addition, since the fuse is formed directly on the smooth silicon insulating film -1- on the bottom surface, the heat capacity of the fuse itself has increased, and even if an excessive current exceeding the specified value flows, it will take time for the fuse to melt. During this time, the semiconductor device may be damaged.

ｆｄ＋　発明の目的 本発明は、上記従来の欠点に鑑み、半導体装置のフユー
ズが、過大電流が流入した際には遅滞なく溶解し、且つ
完全に回路を溶断する構造を提供することを目的とする
。fd+ Purpose of the Invention In view of the above-mentioned conventional drawbacks, an object of the present invention is to provide a structure in which the fuse of a semiconductor device melts without delay when an excessive current flows in, and completely blows out the circuit. .

ｔｅ＋　発明の構成 この目的は、本発明によれば、半導体装置の基板上の電
極に接続されていて、規定電流以上の電流が通電される
と溶断する導電Ｈ料が該基板上に設けられた溝−１−に
形成されてなる半導体装置を提供することによって達成
できる。te+ Structure of the Invention According to the present invention, a conductive H material is provided on the substrate, which is connected to an electrode on a substrate of a semiconductor device and which melts when a current exceeding a specified current is applied. This can be achieved by providing a semiconductor device formed in groove-1-.

（ｆｌ　発明の実施例 本発明は、基板表面において熔解したフーズが溶解して
も、変形した形状のままで、最初に固定された位置に残
って両端の接続電極が電気的に伝導性が維持されている
とか、又基板と接触して置かれるために熱容量が大で／
８解に時間を要する等の欠点を除去するために、フユー
ズの直下の基板」二に溝を設りて、フユーズが溶解する
と同時に液状になったフユーズの金属がその溝に落下し
て確実に両端の電極間の導通を遮断する方法であり、又
フユーズのおかれる基板との間に間隙を設けることによ
りフユーズの熱容量を減少ざ廿るものであって、接続さ
れていた両電極を完全に切断することができる。(fl Embodiment of the Invention) In the present invention, even if the molten food melts on the surface of the substrate, it remains in its deformed shape and remains in the initially fixed position, and the connecting electrodes at both ends maintain electrical conductivity. The heat capacity is large because it is placed in contact with the substrate.
8. In order to eliminate the drawbacks such as the time it takes to solve the problem, a groove is provided in the substrate directly under the fuse, and as soon as the fuse melts, the liquefied metal of the fuse falls into the groove, ensuring that the fuse melts. This method cuts off the conduction between the electrodes at both ends, and also reduces the heat capacity of the fuse by creating a gap between it and the board on which the fuse is placed. Can be cut.

第２図は、実施例の一例の断面図である。FIG. 2 is a sectional view of an example of the embodiment.

シリコン基板１０の表面に、酸化シリコン膜１１が２μ
ｍの厚みであり、その表面に一辺が５μｍ程度の四角形
で、深さが１μｍ程度の溝１２をフォトリソ技術を用い
て形成する。A silicon oxide film 11 with a thickness of 2μ is formed on the surface of the silicon substrate 10.
A groove 12 having a rectangular shape with a side of about 5 μm and a depth of about 1 μm is formed on its surface using photolithography.

１３と１４は金又はアルミニュームの電極であり、幅が
３μｍ程度であって基板表面に配置されているが、双方
の電極は溝の縁の部分で途切れていて、その電極の端子
部分は橋状に設けられたフユーズ１５によって接続され
ている。13 and 14 are gold or aluminum electrodes with a width of about 3 μm and placed on the substrate surface, but both electrodes are interrupted at the edge of the groove, and the terminal portion of the electrode is a bridge. They are connected by a fuse 15 provided in a shape.

このフユーズを形成する方法は、電極とフユーズがほぼ
２ｐｍ程度のオーバラップするようにして、フユーズ材
料としてインジューム又は鉛等を蒸着することによって
なされ、溝の内部とか電極周辺部の余分の領域に蒸着し
ないように、このような部分にはレジスト膜で保護する
ことが必要である。This fuse is formed by depositing indium or lead as a fuse material so that the electrode and fuse overlap by about 2 pm, and the fuse is deposited in the inside of the groove or in the extra area around the electrode. It is necessary to protect such parts with a resist film to prevent vapor deposition.

このような構造のフユーズを使用した半導体装置は規定
以上の過大電流が流れるとフユーズが溶融すると同時に
、溝に落下するため、双方の電極を完全に遮断が可能で
あり、半導体装置の保護がなされる。In a semiconductor device using a fuse with this structure, if an excessive current exceeding the specified value flows, the fuse will melt and fall into the groove at the same time, making it possible to completely cut off both electrodes and protecting the semiconductor device. Ru.

（ｇ）　発明の効果 ５　以」二詳細に説明したように、本発明の半導体装置
のフユーズは、動作が迅速であり、且つ確実に回路の遮
断に供し得るという効果大なるものがある。(g) Effect of the Invention 5 As described in detail below, the fuse of the semiconductor device of the present invention has the great effect of being able to operate quickly and reliably interrupting a circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のフユーズの部分の断面図、第２図は本考
案のフユーズの部分の断面図である。 図において、１０はシリコン基板、１１はシリコン絶縁
膜、】２は溝、１３．１４は電極、１５はフユーズであ
る。FIG. 1 is a sectional view of a conventional fuse, and FIG. 2 is a sectional view of a fuse of the present invention. In the figure, 10 is a silicon substrate, 11 is a silicon insulating film, ]2 is a groove, 13 and 14 are electrodes, and 15 is a fuse.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の基板上の電極に接続されていて、規定電流
以上の電流が通電されると溶断する導電材料が該基板上
に設けられた溝上に形成されてなることを特徴とする半
導体装置。1. A semiconductor device, characterized in that a conductive material is connected to an electrode on a substrate of the semiconductor device and melts when a current higher than a specified current is applied, and is formed on a groove provided on the substrate.
JP59086317A 1984-04-28 1984-04-28 Semiconductor device Pending JPS60231350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59086317A JPS60231350A (en) 1984-04-28 1984-04-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59086317A JPS60231350A (en) 1984-04-28 1984-04-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60231350A true JPS60231350A (en) 1985-11-16

Family

ID=13883453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59086317A Pending JPS60231350A (en) 1984-04-28 1984-04-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60231350A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908692A (en) * 1986-06-20 1990-03-13 Kabushiki Kaisha Toshiba Fuse-containing semiconductor device
EP0510900A2 (en) * 1991-04-26 1992-10-28 AT&T Corp. Wetting-based breakable links
JPH05259404A (en) * 1991-12-18 1993-10-08 Internatl Business Mach Corp <Ibm> Micromechanical switch
US7417300B2 (en) 2006-03-09 2008-08-26 International Business Machines Corporation Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof
US7460003B2 (en) * 2006-03-09 2008-12-02 International Business Machines Corporation Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
US7645645B2 (en) 2006-03-09 2010-01-12 International Business Machines Corporation Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
US7656005B2 (en) 2006-03-09 2010-02-02 International Business Machines Corporation Electrically programmable π-shaped fuse structures and methods of fabrication thereof
US7784009B2 (en) 2006-03-09 2010-08-24 International Business Machines Corporation Electrically programmable π-shaped fuse structures and design process therefore
US20130043972A1 (en) * 2011-08-16 2013-02-21 Kuei-Sheng Wu Electrical fuse structure

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908692A (en) * 1986-06-20 1990-03-13 Kabushiki Kaisha Toshiba Fuse-containing semiconductor device
EP0510900A2 (en) * 1991-04-26 1992-10-28 AT&T Corp. Wetting-based breakable links
JPH05259404A (en) * 1991-12-18 1993-10-08 Internatl Business Mach Corp <Ibm> Micromechanical switch
US7417300B2 (en) 2006-03-09 2008-08-26 International Business Machines Corporation Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabrication thereof
US7460003B2 (en) * 2006-03-09 2008-12-02 International Business Machines Corporation Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
US7531388B2 (en) 2006-03-09 2009-05-12 International Business Machines Corporation Electrically programmable fuse structures with narrowed width regions configured to enhance current crowding and methods of fabricating thereof
US7545253B2 (en) 2006-03-09 2009-06-09 International Business Machines Corporation Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
US7645645B2 (en) 2006-03-09 2010-01-12 International Business Machines Corporation Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
US7656005B2 (en) 2006-03-09 2010-02-02 International Business Machines Corporation Electrically programmable π-shaped fuse structures and methods of fabrication thereof
US7784009B2 (en) 2006-03-09 2010-08-24 International Business Machines Corporation Electrically programmable π-shaped fuse structures and design process therefore
US20130043972A1 (en) * 2011-08-16 2013-02-21 Kuei-Sheng Wu Electrical fuse structure
US8922328B2 (en) * 2011-08-16 2014-12-30 United Microelectronics Corp. Electrical fuse structure

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