JPS60231333A - Semiconductor structure - Google Patents
Semiconductor structureInfo
- Publication number
- JPS60231333A JPS60231333A JP59087120A JP8712084A JPS60231333A JP S60231333 A JPS60231333 A JP S60231333A JP 59087120 A JP59087120 A JP 59087120A JP 8712084 A JP8712084 A JP 8712084A JP S60231333 A JPS60231333 A JP S60231333A
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- single crystal
- substrate
- layer
- crystal layer
- zns
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02469—Group 12/16 materials
- H01L21/02474—Sulfides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02469—Group 12/16 materials
- H01L21/02477—Selenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/0251—Graded layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02557—Sulfides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- Materials Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は高品質なＺｎＳ単結晶層を得るための半導体構
造に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor structure for obtaining a high quality ZnS single crystal layer.
（ロ）従来技術
１−Ｖｌ化合物の一つであるＺｎＳ （硫化亜鉛）は、
エネルギーバンドギャップが広いため、青色発光素子を
得るための一つの素材として有望視されている。しかし
、ＺｎＳでは、Ｉ［−’／Ｉ化合物の特徴として高融点
であること、及び組成元素の蒸気圧が高いことのために
、高い結晶性の単結晶が得にくい。(b) Prior art 1-ZnS (zinc sulfide), which is one of the Vl compounds, is
Because of its wide energy bandgap, it is seen as a promising material for producing blue light-emitting devices. However, in ZnS, it is difficult to obtain a single crystal with high crystallinity because the I[-'/I compound has a high melting point and the vapor pressure of the constituent elements is high.
真空蒸着法やスパッタ法は、ＺｎＳ単結晶を得るための
方法として知られているが、上記理由により結晶性や、
純度の点でいまだ満足を与える手法ではない。Vacuum evaporation method and sputtering method are known as methods for obtaining ZnS single crystal, but due to the above reasons, crystallinity and
This method is still not satisfactory in terms of purity.
また、近年出現した分子線エピタキシャル成長法０２）
、下ＭＢＥ法と称す）を用いたものがＪ ｏｕｒｎａ’
ｌ Ｏｆ Ｃｒｙｓｔａｌ Ｇｒｏｗｔｈ ５３（１９
８１）４２１−４３１ 等で報告されている。In addition, the molecular beam epitaxial growth method that has appeared in recent years02)
The method using the MBE method is Journa'
l Of Crystal Growth 53 (19
81) 421-431, etc.
従来、ＺｎＳのＭＢＥでは、ＺｎＳとの格子整合がよい
とぎれるＧａＰや８１基板を用いて行なわれていた。ま
た、ＧａＡｓを基板として用いた場合でも格子の不整合
は大きいが、結構良好な結果が得られていて、ＧａＰあ
るいはＳｉを基板として用いた場合と余り差がない。こ
の理由として考えられるのは格子の整合性が膜質まで直
接的に反映できる程、高品質な膜が末だ得られていない
と考えられる。この様に格子整合性の良いＳｌやＧａＰ
基板を用いても末だ充分高品質な膜が得られない１つの
大きな理由として特にＭＢＥでは成長前の基板表面の清
浄性が成長膜質を大きく支配するということが分ってい
る。Ｓｉは空気中の酸素と反応しやすく表面に５ｉ−０
２を形成する。またＧａＰも酸素と反応しやすくリン酸
化物、ガリウム酸化物が形成される。これら酸化膜を除
去するためには真空中で極めて高温で処理しなければな
らない。たとえばＳｌの場合だと５ｉ−０□を除去する
には１２００℃以上の加熱が必要で、ＧａＰは６３０℃
程度で除去出来るがこの程度の温度番どなれば母材中の
リンも多量に飛び出し、酸化膜除去後のＧａＰ表面は極
めて荒れた表面になる。Conventionally, MBE of ZnS has been carried out using GaP or 81 substrates that have good lattice matching with ZnS. Further, even when GaAs is used as a substrate, the lattice mismatch is large, but fairly good results are obtained, and there is not much difference from when GaP or Si is used as the substrate. A possible reason for this is that films of such high quality that lattice matching can be directly reflected in film quality have not yet been obtained. In this way, Sl and GaP have good lattice matching.
It has been found that one of the major reasons why a film of sufficiently high quality cannot be obtained even if a substrate is used is that, especially in MBE, the cleanliness of the substrate surface before growth largely controls the quality of the grown film. Si easily reacts with oxygen in the air and has 5i-0 on the surface.
form 2. GaP also easily reacts with oxygen, forming phosphorus oxide and gallium oxide. In order to remove these oxide films, treatment must be performed in a vacuum at extremely high temperatures. For example, in the case of Sl, heating to 1200°C or higher is required to remove 5i-0□, while for GaP it is 630°C.
Although it is possible to remove the oxide film at a certain temperature, a large amount of phosphorus in the base metal also comes out at this temperature, and the GaP surface after the oxide film is removed becomes extremely rough.
この様な表面上にＺｎＳのＭＢＥを行なえばその下地表
面の影響を成長膜も受け膜質の低下をもたらす。ＧａＡ
ｓを基板として用いた場合もやはりＧａＡｅの表面に酸
化膜が形成されるがＧａＡｓの場合の酸化物は５７０Ｃ
の真空中熱処理で完全に除去できる。又、５７０ｔ″で
はＧ ａ −Ａ ９表面のＧａやＡｓはそれ程飛び出さ
ず清浄な表面が得られる。この清浄な表面上にＺｎＳの
ＭＢＥを行なえばそれなりに膜質の良好なものが得られ
るが格子不整があるため格子整合の良い基板を用いた場
合に比較して膜質が劣ると予測される。If MBE of ZnS is performed on such a surface, the grown film will also be affected by the underlying surface, resulting in a decrease in film quality. GaA
Even when S is used as a substrate, an oxide film is formed on the surface of GaAe, but in the case of GaAs, the oxide is 570C.
It can be completely removed by heat treatment in vacuum. In addition, at 570t'', Ga and As on the surface of Ga-A 9 do not fly out so much and a clean surface can be obtained.If MBE of ZnS is performed on this clean surface, a film with fairly good quality can be obtained. Due to the lattice mismatch, it is predicted that the film quality will be inferior compared to when a substrate with good lattice matching is used.
（ハ）発明の目的
本発明は斯る点に鑑みてなされたもので、ＧａＡｓ単結
晶基板上に高品質なＺｎＳ単結晶層を積層可能な半導体
構造を提供せんとするものである。(c) Purpose of the Invention The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor structure in which a high quality ZnS single crystal layer can be stacked on a GaAs single crystal substrate.
に）発明の構成
本発明の構成的特徴は、ＧａＡｓ単結晶基板上ｋｃ Ｚ
ｎ Ｓ ｅ単結晶層、Ｚｎ５ｅ １−ｘＳＸからなる
バッファ層、ＺｎＳ単結晶層を連続的に順次積層してな
り、上記バッファ層の組成比Ｘは上記基板側より０から
１へ順次変化することにある。2) Structure of the Invention The structural feature of the present invention is that
An n S e single crystal layer, a buffer layer made of Zn5e 1-xSX, and a ZnS single crystal layer are successively laminated in sequence, and the composition ratio X of the buffer layer changes from 0 to 1 sequentially from the substrate side. It is in.
←剰実施例
第１図は本発明の一実施例を示し、（１）はｎ型単結晶
基板、（２）は該基板上に積層されたＺｎ５ｅ単結晶層
であり、該層はＧａＡＥｌと略等しい格子定数を有する
。（３）は該単結晶層上に積層されたバッファ層であり
、該バッファ層はＺｎＳ ｅ １−ｘｓＸからなりその
組成比ＸはＺｎ５ｅ単結晶層（２）側より順次０から１
に変化する。（４）は上記バッファ層（３）上に積層さ
れたＺｎＳ単結晶層である。←Example Embodiment Figure 1 shows an embodiment of the present invention, in which (1) is an n-type single crystal substrate, (2) is a Zn5e single crystal layer laminated on the substrate, and this layer is made of GaAEl and They have approximately equal lattice constants. (3) is a buffer layer laminated on the single crystal layer, the buffer layer is made of ZnS e 1-xsX, and the composition ratio
Changes to (4) is a ZnS single crystal layer laminated on the buffer layer (3).
また、上記各層の成長はＭＢＦ法を用いて行なう。Further, the growth of each of the above layers is performed using the MBF method.
第２図はＭＢＥ装置を原理的に示したものである。バッ
クグラウンド真空度ｉｏ”’ｒｏｒｒ以下に排気された
真空容器内において、加熱用ヒータを備えた基板ホルダ
ー０１）上に工ｎ（インジウム）メタル（ＩＬ２にて一
生面が（１００）面であるｎ型ＧａＡｓ（力゛リウム砒
素）基板（１）が固着されている。FIG. 2 shows the principle of the MBE apparatus. In a vacuum chamber evacuated to a background vacuum level below io'''rorr, a substrate holder (01) equipped with a heating heater is placed on an indium (indium) metal (the surface of which is (100) in IL2). A type GaAs (lium arsenide) substrate (1) is fixed.
基板（１）と対向する位置には第１〜＠３セル０題〜（
１９が配され、これらの間には主シヤツタ００と個別シ
ャッタ（１６ａ）〜（１６０）が介在されている。また
上記各セル０３１〜０５１には加熱用ヒータ（１７１及
び温度検出用熱電対（旧が夫々装着されている。更に上
記各セル０ｍ〜（１ωには夫々Ｚｎ、Ｓｅ及びＺｎＳが
収納されている。At the position facing the board (1) are the 1st to 3rd cells 0 to (
19, and a main shutter 00 and individual shutters (16a) to (160) are interposed between them. In addition, each of the cells 031 to 051 is equipped with a heating heater (171) and a temperature detection thermocouple (old).Furthermore, each of the cells 0m to 1ω contains Zn, Se, and ZnS, respectively. .
次いで第１図に示した本実施例を第２図に示しゐ た装置を用いて製造す方法を工程別に説明する。Next, the present embodiment shown in Fig. 1 is shown in Fig. 2. The manufacturing method using the equipment will be explained step by step.
八
Ａ、第１工程
本工程ではＧａＡＳ基板（１）表面の酸化膜を除去する
。具体的には上記各シャッタを閉じた状態で基板（１）
を６００ｔ″に２０分間保持する。8A. First step In this step, the oxide film on the surface of the GaAS substrate (1) is removed. Specifically, with each of the above shutters closed, the board (1)
was held at 600t'' for 20 minutes.
Ｂ、第２工程
本工程では基板（１）上にＺｎ５ｅ単結晶層（２）を成
長せしめる。具体的には基板（１）の温度を３２０℃、
第１セルαＪ温度を３００℃、第２セル０沿温度を約２
００℃とし、主シャフタ０印及び第１、第２の個別シャ
ッタ（１６ａ）（１６ｂ）を開となす。斯る状態を約１
時間保持することにより基板（１）上に約１μｍ厚のＺ
ｎ５ｅ単結晶層（２）が成長する。B. Second Step In this step, a Zn5e single crystal layer (2) is grown on the substrate (1). Specifically, the temperature of the substrate (1) was set to 320°C,
The first cell αJ temperature is 300℃, the second cell 0 temperature is approximately 2
00° C., and the main shutter 0 mark and the first and second individual shutters (16a) (16b) are opened. Such a state is about 1
By holding for a period of time, a Z layer with a thickness of approximately 1 μm is formed on the substrate (1).
An n5e single crystal layer (2) is grown.
Ｃ１第３工程
本工程ではＺｎ５ｅ単結晶層（２）上にバッファ層（３
）を形成する。斯る形成条件は、成長開始前の基板（１
）温度を５００℃、第２セル（１舶温度を２００℃、第
３セル０８温度を９８０℃とし、第１個別シャッタ（１
６ａ）以外の各シャッタを開となし成長を開始する。斯
る成長中、基板（１）及び第２セルＣ１４１を夫々０．
６７℃／ｍｉ、ｎ及び０，８３℃／ｍｉ、ｎの冷却速度
で冷却し、上記第２セル０４）温度が１５０℃でかつ基
板（１）温度が２６０℃となった時点で上記第２個別シ
ャッタ（１６’ｂ）を閉となす。斯る第２個別シャッタ
（１６１））が閉となされた時点で上記バッファ層（３
）は約１μｍ成長し、またその組成はＺｎＳｅｍ結晶層
（２）側がＺｎ５ｅであり成長層表面がＺｎＳとなるよ
うにＺｎ５ｅ１．−ｘＳｘの組成比Ｘが０から１に徐々
に変化している。C1 Third step In this step, a buffer layer (3) is formed on the Zn5e single crystal layer (2).
) to form. Such formation conditions are such that the substrate (1
) temperature is 500°C, the second cell (1 ship temperature is 200°C, the third cell 08 temperature is 980°C, the first individual shutter (1
Growth is started by opening each shutter except 6a). During this growth, the substrate (1) and the second cell C141 were each heated to 0.
Cooling was performed at a cooling rate of 67°C/mi,n and 0,83°C/mi,n, and when the second cell 04) temperature was 150°C and the substrate (1) temperature was 260°C, the second cell The individual shutter (16'b) is closed. When the second individual shutter (161)) is closed, the buffer layer (3) is closed.
) grows to a thickness of approximately 1 μm, and its composition is Zn5e1. The composition ratio X of -xSx gradually changes from 0 to 1.
これはＺｎＳ分子中のＳが基板（１）温度２６０ｔ！以
上では斯る基板温度に略比例して基板（１）への付着量
が減少し、またＳθはそのセル温度の減少に略比例して
飛翔量が減少するためである。This means that S in the ZnS molecule has a substrate (1) temperature of 260t! This is because the amount of adhesion to the substrate (1) decreases in proportion to the substrate temperature, and the amount of flying Sθ decreases in proportion to the decrease in cell temperature.
Ｄ、第４工程
本工程は最終工程であり、上記バッファ層（３）上にＺ
ｎＳ単結晶層（４）を成長せしめる。斯る成長条件は第
６セル（１９を９８０℃、基板（１）温度を２６０℃と
し、主シヤツタ（１６）及び第３個別シャッタ（１６（
りを開とする。斯る条件下では約０．７μｍ／ｈの速度
でＺｎＳ単結晶層（４）が成長する。D. Fourth step This step is the final step, in which Z is formed on the buffer layer (3).
An nS single crystal layer (4) is grown. The growth conditions were as follows: the sixth cell (19) was 980°C, the substrate (1) temperature was 260°C, the main shutter (16) and the third individual shutter (16(
Open up. Under such conditions, the ZnS single crystal layer (4) grows at a rate of about 0.7 μm/h.
本実施例より得られたＺｎＳ単結晶層と上記第１〜第４
工程のうち第２、第３工程を省略し、ＧａＡＳ単結晶基
板上に直接形成されたＺｎＳ単結晶層とのフォトルミネ
ッセンス（ＰＬ）強度をノンドープＺｎＳ単結晶の理論
的な発光波長である３５０ｎｍ以上で測定した。第３図
は本測定結果を示し、同図中曲線ａが本実施例により得
られたＺｎＳ単結晶層のＰＬ強度であり、曲線すがＧａ
Ａｓ単結晶基板上に直接形成されたＺｎＳ単結晶層のＰ
Ｌ強度である。尚、曲線ａの測定時の感度は曲線すの測
定時の感度の１０倍である。The ZnS single crystal layer obtained in this example and the first to fourth
The second and third steps are omitted, and the photoluminescence (PL) intensity with the ZnS single crystal layer formed directly on the GaAS single crystal substrate is set to 350 nm or more, which is the theoretical emission wavelength of non-doped ZnS single crystal. It was measured with Figure 3 shows the results of this measurement, in which curve a is the PL intensity of the ZnS single crystal layer obtained in this example, and the curve a is the PL intensity of the ZnS single crystal layer obtained in this example.
P of ZnS single crystal layer formed directly on As single crystal substrate
L strength. Note that the sensitivity when measuring curve a is 10 times the sensitivity when measuring curve a.
第３図から明らかなように本実施例により得られたＺｎ
Ｓ単結晶層の方が長波長側（３５０ｎｍ以上）の深いレ
ベルｌこよる発光が少なくなっている。これは換言すれ
ば膜質の優秀さを示すものである。As is clear from FIG. 3, the Zn obtained in this example
The S single crystal layer emits less light at a deep level on the long wavelength side (350 nm or more). In other words, this shows the excellent film quality.
（へ）発明の効果
本発明によれば高品質のＺｎＳ単結晶層が得られるため
、青色発光素子等のデバイスに一鳳と応用可能となる。(f) Effects of the Invention According to the present invention, a high-quality ZnS single crystal layer can be obtained, so that it can be applied to devices such as blue light emitting elements.
１ｇ１図は本発明の一実施例を示す断面図、第２図はＭ
ＢＥ成長装置を原理的に示す模式図、第５図はＰＬ特性
を示す特性図である。
（１）−Ｃｒ ａ Ａ ８単結晶基板、ｆ２）−Ｚ ｎ
Ｓ ｅ単結晶層、（３）・・・バッファ層、（４）・
・・ＺｎＳ単結晶層。
出願人 三洋電機株式会社
代理人 弁理士 佐 野 静 夫
第４図
第２図
６Figure 1g1 is a sectional view showing one embodiment of the present invention, and Figure 2 is M.
A schematic diagram showing the principle of the BE growth apparatus, and FIG. 5 is a characteristic diagram showing the PL characteristics. (1)-Cr a A 8 single crystal substrate, f2)-Z n
S e single crystal layer, (3)...buffer layer, (4)...
...ZnS single crystal layer. Applicant Sanyo Electric Co., Ltd. Agent Patent Attorney Shizuo Sano Figure 4 Figure 2 Figure 6
Claims (1)
層、Ｚｎ５ｅ １−ｘＳｘからなるバー１７７層、Ｚｎ
Ｓ単結晶層を連続的に順次積層してなり、上記バッファ
層の組成比Ｘは上記基板側より０から１へ順次変化する
ことを特徴とする半導体構造。(1) ZnSθ single crystal layer, 177 bar layers made of Zn5e 1-xSx, Zn
1. A semiconductor structure comprising S single-crystal layers successively stacked one after the other, wherein the composition ratio X of the buffer layer sequentially changes from 0 to 1 from the substrate side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59087120A JPS60231333A (en) | 1984-04-27 | 1984-04-27 | Semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59087120A JPS60231333A (en) | 1984-04-27 | 1984-04-27 | Semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60231333A true JPS60231333A (en) | 1985-11-16 |
Family
ID=13906093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59087120A Pending JPS60231333A (en) | 1984-04-27 | 1984-04-27 | Semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60231333A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113105896A (en) * | 2020-01-10 | 2021-07-13 | 三星显示有限公司 | Method for producing quantum dots, and optical member and device comprising quantum dots |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5752126A (en) * | 1980-09-16 | 1982-03-27 | Oki Electric Ind Co Ltd | Compound semiconductor device |
| JPS5753927A (en) * | 1980-09-18 | 1982-03-31 | Oki Electric Ind Co Ltd | Compound semiconductor device |
| JPS57128092A (en) * | 1981-01-30 | 1982-08-09 | Sanyo Electric Co Ltd | Imbedded type semiconductor laser device |
-
1984
- 1984-04-27 JP JP59087120A patent/JPS60231333A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5752126A (en) * | 1980-09-16 | 1982-03-27 | Oki Electric Ind Co Ltd | Compound semiconductor device |
| JPS5753927A (en) * | 1980-09-18 | 1982-03-31 | Oki Electric Ind Co Ltd | Compound semiconductor device |
| JPS57128092A (en) * | 1981-01-30 | 1982-08-09 | Sanyo Electric Co Ltd | Imbedded type semiconductor laser device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113105896A (en) * | 2020-01-10 | 2021-07-13 | 三星显示有限公司 | Method for producing quantum dots, and optical member and device comprising quantum dots |
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