JPS60229523A - Input information holding circuit - Google Patents
Input information holding circuitInfo
- Publication number
- JPS60229523A JPS60229523A JP8533684A JP8533684A JPS60229523A JP S60229523 A JPS60229523 A JP S60229523A JP 8533684 A JP8533684 A JP 8533684A JP 8533684 A JP8533684 A JP 8533684A JP S60229523 A JPS60229523 A JP S60229523A
- Authority
- JP
- Japan
- Prior art keywords
- outputs
- pressed
- terminals
- output
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/18—Modifications for indicating state of switch
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
Landscapes
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は複数の出力端子のうち所望の出力端子のみに出
力信号を発生させ乙人力情報保持回路に関すえ。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a human-powered information holding circuit that generates an output signal only at a desired output terminal among a plurality of output terminals.
従来より選択されたもの以外の出力’k IJ上セツト
えスイッチ回路の一例として、第1図に示すようなRS
フリップ70ツブ5.6.7及び8會、1出力に対して
1個ずつ用いたものが知られてい40この場合ブツシュ
スイッチ1.2.3及び4はそれぞれフリップ70ツブ
5.6.7及び8のリセット端子に接続さ7″Iえと共
に互いに他の7リツプフロツブのセット端子にも接続さ
れているので、これらブツシュスイッチのうち押された
ものの出力のみに低レベルの出力信号が発生し、他は高
レベルのままとなり、発生ダイオード9.10.11又
1d12のうち対応すえもののみが点灯する。As an example of a conventional setting switch circuit for outputs other than those selected on IJ, the RS shown in FIG.
It is known that flip 70 knobs 5.6.7 and 8 are used, one for each output. and 8 are connected to the reset terminals of 7" and 8, and are also connected to the set terminals of the other 7 lip-flops, so a low-level output signal is generated only at the output of the pressed switch among these bushings. , the others remain at high level, and only the corresponding one of the generating diodes 9, 10, 11 or 1d12 lights up.
しかしながら上述の様に、各入力端子にそれ−i1れ4
つのフリップフロップに接続式れ4為人力A−子側の接
続が過密になり複雑になえ欠点があった。However, as mentioned above, each input terminal has -i1 and 4
Since it is connected to two flip-flops, the connection on the A-child side becomes overcrowded and complicated.
本発明は、上記の欠点全改良すえ為になされたものであ
り、その目的とすと所は、ゲート入力端子の接続配線数
の少い入力1′?を報保持回路全提供すえものである。The present invention has been made to overcome all of the above-mentioned drawbacks, and its purpose is to reduce the number of connection wires for the gate input terminal (input 1'?). The information holding circuit is fully provided.
第2図は、本発明の一′μ梱四會示す回路図であえ。FIG. 2 is a circuit diagram showing one aspect of the present invention.
第2図に於いて、ナントゲート16〜19はRSフリッ
プフロップ13及び14を形成すえ。Ql、Q。In FIG. 2, Nant gates 16-19 form RS flip-flops 13 and 14. Ql, Q.
Q、及び喝けぞハそれナントゲート16.17.18及
び19の出力であえ。QよとQ工及びQ、とQ、は、そ
れぞハ逆相出力であえ。ナントゲート20〜23の出力
は発光ダイオード9〜12會介して電源十Bに接続さ7
″lzo出力Q0及び喝はマルチプレクサ29の2進入
力端子に接続されえ。マルチプレクサ29は入力端子2
4〜27及び出力端子28ケ有する。Q, and let's cheer! That's the output of Nantes Gate 16, 17, 18, and 19. Q, Q, Q, and Q should each have opposite phase outputs. The outputs of the Nant gates 20 to 23 are connected to the power supply 7B via light emitting diodes 9 to 12.
The ``lzo outputs Q0 and Q0 may be connected to the binary input terminals of the multiplexer 29. The multiplexer 29 has input terminals 2
It has 4 to 27 and 28 output terminals.
以上の嘱成によZ動作全以下に説明すえ0表はブツシュ
スイッチ1.2.3及び4のいずれかを押した場合の出
力Q1及びQ、のレベル及び出力端子9.10.11及
び12のうちいずれがLレベルにな4かを示すものであ
4゜
一例として、ブツシュスイッチ1を押すとQl及びQ、
はLとなり、Ql及びQ、はHとなり、これを保持すふ
。同様にブツシュスイッチ2會理すと。1及びQ、Vi
Lとなり、Ql及びQ、はI]となる。プッンユスイッ
チ3及び4についても同様に表のようになえ。以上のよ
うにブツシュスイッチ1.2.3及び4のいずハか’5
j・iすと、ナントゲート16.18又#i17.1
9のIH力Q0、Q、またけζン1、Q2にはブツシュ
スイッチ1〜4のいずれが・理圧さJlkかを示す2進
データが現わrLる。この結果l;記表に示す様にブツ
シュスイッチ1.2.3及び4のいずれか1つの抑圧に
ヌ・1応してナントゲート2o121.22及び23の
出力の1つがLレベルにな4゜従って例えばブツシュス
イッチ1合理圧す石と発光ダイオード9のみが点灯すえ
。次にプッンユスイッチ2’(l−押圧すとと発光ダイ
オード1oのみが点灯し、発光ダイオード9は消灯す4
o又マルチプレクサ29は機数の入力端子にそれぞれ加
えられた仮数の入力信号のうち、2進入力により指雉さ
れた1つを選択して出力4子に尋/11すえもので、こ
れ自体は周知の猶造會有すえものであえ。従ってゲート
17及び19の出力が、マルチプレクサ29に′ 二゛
−加えらtt4と、ブツ
シュスイッチ1.2.3及び4に対応してそれぞれ入力
端子24.25.26及び27のうちの1つが出力端子
28に厨続さねぇ。Based on the above, all Z operations will be explained below. Table 0 shows the level of outputs Q1 and Q, and output terminals 9.10.11 and This indicates which of the 12 is at the L level.4 As an example, when pushbutton switch 1 is pressed, Ql and Q,
becomes L, Ql and Q become H, and hold this. In the same way, if you meet 2 bush switches. 1 and Q, Vi
L, and Ql and Q become I]. Do the same for Punyu switches 3 and 4 as shown in the table. As mentioned above, any of Bush Switches 1, 2, 3 and 4 '5
j・isuto, Nantes Gate 16.18 and #i17.1
Binary data indicating which of the bushing switches 1 to 4 is at the physical pressure Jlk appears in the IH forces Q0, Q and the straddle ζn 1, Q2 of 9. As a result, as shown in the table below, in response to the suppression of any one of the bushing switches 1, 2, 3 and 4, one of the outputs of the Nant gates 2, 1, 2 and 23 goes to L level.゜Therefore, for example, only the push button of the button switch 1 and the light emitting diode 9 will light up. Next, when you press the Punyu switch 2' (l), only the light emitting diode 1o lights up, and the light emitting diode 9 turns off.
Also, the multiplexer 29 selects one of the mantissa input signals applied to the input terminals of the machine, which is inputted by the binary input, and outputs 4 output signals. There are well-known indigenous societies. The outputs of gates 17 and 19 are therefore added to multiplexer 29 (tt4) and one of the input terminals 24, 25, 26 and 27 corresponding to bush switches 1, 2, 3 and 4 respectively It is not connected to output terminal 28.
第3図は8つの入力端子31〜38のいずれが全1時的
に接地させ2ことにより出力端子56、〜63のうち対
応すZものが接地レベルになえものであAoこの為ナン
トゲート39〜44にょF)RSフリッグフロツブ回路
45.46及び47が嘴成され、この出力がナントゲー
ト48〜55によりデコートサれ乙。入力端子31〜3
8のいずれが接地されたかを示す2進出力はRSフリッ
プ70ツブ45.46及び47から並列データとして与
えられ、例えばナントゲート40.42及び44から出
力端子6斗、6ト及び66に導出されZo
以上の様に本発明によ2と選択された入力端子に対応す
え出力端子のみに信号全導出保持すえ入力1′#報保持
回路において、ナンドゲー)f人カ側と出力側に分散配
置すZことが出来乙ので配線がコ^密にならない等の優
れた効果を得Zことが出来0In Figure 3, any of the eight input terminals 31 to 38 are temporarily grounded, and the corresponding output terminals 56 to 63 are grounded to the ground level. 39-44 F) RS flip-flop circuits 45, 46 and 47 are formed, and their outputs are decoded by Nant gates 48-55. Input terminals 31-3
The binary output indicating which of the terminals 8 is grounded is given as parallel data from the RS flip 70 knobs 45, 46 and 47, and is derived from the Nant gates 40, 42 and 44 to the output terminals 6TO, 6TO and 66, for example. As described above, according to the present invention, all the signals are derived and held only at the output terminal corresponding to the input terminal selected as 2. Since it is possible to use Z, it is possible to obtain excellent effects such as preventing the wiring from becoming crowded.
第1図は従来回路の一しリ、第2図は、不発明によ4−
実施例全示す回路図、第3図は、本発明の他の一実施例
金示す回路図である0
16〜23.39〜44.48〜56−・ナントゲート
9〜12・・番発光ダイオードFig. 1 shows a diagram of a conventional circuit, and Fig. 2 shows a diagram of a conventional circuit.
016-23, 39-44, 48-56-.Nant Gate, 9-12, etc. Light-emitting diodes.
Claims (1)
端子及びリセット端子のうちの一方のみ全選択して相互
に接続した複数種類の相互接続点全それぞれ入力端子と
し、上記各RSフリップフロップ回路について各々の出
力及びその逆相用力のうちの一方のみを選択して今数種
類の論理積金得ふ複数の論理積回路?r:設け4ことに
より、上記入力端子のいずれかに一時的に加えらnた入
力情報に応じて上記複数の論理積回路のうち対応すえ論
理積回路のみに1′!特出力を得z4:?にj−た人力
jη報保持回路。For a plurality of RSS flip-flop circuits, only one of the set terminals and reset terminals of each of the plurality of interconnection points connected to each other is selected as an input terminal, and for each of the above-mentioned RS flip-flop circuits, each output and Is it possible to select only one of the negative phase functions and obtain several types of AND circuits? r: By providing 4, 1'! is applied to only the corresponding AND circuit among the plurality of AND circuits according to the input information temporarily applied to any of the input terminals. Get special output z4:? A human-powered information holding circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8533684A JPS60229523A (en) | 1984-04-27 | 1984-04-27 | Input information holding circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8533684A JPS60229523A (en) | 1984-04-27 | 1984-04-27 | Input information holding circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60229523A true JPS60229523A (en) | 1985-11-14 |
Family
ID=13855795
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8533684A Pending JPS60229523A (en) | 1984-04-27 | 1984-04-27 | Input information holding circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60229523A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030017255A (en) * | 2001-08-24 | 2003-03-03 | 주식회사 엘지이아이 | A key display circuit |
-
1984
- 1984-04-27 JP JP8533684A patent/JPS60229523A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20030017255A (en) * | 2001-08-24 | 2003-03-03 | 주식회사 엘지이아이 | A key display circuit |
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