JPS60229378A - Manufacture of variable capacitance diode - Google Patents
Manufacture of variable capacitance diodeInfo
- Publication number
- JPS60229378A JPS60229378A JP8641184A JP8641184A JPS60229378A JP S60229378 A JPS60229378 A JP S60229378A JP 8641184 A JP8641184 A JP 8641184A JP 8641184 A JP8641184 A JP 8641184A JP S60229378 A JPS60229378 A JP S60229378A
- Authority
- JP
- Japan
- Prior art keywords
- recessed section
- layer
- type
- gaas layer
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 230000003213 activating effect Effects 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000012808 vapor phase Substances 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 9
- 230000007423 decrease Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は超階段接合を有する可変容量ダイオードの製法
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a variable capacitance diode with a hyperstep junction.
従来例の構成とその問題点
可変容量ダイオードはｐ−ｎ接合或はショットキ接合に
逆方向電圧を印加することで接合容量を変化させるもの
で、容量変化を大きくするには、半導体内に主接合面か
ら離れるに従って不純物濃度分布が減少するいわゆる超
階段接合が用いられるＯ
超階段接合可変容量ダイオードの形成方法として、例え
ば高濃度不純物を含むＮ 型半導体基板上に同じ導電型
の低濃度不純物を含むＮ−エピタキシャル層を形成し、
次に主接合面から離れるに従ってＮ型不純物濃度が減少
する不純物濃度分布を拡散法、イオン注入法或はエピタ
キシャル法で形成し、しかる後反対導電型のＰ″−拡散
或はンヨノトキ障壁により接合を形成する。この方法で
は熱処理のときＮ 型半導体基板側からのオートドーピ
ングが生じ、Ｎ−エピタキシャル層の不純物濃度が高く
なり、容量変化比をある程度大きくすることが出来なか
った。又容量変化比を大きくするためＮ−エピタキシャ
ル層の厚みを厚くすると透択的Ｑの低下が大きくなる。Conventional configuration and its problems Variable capacitance diodes change the junction capacitance by applying a reverse voltage to the p-n junction or Schottky junction.In order to increase the capacitance change, it is necessary to As a method for forming an O hyperstep junction variable capacitance diode in which a so-called hyperstep junction in which the impurity concentration distribution decreases as the distance from the surface increases, for example, a method for forming an N type semiconductor substrate containing a high concentration impurity and a low concentration impurity of the same conductivity type is used. forming an N-epitaxial layer;
Next, an impurity concentration distribution in which the N-type impurity concentration decreases as the distance from the main junction surface decreases is formed by a diffusion method, ion implantation method, or epitaxial method, and then the junction is formed by P''-diffusion or a non-conductive barrier of the opposite conductivity type. In this method, autodoping from the N-type semiconductor substrate side occurs during heat treatment, and the impurity concentration of the N-epitaxial layer increases, making it impossible to increase the capacitance change ratio to a certain extent. If the thickness of the N-epitaxial layer is increased in order to increase the thickness, the reduction in the transparent Q becomes large.
又逆耐圧を高めるためガードリングを設けたりするが、
これは容量変化比が減少する。Also, a guard ring is installed to increase reverse voltage resistance.
This reduces the capacitance change ratio.
発明の目的 本発明は基板としてＧａＡｓを用い、容量変化比。Purpose of invention In the present invention, GaAs is used as the substrate, and the capacitance change ratio is small.
透択度Ｑ、逆耐圧の最適化が容易な可変容量ダイオード
の製造方法を提供する。Provided is a method for manufacturing a variable capacitance diode that allows easy optimization of transparency Q and reverse breakdown voltage.
発明の構成
本発明は高比抵抗ＧａＡｓ層に凹部を形成し、この凹部
にイオン注入法で不純物を導入し、短時間アニールでイ
オン注入した不純物を活性化し、前記凹部にショットキ
接触を形成する可変容量ダイオードの製造方法である。Structure of the Invention The present invention is a variable method in which a recess is formed in a high resistivity GaAs layer, an impurity is introduced into the recess by ion implantation, and a Schottky contact is formed in the recess by activating the ion-implanted impurity by short-time annealing. This is a method for manufacturing a capacitor diode.
実施例の説明
不純物濃度として１ｏ１８ ｃｒｎ−３の訂型ＧａＡｓ
基板１に気相エピタキシャル法を用いて不純物濃度６×
１ｏ ｃｒｎ 、厚み０．６ ｐｍのｎ−型ＧａＡｓ層
２を成長させる（第１図ａ）。Ｓｉ３Ｎ４膜３を形成し
、写真食刻法を用いて、所望の面積の開孔部をＳｉ３Ｎ
４膜３に形成Ｌ 、 Ｓ ｉ３Ｎ４膜３をマスクとして
ｎ−型ＧａＡｓ層２をエツチングし、ｎ−型ＧａＡｓ２
に凹部４を形成する（第１図４）。Description of Examples Modified GaAs with impurity concentration of 1o18 crn-3
The impurity concentration is 6× on the substrate 1 using the vapor phase epitaxial method.
An n-type GaAs layer 2 having a thickness of 10 crn and a thickness of 0.6 pm is grown (FIG. 1a). A Si3N4 film 3 is formed, and a desired area of the opening is formed using photolithography.
Using the Si3N4 film 3 as a mask, the n-type GaAs layer 2 is etched to form an n-type GaAs2 layer.
A recess 4 is formed in (FIG. 1, 4).
次にＳｉ３Ｎ４膜をマスクとしてＳｉ イオン５をイオ
ン注入する。注入条件は１０ＯＫｅｖで３×１ｏ１２ｃ
ｒｎ−２である。注入後赤外線ランプを用いて１０００
’Ｃで１０秒間アニールし、ｎ型イオン注入層６を形成
する（第１図Ｃ）。ＡＩ を真空蒸着しンヨノトキ接触
７を四部４に形成し、オーミック電極８を訂ＧａＡｓ基
板に形成する。Next, Si ions 5 are implanted using the Si3N4 film as a mask. Injection conditions are 10OKev and 3×1o12c
It is rn-2. 1000 using an infrared lamp after injection
Annealing is carried out for 10 seconds at 'C' to form an n-type ion-implanted layer 6 (FIG. 1C). AI is vacuum evaporated to form a contact 7 on the four parts 4, and an ohmic electrode 8 is formed on the GaAs substrate.
上記実施例で凹部４を形成したのは、所望の併択度Ｑを
得ること及び逆耐圧向上のためである。The reason why the recess 4 was formed in the above embodiment is to obtain the desired degree of combination Q and to improve the reverse breakdown voltage.
透択度Ｑは主にｎ＋型ＧａＡｓ基板１とｎ型イオン注入
層６にはさまれたｎ−型ＧａＡｓ層２の厚みで決するの
で凹部の深さを制御することで所望の透択度Ｑを得るこ
とが出来る。逆耐圧は計算でめられるｎ型イオン注入層
の不純物濃度分布、残存するｎ−型ＧａＡｓ層２の厚み
、不純物濃度以外に表面近傍で起る表面破かいである。Since the transparency Q is mainly determined by the thickness of the n-type GaAs layer 2 sandwiched between the n+-type GaAs substrate 1 and the n-type ion-implanted layer 6, the desired transparency Q can be achieved by controlling the depth of the recess. can be obtained. The reverse breakdown voltage is calculated based on the impurity concentration distribution of the n-type ion-implanted layer, the thickness of the remaining n-type GaAs layer 2, the impurity concentration, and surface fracture occurring near the surface.
凹部４を形成したのは表面破かいを緩和し、逆耐圧を向
上せしめるため設けた。表面破かいを緩和するに必要な
凹部４の深さをめるため、ｎ−型ＧａＡｓ層を充分厚く
して実施例と同様のイオン注入条件でｎ型イオン圧入層
を形成し、凹部の深さを変化させて逆耐圧をめた。第２
図にその結果を示す。第２図から明らかな様に、凹部を
形成することにより、逆耐圧は向上し凹部の深さが０．
１６μｍ以上にすることにより逆耐圧ははソ一定の値と
なる。又第２図で逆耐圧のばらつきを示した様に、凹部
を形成することにより逆耐圧のバラツキも減少せしめる
ことが出来る。The recesses 4 were formed to alleviate surface cracks and improve reverse pressure resistance. In order to increase the depth of the recess 4 necessary to alleviate surface cracking, the n-type GaAs layer was made sufficiently thick and an n-type ion implantation layer was formed under the same ion implantation conditions as in the example, to increase the depth of the recess. The reverse pressure resistance was increased by changing the temperature. Second
The results are shown in the figure. As is clear from FIG. 2, by forming the recess, the reverse breakdown voltage is improved and the depth of the recess is 0.
By setting the thickness to 16 μm or more, the reverse breakdown voltage becomes a constant value. Furthermore, as shown in FIG. 2, the variation in reverse breakdown voltage can be reduced by forming the recess.
イオン注入後短時間アニール法を用いたのは、所望の容
量−電圧特性を得るために用いた。通常の電気炉アニー
ルを用いるとｎ” ＧａＡｓ層からの拡散のため所望の
容量−電圧特性が得られない。又電気炉アニールを用い
ると第２図の点線で示した様に短時間アニールに比して
逆耐圧が低下する。The short-time annealing method after ion implantation was used to obtain desired capacitance-voltage characteristics. If normal electric furnace annealing is used, desired capacitance-voltage characteristics cannot be obtained due to diffusion from the n'' GaAs layer.Furthermore, if electric furnace annealing is used, as shown by the dotted line in Figure 2, the desired capacitance-voltage characteristics cannot be obtained compared to short-time annealing. As a result, the reverse breakdown voltage decreases.
この理由については明らかでないが、横方向拡散による
のではないかと考えている。Although the reason for this is not clear, we believe that it is due to lateral diffusion.
発明の効果
以上実施例で詳述した如く、本発明によれば、所望の容
量変化比、併択的Ｑが得られるのみならず、逆耐圧を向
上せしめることが出来る超階段型可変容量ダイオードの
製造方法でその工業的価値は大である。Effects of the Invention As described in detail in the embodiments, the present invention provides a super-step type variable capacitance diode that not only provides a desired capacitance change ratio and optional Q, but also improves reverse breakdown voltage. Its manufacturing method has great industrial value.
第１図（８）〜（ｄ）は本発明の一実施例の超階段型可
変容量ダイオードの製造工程を示す断面図、第２図は逆
耐圧の凹部の深さ依存性を示す図である。。
１・−ｎ＋型ＧａＡｓ基板、２−−−−＝ ｎ−型Ｇａ
Ａｓ層、３・・・・・Ｓ １３Ｎ４膜、４ ・・・凹部
、５・・ Ｓｉイオン、６・ ・・イオン注入層、７
ノヨノトキ接触、８・・ オーミック電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図
凹ｇＴ５つ深′：！：（／ＬｔｍうFIGS. 1(8) to (d) are cross-sectional views showing the manufacturing process of a super-step type variable capacitance diode according to an embodiment of the present invention, and FIG. 2 is a diagram showing the dependence of the reverse breakdown voltage on the depth of the recess. . . 1.-n+ type GaAs substrate, 2----= n-type Ga
As layer, 3... S 13N4 film, 4... Concave portion, 5... Si ion, 6... Ion implantation layer, 7
Noyonotoki contact, 8... Ohmic electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 concave gT 5 deep':! :(/Ltm
Claims (1)
電形を有する高比抵抗ＧａＡｓ層をエピタキシャル成長
により形成する工程、前記高比抵抗ＧａＡｓ層に凹部を
形成する工程、前記高比抵抗ＧａＡｓ層に形成した凹部
に同−導電形の不純物をイオン注入法で導入し短時間ア
ニールでイオン注入した不純物を活性化する工程、前記
四部にショットキ接触を形成する工程を含むことを特徴
とする可変容量ダイオードの製造方法。a step of forming a high resistivity GaAs layer having the same conductivity type on a low resistivity GaAs substrate of a first conductivity type by epitaxial growth; a step of forming a recess in the high resistivity GaAs layer; The method is characterized by including the steps of introducing impurities of the same conductivity type into the recesses formed in the GaAs layer by ion implantation, activating the ion-implanted impurities by short-time annealing, and forming Schottky contacts in the four portions. Manufacturing method of variable capacitance diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8641184A JPS60229378A (en) | 1984-04-27 | 1984-04-27 | Manufacture of variable capacitance diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8641184A JPS60229378A (en) | 1984-04-27 | 1984-04-27 | Manufacture of variable capacitance diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60229378A true JPS60229378A (en) | 1985-11-14 |
Family
ID=13886123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8641184A Pending JPS60229378A (en) | 1984-04-27 | 1984-04-27 | Manufacture of variable capacitance diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60229378A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63300570A (en) * | 1987-05-29 | 1988-12-07 | Nec Corp | Manufacture of gallium arsenide hyper abrupt varactor diode |
-
1984
- 1984-04-27 JP JP8641184A patent/JPS60229378A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63300570A (en) * | 1987-05-29 | 1988-12-07 | Nec Corp | Manufacture of gallium arsenide hyper abrupt varactor diode |
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