JPS60229363A - Automatic compensator for threshold of mos transistor - Google Patents

Abstract

PURPOSE:To compensate the threshold voltage shifts of MOSs automatically by connecting a MOS for a first sensor to a MOS to be controlled and connecting a MOS for a second sensor to the MOS for the first sensor. CONSTITUTION:A P channel threshold compensating circuit 31 controls the back gate biases of P channel transistors P1, P2 for CMOS inverters I1, I2, and compensates the thresholds of the transistors P1, P2. An output node S4 for P channel transistor P2 for a sensor is connected to each substrate for the transistors P1, P2. An N channel threshold compensating circuit 32 controls the back gate biases of N channel transistors N1, N2 for the inverters I1, I2, and compensates the thresholds of the transistors N1, N2. An output node S5 for a transistor NS is connected to each substrate for the transistors N1, N2 respectively.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention automatically senses the shift in the threshold voltage of a MOS-FET (insulated f-type field effect transistor) and corrects it or sets it to a predetermined value. Sudame no MOS) 9
Automatic correction of sensor threshold! ! :Relating to placement.

[Technical background of the invention]

Figures 1 and 2 are for N channels, respectively.

A general structure of a P-channel MOS-FET is shown. That is, in FIG. 1, reference numeral 1 denotes a P-type silicon substrate 1, on which a source region 2 and a drain region 3 made of an N+ type impurity layer are diffused and formed. A dirt electrode (for example, a polysilicon layer) 5 is formed thereon via a dirt oxide film (5in2 film) 4. Note that 6 is a substrate electrode region υ made of a P+ diffusion layer formed on a part of the surface of the silicon substrate 10,
Normally, a source potential V (ground potential) is applied to the substrate 1 through this electrode region 6 as a back dart bias. In this N-channel MO8-FET K, by applying a positive potential to the dirt electrode 5,
The source and drain become conductive (turned on).

On the other hand, in FIG. 2, reference numeral 7 denotes a NW silicon substrate, on a part of which a source region 8 and a drain region 9 made of a P+ type impurity layer are diffused and formed.
, 9 on the substrate through the dirt oxide film 4.
is formed. Note that 10 is the silicon substrate 70 described above.
Normally, a source potential VDD (positive potential) is applied to the substrate 7 through the electrode region 10, which is formed of a diffusion layer formed on a part of the surface, as a positive voltage. P channel MO8=FET like this
When the ground potential is applied to the r-to electrode 6, conduction is established between the source and the drain.

[Problems with background technology]

By the way, during use of the LSI etc. having MO8) transistors, the dirt oxide film 4 may be damaged due to some external cause.
Positive charges may accumulate inside. In this case, an N-channel transistor.

Each threshold value of P-channel transistor vTIN + VTH
A problem arises in that P is shifted to the negative side, the mark on the low level side of the N-channel transistor is reduced, and the switching speed of the P-channel transistor is reduced.

Further, in an LSI having a CMO8 circuit using a P-channel transistor and an N-channel transistor, the shift of the threshold value of L1 causes a problem that the characteristics of the circuit change and the operating margin of the circuit decreases significantly.

In addition, due to the miniaturization of transistors accompanying the integration of LSIs having transistors (MO8), especially in the case of N-channel transistors, channel hot The problem is that the electron effect occurs and the threshold voltage VTilN shifts to the positive side, reducing the switching speed and deteriorating the performance of the circuit.9 This problem will become very worrying as the integration becomes even higher in the future. This is an important issue.

However, with conventional LSIs, etc., no measures have been taken to automatically correct the shift of the threshold value as described above when it occurs during use, and the shift may cause the threshold value to permanently change. As a result, the usable time (guaranteed time for normal operation) of the LSI % is inevitably significantly limited.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is capable of automatically correcting shifts in the threshold voltage of MOS transistors due to external causes during use or due to miniaturization during high integration. Another object of the present invention is to provide an automatic correction device for a MOS transistor threshold value that can prevent deterioration of circuit performance caused by the above shift.

[Summary of the invention]

That is, the MOS transistor threshold automatic correction device of the present invention is provided on the same semiconductor chip as the controlled 1v10S transistor or on a separate chip, and the first sensor MO transistor and the transistor whose source and substrate are connected to each other. ,
a dart voltage source and a source voltage source that provide an effective dart bias that reverses the first capacitor MOS transistor from a conductive state to a non-conductive state or vice versa when a threshold shift of a predetermined amount occurs in the first capacitor MOS transistor; 1 for sensor MO3) Connect a resistor or source to the drain of the transistor.
A predetermined voltage source connected via a second sensor MO8) transistor whose substrates are connected to each other and the drain potential of the first sensor MO8) transistor are supplied to the substrate of the controlled MO8) transistor. The present invention is characterized in that it includes wiring.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Figure 3 shows a part of an LSI having MOS transistors, where ``l'' is a P-channel transistor P, an N-channel transistor N, and a VDD power supply and a VIN+
A first CMOS inverter is connected in series with a power source, and each dart is commonly connected. Similarly, 11 is a P-channel transistor P and an N-channel transistor N,
and a second CMOS inverter consisting of the first CMOS inverter.
is cascaded to a CMOS inverter I. Note that Sl is an input node, and Sl and sj are output nodes.

On the other hand, 31 is the CMOS inverter I, , I.

This is a P-channel threshold correction circuit for controlling the pack dart bias of P-channel transistors P, , P, and correcting their dark values. its drain (output node S,) is connected to V+ptFE through a resistor R, its f−) UVap voltage source
connected to the source. The output node S4 is connected to each substrate of the P-channel transistors P1+P1 of the CMOS inverter '1+11.

Further, 32 is an N-channel dark value correction circuit for controlling the packed dirt bias of the N-channel transistor N 1 + N 1 of the CMOS inverter It+11 and correcting its threshold value. Its source and substrate are connected to the VIeN power supply, its dart is connected to the Vos' voltage source voltage, and its drain (output node Ss) is connected to the VIeN power supply through the resistor R1.
N Connected to voltage source. The output node S6 is connected to each substrate of the N-channel transistor Nl+Nl of the CMOS inverter Il+2.

Next, the operation of the above LSI circuit 1 will be explained. Now, LSI
Consider the case where the dark voltage of each transistor shifts to the negative side due to some external cause during use. in this case,
The initial threshold voltage of each of the N-channel transistor N and P-channel transistor Pa for the sensor is VTN.
The threshold shift amount of 8 and VTPSl is lVTN.
g and Δvtp 8. In addition, the initial dark value voltage of each controlled N-channel transistor N1 r N 1 whose pack dart bias is controlled is v'rs
1 The threshold shift amount for each is ΔVTN N1 r N The threshold for each when the N-channel transistor for the sensor performs the switch operation after 1 shift is vts'
It is expressed as Similarly, the initial dark value voltage of each of the controlled P-channel transistors Pl+Pl is VTP%, and the threshold value shift lever of each is ΔVTP, and the p, +P! when the P-channel transistor for the sensor performs a switching operation after shifting. Each darkness value is expressed as V7p'. Also,
The sensor N-channel transistor N8 is off in the initial state, and its dart bias (VGN
-VIIN) is selected. Further, the P-channel transistor P8 for the sensor is on in the initial state, and its dart bias VGP-VIP is selected so that it is turned on when a shift of the absolute value 1ΔVTPI or more of the threshold value Δvtp occurs. .

Therefore, in the initial state, the sensor N-channel transistor N8 is off, and the P-channel transistor P
a is on, and the controlled N-channel transistor N
L r N! VI as/J Tsukudato Bias
By applying pressure to N1, its dark value becomes the initial value VTH, and the controlled P-channel transistor PIIP2 is set to VIp1 as pack r-1 bias.
By applying 11 pressure, the threshold value becomes the initial value VT.
It is P.

On the other hand, when the threshold value of each transistor shifts, the N-channel transistor NB for the sensor is turned on;
P-channel transistor P.

L is turned off. Due to this, a lower ■Σn% pressure than before is applied to the controlled N-channel transistor Nl, N as a pack gate bias, so that its threshold value becomes higher than the value after the shift VTN+Δy TN/. It is corrected to return to the initial value VTH, and a lower VzN'dL pressure than before is applied as a backdate bias to the P-channel transistors P and IF5. Therefore, the dark value changes from the shifted value VTP+ΔTP' to the initial value. Corrected to return to VTP.

Next, the above operation will be explained in detail based on numerical examples. M.O.
As is well known, the relationship between the threshold voltage vrn of the S) transistor and the R-) bias is expressed by the following equation.

However, the fourth term on the right side is a 10 sign in the case of N channels and a 1 sign in the case of P channels.

Replace with VTR = A Sat/B (129'fl+1Vnol)
-(4) is obtained.

The initial value VTN of N-channel transistors N, , N, is
Pack dirt noise is obtained by VllG=ViN, so VTH= A + 2%l + lVt5l) = 1
5). N-channel transistor N l + N2
(value VTN when the sensor is turned on after dark value shift)
' is obtained by ■BG=■εN, so VTN'
= A + B (1211zl + IVINI)
−(6). In order for the shift error between the threshold values VTN and VTN' to cancel out the threshold shift amount ΔVTN, the following holds true: ΔVTN:VTN'-VTN = A Metamensho - A; Menkari... (7) There are 8 fleas. Here, if ΔVTN is set to, for example, 10.3V, the value of the other can be set by setting either VIN or VIN (for example, VIN=OV=Vllll+).
Threshold 1 direct shift amount ΔVTN8 of channel transistor NB
and a controlled N-channel transistor N I + N
! (threshold shift) MΔVTN, there is a relationship of ΔVTN ``” ΔVTN8 X aw - (8), and the above αN can be determined empirically.

Here, the threshold shift it due to external causes is larger in the controlled transistor in the operating state than in the sensor transistor in the off state in the initial state, and α in the above equation (9)
N can be considered to be 〉1.

In addition, as mentioned above, the dart bias (YON-VzN) applied to the N-channel transistor N for the sensor
As above, when the threshold value of the transistor N8 shifts from VTN[+ by ΔVTN8],
・ is pre-selected to be "', and the following formula % formula % is established.Substituting both formulas (9) into the above formula 〇〇, ∆■ tN VaN = VrNs + - 10 VEN = J ]) αN.Also, AiJ formula (7) Yoshi1■訃1=Leave(Me1gununtaishifu-b-ΔVT,)2-12
φf1...(2), where VεN is a negative potential, and substituting both equations (3) into the above equation (2), we get +12φ...α1, and converting the above equation (2) into both equations Qυ. Substituting it gives .

Here, to simplify the explanation, VtNa=0.8y+
Assuming ΔvTN=-〇, 3v, αN=1.2, the controlled N-channel transistor NI+N! with pack dirt bias increment (VxN-VIN)=-5v. Assuming that it is possible to increase the dark value voltage by 0.3v and the initial pack gate bias VrN=Vsg=Ov, then VzH=5v and both equations are 0υ. That is, if vTNB and αN are fixed and the N-channel threshold value correction circuit 32 is designed to correct the shift when a threshold value shift of ΔVTN occurs, give -5V as VMN and -4V as YON. , 45v.

On the other hand, also in P channel transistor P1+P1,
In order for the shift value between the threshold value VTP and V↑P' in the pack dirt bias VIP r vKP to cancel ΔVTP, -ΔVTP"'vtp' VTP = -1/B (+2φfl + IVgpl) + mmarpl) ・...<1 holds true, Δ■, rP=ΔVTPB P6
The dart bias (VGP - Vlp) is selected in advance so that the transistor Ps is turned off when the threshold of the transistor Ps shifts by ΔVTPB, and VOP-VIP = VTP8 + ΔVtps -1ae.
holds true. Substituting both formulas α into the above formula 〇〇, it becomes Δvtp Vop = Vtps +-+Vrp - (11αP.Here, if VIP is the positive acid position, the previous formula αυ
, (3) YOshi12φf1...Ken and Nashi, substitute the above equation - into both equations (to) to obtain ΔVTP VGP"VTPB+□ αP -12φf1...91).Here, the explanation For simplicity, Vrpa
=-0,8v +ΔVTP =-0,3v, αp=1
．． 0, the pack dart bias increment (Vgp −
Assuming that it is possible to increase the dark value voltage of the controlled P-channel transistors P, I + PR by 0.3v (the absolute value decreases) with VIp ) = -1v, r-tobias VIP = VDD = 5 v
Then, V! Since p=6v, both equations (to) are satisfied.

Note that in each of the above embodiments, the controlled transistor is a CMO
Although it was an S inverter circuit, it is not limited to this and other CMO
There may be three circuits, and although one N-channel or P-channel transistor is used as the sensor transistor, the present invention is not limited to this, and a sensor transistor with a CMO8 configuration may be used. That is, in the threshold value correction circuit 4 shown in FIG.
The substrate of the P-channel transistor P8 is connected to the vI voltage source, and the f-t is connected in series between the
connected to a p-voltage source, and the N-channel transistor Ns
The substrate is connected to the vE voltage source, and the dart is connected to the VaNt pressure source. In the initial state, the P-channel transistor PB is on, and the N-channel transistor N is off. After channel transistor N8 turns on/off, P
Each dart bias (Vop-Vr) r (You
Vz) has been established.

Therefore, the controlled N-channel transistor N is given V as the packed dart bias in the initial state, and after its threshold is shifted, VZ is given as the packed dart bias, so that the threshold becomes the initial value. Corrected to return.

In this case, the sensor P-channel transistor P8. N
The on-resistance and off-state of each channel transistor NB,
It is desirable to optimize the turn-on timing to ensure sufficient margin for correction operation.

In addition, each of the previous ml embodiments has a threshold correction circuit and a controlled circuit (
CMOS inverter r,, 12, etc.) on the same LSI
Although these are provided on a chip, they may be provided on separate chips, or may be provided as independent semiconductor devices so that the threshold value correction circuit is shared by a plurality of LSIs.

FIG. 5 shows a part of an LSI according to another embodiment of the present invention, in which the back gate bias is switched and supplied in order to correct the threshold value VTN of the N-channel transistor of the cMOS inverter (, /). A correction circuit 51 is provided.In this threshold correction circuit 51, the source and substrate of an N-channel transistor N8 for the sensor are connected to the VIN voltage source, its dart is connected to the VGN i voltage image, and its drain ( The output node Sa) is connected to the VIeN voltage source via a resistor R3.The output node S6 is connected to the substrate of the N-channel transistor N1 of the CMOS inverter (, /).

Next, the operation of the above LSI circuit will be explained. Let us consider a case where the threshold of a 9N channel transistor Nl,N shifts to the positive side during use of the LSI due to the channel hot electron effect due to the miniaturization of transistors accompanying higher integration of LSI. The sensor N-channel transistor N8 is turned on in the initial state, and the controlled N-channel transistor N8 is turned off when the threshold value shifts by more than a predetermined amount (Δvts). VGN-VIN) is selected.

Therefore, in the initial state, the sensor N-channel transistor raster Na1d is on, and the controlled N-channel transistor N1 is set to VIN as the pack dart bias.
By applying a voltage, the threshold value changes to the initial value VTH
It has become. On the other hand, when the threshold values of the transistors are shifted, the sensor N-channel transistor N8 is turned off, and the controlled N-channel transistor N8 is turned off as a back gate bias.
By applying the gs voltage, the threshold value is corrected to become lower from the shifted value VTN+ΔVTN and return to the initial value VTN. In this case, assuming that the dark value of the controlled transistor Nl when the sensor transistor is turned off is VTN', the shift amount between the threshold VTN * vTN' must be -ΔVTs to cancel out the threshold shift amount ΔvTN. =VTs'VTN...(2) There are fewer 8 fireflies that hold true. In addition, the N-channel transistor Na for the sensor (VGN VsN)
1, upper 6 transistors N8's FikJ1 direct voltage; pre-selected so that the above transistor N8 would turn off when shifted by Δ■ NB from the initial value VTNB,
The following formula % formula % holds true. Therefore, from Ryoshikikan, 1VIN+=-! (B(12 ear songs-'Vt*)2-1
2φfl ・(I, and VIN is a negative potential, the above formula (
Substituting c) and reduction (3) into both equations, VON=VTNII+ΔVTNa −VIN”VTNI
I+ΔVTNa +12φf1 (c) is obtained.

Here, to simplify the explanation, N VTNll=0.8
V.

Assuming ΔVTN=0.3 v and αN=1.0, the threshold of the controlled N-channel transistor N1 is set to 0.
Assuming that it is possible to reduce the voltage by 3V, and assuming that the pack dirt bias at the time of correction is Vzs=Vas=Ov, V
If IN=-5V, it will be OFF, and both types of wires will be OFF.

〔Effect of the invention〕

As described above, the MOS transistor threshold automatic correction device of the present invention may be affected by external causes during use of a semiconductor integrated circuit provided with MOS transistors or due to miniaturization during high integration. Shifts in threshold values of MOS transistors can be automatically corrected. Therefore, it is possible to prevent the deterioration of circuit performance caused by the above-mentioned Schiff)K, and it is possible to significantly extend the usable time of the semiconductor integrated circuit. Moreover, the device of the present invention has a conventional design,
It is easily realized using manufacturing technology, and dark value correction is possible by controlling the bias of one or more controlled MO8) transistors with one threshold value correction circuit. Therefore, it has the advantage that the structure is simple and the increase in the area of the front and back surfaces is small.

[Brief explanation of drawings]

Figures 1 and 2 are respectively conventional N-channel MOS
-FET and P-channel MO8-FET; FIG. 3 is a MOS according to the present invention; FIG. FIG. 3 is a circuit diagram showing another embodiment of the present invention. Nl r N2 + Pl r P 2...Controlled transistor, N81 PR...Sensor transistor, VIN + VIN r VGN + VIP +
vgp l VGP + ■I +V, ... Voltage source, ■+ + ■3 + I% ・” CMOS inverter. Applicant's representative Patent attorney Takehiko Suzue?l';1 Figure 2 Figure 3

Claims (4)

[Claims] (1) A first sensor MOS transistor that is provided on the same semiconductor chip as the controlled MO8) transistor or on a separate chip, and whose source and substrate are connected to each other, and a a gate voltage source and a source voltage source that provide an effective dart bias to reverse from a conductive state to a non-conductive state or vice versa when a quantitative threshold shift occurs; and a MO for the first sensor.
8) A second sensor MO in which a resistor or a source and a substrate are connected to each other to the drain of the transistor 8) A predetermined voltage source connected through two transistors and the first sensor MO 3) The drain potential of the transistor. The controlled M
O8) A MOS device which is equipped with wiring for supplying to the substrate of the transistor.) An automatic correction device for the transistor darkness value. (2) The MO8) transistor for the second sensor is
MO8) A patented transistor for a sensor, characterized in that it is of a conductivity type different from that of the first sensor MOS transistor, and is provided with an effective dart bias so that its conduction state is opposite to that of the first sensor MOS transistor. Automatic threshold correction device. (3) The MOS according to claim 1, wherein the first sensor MOS transistor is of the same conductivity type as the controlled MO8 transistor.
Automatic correction device for transistor threshold. (4) The controlled MOS transistor is composed of a P-channel transistor and an N-channel transistor in a CMOS circuit, and the first sensor MOS transistor is provided corresponding to each of these two types of transistors. An automatic correction device for a transistor threshold value according to claim 1.