JPS60229142A - Microcomputer - Google Patents

Abstract

PURPOSE:To omit an instruction exclusive for bit decision of data on a RAM and to simplify an instruction system by executing a prescribed instruction immediately before the execution of a bit decision instruction of an accumulator, therefore deciding the bit of the RAM data. CONSTITUTION:When a bit decision instruction of an accumulator is executed, an instruction decoder 16 delivers a control signal ACTAL to control a selection circuit 15. At the same time, an instruction (RAM bit decision instruction) to be executed before the bit decision instruction of the accumulator is executed. Then the decoder 16 delivers a control signal BTAL and a TMB signal. The signal TMB is applied to a delay circuit 18 and delayed consecutively until the execution is through with a RAM bit decision instruction. The output of the circuit 18 is applied to a gate circuit 19. When the bit decision instruction of the accumulator is executed independently, the signal ACTAL is applied to the circuit 15. However the signal ACTAL is cut off by the circuit 19 with the output of the circuit 18 if the bit decision instruction is executed after the RAM bit decision instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a microcomputer having an Akinimulator bit judgment instruction, and in particular to a microcomputer Ktll processor capable of bit judgment of data stored in RAM&C. .

(b) Prior Art Generally, microcomputers are provided with various bit judgment instructions. The bit judgment instruction determines whether a bit specified by immediate data included in the instruction code is a predetermined value, and if it is a predetermined value, loads the immediate data included in the instruction code into the program counter. , is a so-called branch instruction that branches the program to a target address, and if it is not a predetermined value, executes the next instruction and advances the program.

Conventionally, as shown in FIG. 1, in a microcomputer in which the output of an accumulator (2) is applied to an ALU (11), a bit judgment instruction for the accumulator (2) is provided, but a bit judgment instruction for RAM+31 is not provided. Therefore, when performing a bit determination of RAM+3), first transfer data from RAM (31) to accumulator (2) via data bus (4) by executing a transfer instruction, and then transfer data from accumulator (2) to accumulator (2). A bit judgment instruction is executed.Then, the control signal output from the instruction decoder (5) causes ALU(1
) performs bit judgment of accumulator (2) and outputs the result as branch control signal BRN, resulting in RA
This means that the bit determination of M(3) data has been made.

In this microcomputer, when data is transferred from RAM (3) to accumulator (2), the data previously stored in accumulator (2) is erased, so the bit judgment of RAM (3) is performed. In some cases, it is necessary to execute an instruction to save data in the accumulator (2) to another register or the like in advance, which has the disadvantage of increasing the number of program steps.

On the other hand, as shown in Fig. 2, the accumulator (6)
In the microcomputer, the output of the data bus (sword data) is switched by the control signal from the instruction decoder (8) and applied to the input of the ALU (9). In addition, a RAMQOI bit determination instruction is provided.

That is, when the RAM ([1) bit judgment instruction is executed, the data bus (7) is connected to the input of the ALU (9) by a control signal from the instruction decoder (8),
Data in RAM (II) is transferred directly to ALU (9),
A bit determination is made in the ALU (9). In this microcomputer, it is necessary to prepare a plurality of bit judgment instructions dedicated to the RAM, which causes problems when the number of instructions increases and the ability of an instruction decoder or the like is limited. The provision of such a bit judgment instruction exclusively for RAM was proposed by the applicant on August 2, 1981.
``Microcomputer Material Series No.'' published on 0th.

8LC6500 Series User's Manual", pages 90 and 91.

(c) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to minimize the increase in the number of program steps and the number of instructions when performing bit determination in RAM without erasing data in the accumulator. The purpose is to limit the

2) Structure of the Invention The present invention provides a RAM for storing data and an ALU for performing calculations.
, an accumulator (AC) that temporarily stores data, an instruction decoder that decodes instructions and controls each circuit, and a data bus that transfers data. In the microcomputer in which the bit determined by the ALU is determined, the control signal is output from the instruction decoder when the bit determination instruction is executed, or the control signal is output when a predetermined instruction is executed. a selection circuit that is controlled to select and output data from the accumulator or data from the data bus; an accumulator latch that temporarily stores data output from the i selection circuit and applies it to the ALU; a delay circuit that delays a control signal output from the instruction decoder until the next instruction is executed; and a gate circuit that blocks the control signal output when the bit judgment instruction is executed by the output of the delay circuit. By executing the bit judgment instruction immediately after the predetermined instruction, the specified data in the RAM is applied to the ALU via the selection circuit and the accumulator latch, and a bit judgment is performed. be.

(e) Embodiment FIG. 3 is a partial block diagram of a microcomputer showing an embodiment of the present invention. The data bus aD is an 8-bit transmission line that sends and receives data between internal circuits, and the RAM (12) and the RAM (12) to which data is written and read in 8-bit units via the data bus (11). An accumulator 0 that inputs and temporarily stores data to be calculated from a data bus (111) is connected to an ALU (141) that performs calculations and bit judgments.The data stored in the accumulator I via the data bus I is The output of aJ is applied to the selection circuit a!9.

Further, the other input of the selection circuit a9 is connected to the data bus Ql.
) are connected, and the control signals BTAL and A output from the selection circuit a and the main instruction decoder a@
It is controlled by CTALK and selectively outputs the data of the accumulator a31 or the data from the data bus Qll to the accumulator controller αη.

The accumulator latch surface is a storage circuit that holds the data to be operated on during the execution of an operation in the A-LU (141), and its output is connected to the input of the ALUQ41. It is controlled by a control signal BTK output from
Addition or subtraction is performed and the result is output to the data bus OD.Furthermore, at the time of bit judgment, only the specified bit of the data to be judged E is subjected to a bit judgment by ANDing with the data of °°1', etc., and the result is sent to the control signal BRN. Output as .

That is, if the bit judgment result is [yes J, immediate data indicating the branch destination address included in the code of the bit judgment instruction is loaded into the program counter by the control signal BRN, and the program is branched. If "no", the control signal BRN is not output and the program proceeds to the next step. The instruction decoder (L61) decodes the instruction to be executed and outputs a signal to control each circuit in order to execute the instruction. When the bit judgment instruction of the accumulator according to the present invention is executed, the instruction decoder ae selects Outputs the control signal ACTAL that controls the circuit α9, and also outputs the control signal ACTAL that controls the circuit α9.
(For convenience, R
When the instruction decoder αQ is executed, the instruction decoder αQ outputs the control signals BTAL and TM.
Output B. The control signal TMB is applied to the delay circuit 08 and is delayed until the cycle in which the - instruction is executed, that is, the execution of the RAM bit determination instruction is completed. delay circuit t
The output of tS is applied to the gate circuit section, and the gate circuit al controls the control signal ACTAL output from the instruction decoder Qf9 based on the output of the delay circuit Q8. That is, when the bit judgment instruction of the accumulator is executed alone, the control signal ACTAL is applied to the gate circuit a! However, when the accumulator bit judgment instruction is executed after the RAM bit judgment instruction is executed, the delay circuit Q8
1 output causes the gate circuit section to cut off the control signal ACTAL.

FIG. 4 shows a specific logic circuit example of the selection circuit α, the delay circuit α, and the gate circuit a9, and the selection circuit α51 &
The AND gate (21) to which each bit output ACO to AC7 of the accumulator a3 is applied, and the data bus t
The AND gate ψυ to which each bit DBO-DB7 of tn is applied, and the OR gate (2) to which the outputs of AND gates (2) and (2+) are applied;
The output of 2 is the input AC of the accumulator latch (17)
It is output to LO to ACL7. Delay circuit Q8 is D-FF
The control signal TMB from the instruction decoder ae is applied to the D input terminal, and the clock signal y is output at the end of one machine cycle among the system clocks that control the operation of the microcomputer. A system clock CP4B is applied. Therefore,
The output Q of D-FFQ3) is "1" during a machine cycle in which the RAM bit judgment instruction is executed and the control signal TMB is at the 1" level, and the output Q of the system clock CP
4B falls and becomes 0" during the next machine cycle. The gate circuit al is an AND gate (to), and D
-F F (The output Q of 231 and the control signal ACTAL are input, and the output is applied to the AND gate.
A control signal BTAL is applied from the instruction decoder αe to the AND gate Qυ of the selection circuit (15+).

Therefore, when the bit judgment instruction of the accumulator is executed alone, the control signal AC'TAL of instruction decoder 4 becomes 1", and the AND gate
The data in accumulator 0 is transferred to and stored in the accumulator latch (17), and the bit is judged in the ALU (141).On the other hand, when the RAM bit judgment instruction is executed, Immediate data that specifies the address of RAMH included in this instruction causes data in that RAM (12) to be sent to the data bus circle. At this time, the control signal BTAL
is 11'', so the data of RAMQ2 sent to the data bus (11) is transferred and stored in the accumulator latch α7)K via the AND gate υ.
The control signal TMB which has become 1' is stored in the D-FFI 231K at the last system clock CP4B.

Next, when the accumulator bit judgment instruction is executed, the control signal ACTAL becomes 1'', but since the output power of D-FF (c) is % It Q It due to the execution of the RAM bit judgment instruction, AND Gate C24
) is 0", and the data of the accumulator a3 is not transferred to the accumulator latch (I7). Therefore, the RAM stored in the accumulator latch 0η
(12 data are bit-judged in ALUQ4). In this case, the data stored in the accumulator α is retained without being erased.

(F) Effects of the Invention As described above, according to the present invention, by executing a predetermined instruction immediately before the accumulator bit judgment instruction, R
Bit determination of AM data is performed, and in this case, there is no need for an instruction to save the data in the accumulator, and there is no need for a dedicated instruction for bit determination of RAM data, so the program Since the steps are short (and the total number of instructions is reduced, and the instruction system is simplified), it has the advantage of becoming an easy-to-use microcomputer.

[Brief explanation of drawings]

1 and 2 are block diagrams showing a conventional example, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a partial circuit diagram of the block shown in FIG. 3. ao...data bus, α2...RAM, 031.
...Accumulator, α...ALU, Q5)...
・Selection circuit, (1G+...instruction decoder, (17)...accumulator latch, 餞...
・Delay circuit, al...gate circuit. Applicant Sanyo Electric Co., Ltd. and 1 other agent Patent attorney Shizuo Sano Figure 1 Figure 2

Claims (1)

[Claims] (1) It has a RAM that stores data, an ALU that performs calculations, an accumulator (AC) that stores data, an instruction decoder that decodes instructions and controls each circuit, and a data bus that transfers data, and includes bit judgment instructions. from the instruction decoder in the microcomputer in which the specified bit of the data in the accumulator is determined by the ALU when executed;
a selection circuit that is controlled by a control signal output when the bit judgment instruction is executed or a control signal output when a predetermined instruction is executed, and selects and outputs the data of the accumulator or the data of the data bus; an accumulator latch that temporarily stores data output from the selection circuit and applies it to the ALU; and a delay that delays the control signal output from the instruction decoder when the predetermined instruction is executed until the next instruction is executed. circuit, and a gate circuit that cuts off a control signal output when the bit judgment instruction is executed by the output of the delay circuit, and by executing the bit judgment instruction immediately after the predetermined instruction, the RAM is controlled. A microcomputer, characterized in that designated data is applied to the ALU via the selection circuit and accumulator latch, and a bit determination is made.