JPS6022854A - Digital signal modulating and demodulating system - Google Patents

Abstract

PURPOSE:To decrease the effect of waveform deterioration by applying 2-bit summed up quantity conversion to a signal at a transmission side, and appling the GMSK (Gaussian-filtered Minimum Shift Keying) modulation thereto, transmitting it and allowing the reception side to apply the detected signal with full wave rectification to identify sequentially the integration value between two time slots. CONSTITUTION:An input signal is transmitted through the summed up quantity conversion circuit comprising an exclusive OR circuit 12 and a delay circuit 14 having a delay time of 2T (T is input signal time slot) and through a GMSK modulation circuit 13. The signal is detected by a detection circuit 22 at the reception side and a base band signal is led to a full-wave rectification circuit 23. An output of the rectifier circuit 23 is inputted to integration circuits 24, 25 for 2T period where the integration period is shifted by one time slot period T. The output of the integration circuits 24, 25 is identified by identification circuits 28, 29 at the end of period of integration and outputted to an output terminal 31 through a selection circuit 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a digital communication system. In particular, it relates to a digital signal modulation/demodulation method that is applicable when the received output waveform is degraded due to code amount interference or the like.

[Description of prior art]

On the receiving side of conventional digital communication systems, a method of performing binary identification at intermediate points of data transition points is widely used. However, in order to obtain narrowband signals in digital wireless communications, etc., when a signal whose base band is limited on the transmitting side is detected on the receiving side, the more severe the band limitation is, the wider the waveform on the time axis becomes. Therefore, the detected output is subject to code amount interference, and the error rate characteristics of the reproduced digital information deteriorate.

Figure 1 shows an example of the detection output waveform of a GMSK (Gaussian filtered minimum shift keying) modulated signal, where So is the conventional discrimination value, tl
is the identification Yu/Iminoji. c at identification timing t1
The opening of the detected output waveform is hl. In this waveform, the eye aperture is small, so the noise margin is small, and therefore the error rate of the identification output increases.

[Purpose of the invention]

SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks, it is an object of the present invention to provide a communication system that can obtain good error rate characteristics even when waveform deterioration occurs due to code amount interference or the like.

[Features of the invention]

In the present invention, even if the received output waveform is degraded, by full-wave rectifying the received output waveform and performing integration over two time slots, it can be identified as having a large noise margin at the end of the integration, and the code after the identification is This method focuses on the fact that there is a certain relationship between the data before and after the series, and the sending side
Hino I.'s summation logic conversion is performed, and on the receiving side, the above integration is shifted by one time slot and performed using two circuits, and the integral outputs of the two integral discharge filters are identified, and the reproduced code sequence obtained by III is generated by one time slot. ” tl the selected items for each sort
It is characterized by being a modulated signal.

Note that the present invention is based on an earlier application by the same inventor (Japanese Patent Application No. 1983-
31804).

[Principle of the invention]

The operating principle of the present invention is described in GMSK (Gaussian4i).
1tered old nimuma 5hift Keyin
The case using g) will be explained as an example.

Figure 1 (al is an example of the detected signal eye pattern of G M S H, and in the same figure (bl is a signal obtained by full-wave rectification of the detected signal). In the same figure (al, the eye pattern at the conventional identification timing t1 is The eye aperture is smaller due to code amount interference. On the other hand, the eye aperture at time 2 is smaller than the eye aperture at time t1. Now, it is assumed that identification is performed at time t2, and as shown in FIG.
Let the reproduced code sequences in 2 and 2 be di and di', respectively. It is assumed that the code sequences di and di' are given by -------(11 ----------(2+) for the identification thresholds S1, E2, and s3. In this case, di-di' becomes , the transmission code sequence is shifted from bi, and di takes "1" when bi changes, and takes l-OJ when it does not change.

From this, di-old ■bi1 (■ is exclusive OR)-old-(3)
It can be expressed as

Figure 2 shows the locus of the integrator output when the signal shown in Figure 1 (bl) is integrated over two time slots 2T (T is the data repetition period) with time L1 as the starting point. Identification is performed at the same time as the end of , and the reproduced code sequence that is iMed by this is di''.di
″ shall be identified as given by the following equation.

11---(4) Here, S4 and S5 represent the discrimination darkness values in FIG. Note that the integrator output is immediately discharged after identification to start the next integration.

The table shows the relationship between the code sequence drPl in equation (2) and the code sequence df' in equation (4).

(Hereinafter, unfaithful margins) As we will see, there is a relationship between the code sequences di'' and di': di''=old'■ old-s' -----------(51).Furthermore, the formula ( By substituting equation (3) into 5), di'' = bi ebf-t ------(61) is obtained. The code sequence di'' is the transmission code sequence bi and the code sequence b two time slots before. 11'' if there is a change between t'-2 and rOJ if there is no change.

Therefore, on the transmitting side, the code sequence bi obtained by performing the summation logic conversion of bi=ai of bi-2−−−−−−−−(2 hino 1− given by the force) on the information signal ai is transmitted. In this way, the information signal a on the transmitting side
+ is played on the receiving side.

Since the code sequence d+lF is obtained with a period of every 2T,
Code sequences obtained by identifying the integral outputs of the zu-ru integral lJ station filter that integrates from time t1 to tl → 2T and the integral discharge filter that integrates from time t1+'p to t+43T are selected alternately every 1゛ cycle. Therefore, the information signal a
i is demodulated.

[Explanation based on examples]

FIG. 3 is a block diagram of the system according to the embodiment of the present invention. In the transmitter, a signal to be transmitted is input to an input terminal 11 . This signal is guided to one input of the exclusive OR circuit 12, and its output is input to the transmitting circuit 13. Further, the output of the exclusive OR circuit 12 is branched and connected to the other input of the exclusive OR circuit 12 via a delay circuit 14.

This delay circuit 14 is a circuit that delays the input signal by two times (2T). The output of the transmitting circuit 13 is sent to the transmission line 18 from the transmitting output terminal 15.

In the receiving device, a signal arriving at a receiving input terminal 21 from a transmission path 18 is demodulated into a baseband signal by a receiving circuit 22, and the output thereof is input to a full-wave rectifier circuit 23. The output of the full-wave rectifier circuit 23 is branched and applied to two integration circuits 24 and 25 and a timing signal generation circuit 26. The output of the integration circuit 24 is connected to the identification circuit 28, and the output of the integration circuit 25 is connected to the identification circuit 28.
The output of is connected to the identification circuit 29. Integrating circuit 24.2
Timing signals are supplied to the identification circuits 5 and 29 from the timing signal generation circuit 26, respectively. The outputs of the identification circuits 28 and 29 are connected to the input of a selection circuit 30, and the output of this selection circuit 30 is guided to a reception output terminal 31. This selection circuit 30 is similarly controlled by the output signal of the timing signal generation circuit 2G. A circuit configured to repeat integration, identification, and reset by combining the integrating circuit and the identifying circuit can be obtained as a commercially available integrated circuit as an integrating filter.

To explain the operation of the device configured in this way, the transmitting device receives a signal to be transmitted (code sequence ai
) is input. The signal is subjected to 2-bit summation logic conversion by a delay circuit 14 which provides a delay of 1-2 times, and becomes a transmission signal (code sequence bi).

In the receiving device, an integrating circuit 24 and an integrating circuit 1N152.
', ) repeats the reset operation for 411 minutes at a cycle of 2 times 4 times (2T) of the input signal. Moreover,
The operating periods of the integrating circuit 24 and the integrating circuit 25 are configured to be shifted by one time slot (IT). This situation is not shown in time chart 1 of FIG. That is, FIG. 4A shows the integrating operation of the integrating circuit 24, the discriminating operation of the discriminating circuit 28, and the 1-operation of the integrating circuit 24. Also,
FIG. 4B shows the integration operation of the integration circuit 25, the identification operation of the identification circuit 29, and the reset operation of the integration circuit 25. The selection circuit 30 alternately selects the identification outputs of the identification circuits 28 and 29 at a cycle of 1 time l:'I·(1'F) and sends it to the output terminal 31.

Here, the input baseband signal of the sending circuit 13 is the first baseband signal.
The signal is as shown in the figure (al). This signal is expressed by the above equation (7).
As shown in the figure, the exclusive OR of the input signal code sequence and the transmission signal code sequence 2 bits earlier is performed, resulting in an output signal indicating whether there has been a change or no change in the two code sequences. This is present at the output of the receiving circuit 22 of the receiving device. When this signal is full-wave rectified by the all-S rectifier circuit 23, it becomes the signal shown in FIG.
Integrating over will identify whether the signal has changed over 2T. In other words, if the signal is rl IJ at this 2T time, the output of the integrating circuit is the second
As shown by P in the figure, it becomes a positive value. If the signal is 100'', the output of the integrating circuit will be a negative value as shown by Q in FIG. Furthermore, during this 2T, the signal is "10" or "
2, the output of the integrating circuit becomes as indicated by R in FIG. The reason why multiple trajectories are drawn for each of P, Q, and H in Figure 2 is that, for example, even if the same number is "11", the signal waveform will differ depending on the previous value, and the locus of its integration will differ. show.

In FIG. 2, 84 and S5 indicate the discrimination values of the discrimination circuits 28 and 29. That is, by performing the identification of the -1 binary notation (4), it is possible to identify whether or not there has been a change in the signal over two bits. If this is selected alternately at a period of one time slot, this is exactly the equation (6
), if there is a change from the previous code sequence, it will be "1", and if there is no change, it will be "0". will be reproduced.

In this way, the method of the present invention performs signal identification by performing integration over 2 pins on the receiving side, so it is different from the conventional method.
Compared to the case where identification is performed at a point, the difference in the signal for identification becomes much larger when there is code amount interference, and even if there is code amount interference, demodulation can be performed with a small error rate.

The method of the present invention can be applied not only to the above-mentioned GMSK wireless transmission method and baseband transmission, but also to the TFM method.

〔Effect of the invention〕

As explained above, according to the present invention, even when the signal waveform obtained in the detection output is degraded due to code amount interference etc.
Identification can be performed with a large noise margin. Furthermore, the transmitting device and receiving device of the present invention have the excellent advantage of being realized with a simple circuit configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating signal waveforms in an embodiment of the present invention. FIG. 2 is a diagram showing the output signal waveform of the integrating circuit. FIG. 3 is a circuit diagram of a device according to an embodiment of the present invention. FIG. 4 is an operation time chart of the integrating circuit and the discriminating circuit. 12... Exclusive OR circuit, 13... Transmission circuit, 1
4... Delay circuit, 22... Receiving circuit, 23... Full wave rectifier circuit ~ 24.5... Integrating circuit, 26... Timing signal generation amount Fl&, 28.29... Identification circuit ,
30...Selection circuit. Special 11'F 191 people Nippon Telegraph and Telephone Public Corporation agent Patent attorney Ide Nao Takashit+ b -1+ t1t2tI◆2T -1÷4 Nail 1 Figure '153 side

Claims (1)

[Claims] (11) The transmitting device is provided with means for performing 2-bit summation logic conversion on the binary digital information signal to be transmitted, and the receiving device is provided with means for performing full-wave rectification on the received baseband signal. and means for integrating the output signal of the full-wave rectifying means over two time lofts from approximately the midpoint of the transition point of the signal, identifying the result of the integration, and immediately resetting and repeating the above integration. and a first identification and regeneration circuit configured with a circuit equivalent to the first identification and regeneration circuit, which receives the output signal of the full-wave rectifying means and is l time slot shifted from the first identification and regeneration circuit. and means for alternately selecting the identification outputs of the first identification and regeneration circuit and the second identification and regeneration circuit every time slot. Digital signal modulation/demodulation method.