JPS60226143A - Manufacture of heat dissipating type metallic package - Google Patents

Manufacture of heat dissipating type metallic package

Info

Publication number
JPS60226143A
JPS60226143A JP59083202A JP8320284A JPS60226143A JP S60226143 A JPS60226143 A JP S60226143A JP 59083202 A JP59083202 A JP 59083202A JP 8320284 A JP8320284 A JP 8320284A JP S60226143 A JPS60226143 A JP S60226143A
Authority
JP
Japan
Prior art keywords
holes
heat dissipating
thin plate
hole
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59083202A
Other languages
Japanese (ja)
Inventor
Yukio Saito
斉藤　幸夫
Akira Isono
磯野　彰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59083202A priority Critical patent/JPS60226143A/en
Publication of JPS60226143A publication Critical patent/JPS60226143A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To manufacture the titled package with excellent productivity subject to easy impedance matching in high frequency band as sell as excellent heat dissipation and airtightness by a method wherein input and output terminals of electric signal are positioned on a main surface of a thin plate protruding from the surface after pass through the corresponding hole and the said hole is filled by a glass sealing material. CONSTITUTION:Multiple round through holes 5 and multiple square through holes 6 are perforated into a Kovar made thin sheet 1 and then output and input terminal ends 2 of electric signals are arranged protruding beyond the round holes 5 while a projection 7 for loading a heating chip provided on a heat dissipating metallic body 3 is inserted into the square holes 6. The Kovar made input and output terminals 2 and the Kover made thin sheet 1 are sealed into one body utilizing a glass sealing material 4 increasing the sealing area and extending the leak pass to restric the shape of glass part. The terminals 2 and the projection 7 of heat dissipating body 3 are inserted respectively into the holes of heat dissipating body 3 and the holes 6 of thin sheet 1. Finally the surfaces 8 coming into contact with each other may be brazed into one body.

Description

【発明の詳細な説明】 技術分野 本発明は放熱形金属パッケージの製造方法に関し、特に
・・イブリッドＩＣ（集積回路）であってマイクロ波Ｉ
Ｃ用の高密度性、高精度及び高放熱性を要求される金属
パッケージの製造方法に関するものである。Detailed Description of the Invention Technical Field The present invention relates to a method for manufacturing a heat-dissipating metal package, particularly for hybrid IC (integrated circuit) and microwave I
The present invention relates to a method for manufacturing a metal package for C, which requires high density, high precision, and high heat dissipation.

従来技術 か＼るＩＣ用金属パッケージは、コバーに代表される鉄
ニツケル系金属とガラスとにより構成されているものが
一般的であり、これは生産性に高いこと及び気密性に優
れていることから大量に生産されている。しかし、これ
らはいずれも熱伝導率が小さく、よって高出力チップを
実装してパワートランジスタ等としてデバイス化する場
合は使用できない。Conventional IC metal packages are generally made of iron-nickel metal such as Kobar and glass, which has high productivity and excellent airtightness. It is produced in large quantities from However, all of these have low thermal conductivity, and therefore cannot be used when a high-output chip is mounted to form a device such as a power transistor.

そこで、銅を代表とする金属と前述した鉄ニツケル系合
金とを接合した金属パッケージが多く開発されており、
パッケージにペレット類をろう付後キャップをプールす
る場合の工法として、グロジエクション溶接、シーム溶
接等が一般に用いられているが、溶接性２作業性等から
パッケージの接合部は前述の鉄ニツケル系金属の封着金
属が用いられているのである。Therefore, many metal packages have been developed that bond metals, typically copper, with the aforementioned iron-nickel alloys.
Grozie welding, seam welding, etc. are generally used to pool the cap after brazing pellets to the package, but for reasons of weldability and workability, the joints of the package are made of the aforementioned iron-nickel type. Metal sealing metal is used.

か＼る金属パッケージにおいて、当該封着金属の孔に信
号入出力端子を封着する場合、この孔の内側の形に倣っ
てガラスが充填されて封着されるために、封着ガラスの
形状の任意性に乏しく形状の選定が限定されよってあま
り複雑な形状とすることは困難となっている。これは、
Ｆｅ−Ｎｉ系合金が難削材料であってストレート孔なら
ば容易に加工できるが、段付き等の複雑な形状の孔加工
は困難であることに起因している。こ＼で、特にマイク
ロ波用ＩＣパツクージにあっては、高周波インピーダン
スがこの封着部形状に関係することから、従来パッケー
ジではインピーダンス整合等が自在にできないという欠
点を有している。In such a metal package, when sealing a signal input/output terminal into a hole in the sealing metal, glass is filled and sealed following the shape of the inside of the hole, so the shape of the sealing glass is The selection of shapes is limited due to the lack of arbitrariness, making it difficult to create very complex shapes. this is,
This is because Fe--Ni alloy is a difficult-to-cut material, and although straight holes can be easily machined, it is difficult to machine holes with complicated shapes such as stepped holes. Particularly in the case of microwave IC packages, the high frequency impedance is related to the shape of the sealing part, so conventional packages have the disadvantage that impedance matching cannot be performed freely.

発明の目的　゛ 本発明は、放熱性、気密性に優れかつ高周波域のインピ
ーダンス整合も容易に図れる生産性の良好な放熱形金属
パッケージの製造方法を提供することを目的としている
。OBJECTS OF THE INVENTION An object of the present invention is to provide a method for manufacturing a heat dissipating metal package with excellent heat dissipation, airtightness, and easy impedance matching in a high frequency range, and with good productivity.

発明の構成 本発明による放熱形金属パッケージの製造方法は、電気
信号入出力端子突出用孔及び発熱チップ塔載用の凸部を
有する放熱金属体の当該突部突出用孔が穿設されたＦｅ
−Ｎｉ系合金製薄板を準備し、電気信号入出力端子を、
対応する前記孔を貫通せしめて前記薄板の一主表面上に
突出するように位置させ、ガラス封着部材を当該孔に充
填すると共に前記薄板の地主表面上における当該孔の周
囲にガラス盛りする形状で薄板と入出力端子とを一体封
着し、しかる後に放熱金属体の凸部を対応する前記孔に
嵌合させてこの凸部を前記薄板の一主表面上に突出させ
るようにし、前記薄板の他生表面と放熱金属体の表面と
の接触部を固着してなることを特徴としている。Structure of the Invention The method of manufacturing a heat dissipation type metal package according to the present invention provides a method for manufacturing a heat dissipation type metal package in which a heat dissipation metal body having a protrusion hole for electrical signal input/output terminals and a protrusion for mounting a heat generating chip is formed.
-Prepare a Ni-based alloy thin plate, connect electrical signal input/output terminals,
A shape in which the corresponding hole is penetrated and positioned so as to protrude on one main surface of the thin plate, a glass sealing member is filled into the hole, and glass is arranged around the hole on the main surface of the thin plate. The thin plate and the input/output terminal are integrally sealed together, and then the convex part of the heat dissipating metal body is fitted into the corresponding hole so that the convex part protrudes onto one main surface of the thin plate, and the thin plate It is characterized in that the contact portion between the other surface and the surface of the heat dissipating metal body is fixed.

以下に、本発明を図面を用いて説明する。The present invention will be explained below using the drawings.

第１図は本発明の実施例の製造工程における一過程のパ
ッケージ平面と側面図（半断面図）である。コバー製薄
板１には複数の貫通しだ丸孔５と複数の貫通した角孔６
とが夫々図示の如く穿設されており、丸孔５には電気信
号入出力端子２の先端が突出して配置され、また角孔６
には、放熱用金属体３に設けられた発熱チップ９（第３
図参照）塔載用凸部７が嵌合せしめられる。FIG. 1 is a plan view and a side view (half sectional view) of a package in one step in the manufacturing process of an embodiment of the present invention. The thin plate 1 made of covar has a plurality of penetrating oblong holes 5 and a plurality of penetrating square holes 6.
are bored as shown in the figure, and the tip of the electrical signal input/output terminal 2 is arranged in the round hole 5 so as to protrude, and the square hole 6
, a heat generating chip 9 (third
(See figure) The tower mounting convex portion 7 is fitted.

コバー製入出力端子２とコバー薄板１との一体封着はガ
ラス封着部材４にてなされるものであり、第２図を用い
て詳細に述べるに、先ず孔５，６が穿設された薄板１を
準備し、この薄板１の孔に入出力端子２を貫通して薄板
１の一主表面上に突出する如く位置させる。そして、ガ
ラス封着部材をこの孔５に充填すると共に薄板１の他生
表面８上におけるこの孔５の周囲にガラス盛りする形状
にてこの薄板と入出力端子とを一体封着するものである
。The input/output terminal 2 made of Kovar and the thin Kovar plate 1 are integrally sealed using a glass sealing member 4. To describe this in detail with reference to FIG. 2, holes 5 and 6 are first bored. A thin plate 1 is prepared, and an input/output terminal 2 is inserted into a hole in the thin plate 1 and positioned so as to protrude onto one main surface of the thin plate 1. Then, a glass sealing member is filled into the hole 5 and glass is placed around the hole 5 on the other surface 8 of the thin plate 1 to integrally seal the thin plate and the input/output terminals. .

こうすることにより、封着面積が多くなりリークパスを
長くすることができると共に、従来のようにガラス部の
形状の制約は全くなくなり、封着ガラスの形状が任意に
選定できることになる。By doing so, the sealing area can be increased and the leak path can be lengthened, and there is no restriction on the shape of the glass portion as in the past, and the shape of the sealing glass can be arbitrarily selected.

こうして、入出力端子２が一体に形成されたコバー薄板
１と放熱金属体３とを一体化するのであるが、第１図に
示しだ様に、端子２を放熱体３の孔部に、また放熱体３
の凸部７を薄板１の孔６に夫々嵌合する。そして、互い
の接触する平面（８）同士をろう付けして一体化するこ
とになる。In this way, the thin cover plate 1 on which the input/output terminals 2 are integrally formed and the heat dissipating metal body 3 are integrated, and as shown in FIG. Heat sink 3
The protrusions 7 of are fitted into the holes 6 of the thin plate 1, respectively. Then, the planes (8) that are in contact with each other are brazed to be integrated.

とのコバー薄板１は、プレスやエツチング等の工法によ
り安価にかつ迅速に加工が可能であり、放熱金属体３も
簡単な形状であるので、プレスや切削加工等により容易
に製造できる。更に、ろう付けも平面同士の接合である
ので、容易でありパッケージ全体の製造コストも安価と
なる。The thin cover plate 1 can be processed inexpensively and quickly by methods such as pressing and etching, and the heat dissipating metal body 3 has a simple shape, so it can be easily manufactured by pressing, cutting, etc. Furthermore, since brazing is a joining between planes, it is easy and the manufacturing cost of the entire package is low.

第３図は発熱チップ９や他のベレット類１０を塔載した
場合の断面図であり、放熱金属体３の凸部７上に発熱チ
ップ９が直接塔載され、コバー薄板１の一主表面上に他
のベレット類ＩＯが塔載される。FIG. 3 is a cross-sectional view of the case where the heat generating chip 9 and other pellets 10 are mounted on the tower. Other pellets IO are mounted on top.

従って、発熱チップ９の放熱性は良好となり、更に他の
ベレット類１０の実装も凸部７を基準とすることができ
るので高精度になされ得る。よって、ペレット間の接続
金属１１のボンディング長を極力短くすることができ、
高周波域に特に有効となる。Therefore, the heat dissipation of the heat generating chip 9 is improved, and since the other pellets 10 can be mounted using the convex portion 7 as a reference, high accuracy can be achieved. Therefore, the bonding length of the connecting metal 11 between pellets can be made as short as possible,
Particularly effective in high frequency range.

第４図はペレット類の実装後においてキャップ１２を取
付けだ場合の側面図であり、キャップ１２の接合部１３
はコバーであるので溶接は容易となって気密性が良好と
なっている。更に、高周波域のインピーダンス整合も、
外周金属とガラスの形状とを適宜選定することによって
任意に行える。FIG. 4 is a side view when the cap 12 is attached after mounting pellets, and shows the joint 13 of the cap 12.
Since it is a cover, welding is easy and airtightness is good. Furthermore, impedance matching in the high frequency range
This can be done arbitrarily by appropriately selecting the outer metal and the shape of the glass.

発明の効果 叙上の如く、本発明によれば、気密性、放熱性及び加工
製に優れた金属パッケージのみならず高周波域でのイン
ピーダンス整合も自由に設定自在な金属パッケージが得
られる。Effects of the Invention As described above, according to the present invention, it is possible to obtain not only a metal package with excellent airtightness, heat dissipation, and processing properties, but also a metal package in which impedance matching in a high frequency range can be freely set.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例の製造工程における一過程のパ
ッケージの平面図及び半断面を有する側面図、第２図は
ガラス封着状態を示す断面図、第３図はペレット類搭載
後の断面図、第４図はキャップ接合後の１部断面を含む
側面図である。 主要部分の符号の説明 １・・・封着金属　２・・・電気信号入出力端子３・・
・放熱金属　４・・・ガラス ５．６・・・孔　７・・・凸部 出願人　日本電気株式会社 代理人　弁理士　柳　川　信Fig. 1 is a plan view and a side view with a half cross section of the package at one stage in the manufacturing process of the embodiment of the present invention, Fig. 2 is a sectional view showing the glass sealed state, and Fig. 3 is after loading pellets. The sectional view and FIG. 4 are side views including a partial cross section after the cap is joined. Explanation of symbols of main parts 1...Sealing metal 2...Electric signal input/output terminal 3...
・Heat dissipation metal 4...Glass 5.6...hole 7...convex part Applicant NEC Corporation Agent Patent attorney Shin Yanagawa

Claims (1)

【特許請求の範囲】[Claims] 電気信号入出力端子突出用孔及び発熱チップ塔載用の凸
部を有する放熱金属体の前記凸部突出用孔が穿設された
Ｆｅ−Ｎｉ系合金製薄板を準備し、前記電気信号入出力
端子を、対応する前記孔を貫通せしめて前記薄板の一生
表面上に突出するように位置させ、ガラス封着部材を当
該孔に充填すると共に前記薄板の地主表面上における当
該孔の周囲にガラス盛りする形状で薄板と入出力端子と
を一体封着し、しかる後に前記放熱金属体の凸部を対応
する前記孔に嵌合させてこの凸部を前記薄板の一生表面
上に突出させるようにし、前記薄板の地主表面と前記放
熱金属体の表面との接触部を固着してなることを特徴と
する放熱形金属パンケージの製造方法。A Fe--Ni alloy thin plate having a hole for protruding the electric signal input/output terminal and a protrusion for the protrusion of the heat dissipating metal body having the protrusion for mounting the heat generating chip is prepared, A terminal is passed through the corresponding hole and positioned so as to protrude above the surface of the thin plate, and a glass sealing member is filled into the hole and a glass plate is placed around the hole on the main surface of the thin plate. A thin plate and an input/output terminal are integrally sealed in such a shape, and then the convex portion of the heat dissipating metal body is fitted into the corresponding hole so that the convex portion protrudes above the surface of the thin plate, A method of manufacturing a heat dissipating metal pancage, characterized in that a contact portion between the base surface of the thin plate and the surface of the heat dissipating metal body is fixed.
JP59083202A 1984-04-25 1984-04-25 Manufacture of heat dissipating type metallic package Pending JPS60226143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59083202A JPS60226143A (en) 1984-04-25 1984-04-25 Manufacture of heat dissipating type metallic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59083202A JPS60226143A (en) 1984-04-25 1984-04-25 Manufacture of heat dissipating type metallic package

Publications (1)

Publication Number Publication Date
JPS60226143A true JPS60226143A (en) 1985-11-11

Family

ID=13795737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59083202A Pending JPS60226143A (en) 1984-04-25 1984-04-25 Manufacture of heat dissipating type metallic package

Country Status (1)

Country Link
JP (1) JPS60226143A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0930648A2 (en) * 1998-01-16 1999-07-21 Sumitomo Electric Industries, Ltd. Package for semiconductors, and semiconductor module that employs the package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0930648A2 (en) * 1998-01-16 1999-07-21 Sumitomo Electric Industries, Ltd. Package for semiconductors, and semiconductor module that employs the package
EP0930648A3 (en) * 1998-01-16 2000-04-19 Sumitomo Electric Industries, Ltd. Package for semiconductors, and semiconductor module that employs the package
US6335863B1 (en) 1998-01-16 2002-01-01 Sumitomo Electric Industries, Ltd. Package for semiconductors, and semiconductor module that employs the package

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