JPS60226140A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the accuracy of checking acceptable ratio of through holes by means of increasing the numbers of inspected through holes without increasing the chip area by a method wherein holes for checking acceptability of multilayered wiring connection making use of an element region unused for making a proper logic circuit are provided. CONSTITUTION:Eight each of through holes 1 are provided in a wiring region of a basic cell region 8. If this through hole check pattern is arranged on unused basic cells, a least 200 each of through holes may be formed. When such a through hole check pattern is arranged and connected utilizing 1% of integrated circuit with 10,000 each of basic cells (normally at least around 1% of them are unused), 800 each of through holes may be connected in series by 100 each of unused basic cells to improve the accuracty of checking acceptable ratio of through holes.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a semiconductor integrated circuit device, and particularly to a DA (Des
The present invention relates to a master slice type semiconductor integrated circuit device using ign automation processing.

(Prior Art) In recent years, semiconductor integrated circuit devices have become denser and larger, and the master slicing method is attracting attention as a method for shortening the manufacturing period, especially in random logic circuits.

The master slicing method consists of configuring a logic circuit on a semiconductor substrate by arranging elements that are common to each product type in an array as basic cells, forming them in advance up to a certain stage of the common manufacturing process, and then processing them according to the product type. DA any logical function
Various logical functions are realized by creating contacts or masks after metal wiring through processing.

A master slice type semiconductor integrated circuit device.

In order to support a wide variety of products, the usage status of the basic cells arranged in an array, the wiring area, and the input/output circuit cells arranged around the chip periphery differs depending on the product. That is, the usage rate is less than 100 units.

In other words, there are unused areas in the input/output circuit cells, basic cells, and wiring areas.

In addition, in recent years, with the increase in density of semiconductor integrated circuit devices,
A miniaturized multilayer wiring structure is adopted. In addition to the 8 + 4 board and Al contacts, the multilayer wiring structure is
A contact between L and Al (hereinafter referred to as a through hole) is required. Large-scale integrated circuits are required to have an extremely high yield rate of through-holes because of the large number of through-holes. In order to increase the quality of through holes,
Check the through holes. It is necessary to carry out feed packing in the through hole forming process and to quickly remove defective products.

Conventionally, several dozen through-hole check patterns have been used to check through-holes. However, large-scale integrated circuits may require hundreds of thousands to millions of through-holes, and a through-hole check pattern with only a few dozen through-holes for such a large number is difficult to use. The accuracy in determining pass/fail is low.

FIG. 1 is a plan view of an example of a conventional through-hole exposure check pattern.

In FIG. 1, 1 is a through hole, 2 is a first conductive layer (
3 is the second conductive layer (usually the 2nd A1 layer)
, 4 is a cover, and 6 and 7 are probe pads.

In this pattern, the first conductive layer 2 and the second conductive layer 3
Six through holes are provided to connect the probe pads 6 and 7, and the quality of the through holes can be determined by conducting a continuity test between the probe pads 6 and 7.

Usually, this pattern is placed on the outer periphery or corner of the chip, and a continuity test is performed at the end of the manufacturing process (after completion of the second conductive layer 3). It is thought that six through holes are insufficient to judge the quality of the through holes of the entire chip, and normally, if the space between pads 6 and 7 is open, it can only be determined that the chip is defective. If the number of through holes increases, the resistance component per through hole can also be measured.

However, in order to increase the number of through holes, the overall area of the check pattern shown in FIG. 1 increases, which increases the chip size, which is not a good idea. For this reason, conventionally, a check pattern having at most several dozen through holes was provided in a small area such as a corner. Therefore, through-hole quality judgment 1/[ is insufficient,
The drawback was that the accuracy of the quality of through holes could not be increased.

(Objective of the Invention) The object of the present invention is to eliminate the above-mentioned drawbacks, increase the number of through-hole check patterns without increasing the chip size, and improve the accuracy of determining the through-hole production rate. An object of the present invention is to provide a semiconductor integrated circuit device.

(Structure of the Invention) A semiconductor integrated circuit device of the present invention has elements constituting a logic circuit arranged repeatedly on one main surface of a semiconductor substrate, and required elements among the elements are connected with metal wiring as desired. A master slice type semiconductor integrated circuit device that configures a logic circuit, characterized in that through holes for testing the quality of connections between multilayer wiring are provided in element areas and wiring areas that are not used in the configuration of the logic circuit. configured.

(Example) Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a plan view of an embodiment of the chiku 1 of the present invention.

This embodiment is an example in which a through-hole for testing is provided in the element area of the element area and wiring area that were not used when constructing the logic circuit.

In FIG. 2, 1 is a through hole, 2i[1 conductive layer, and 3 is a second conductive layer. In this embodiment, eight through holes are provided in a wiring area within one basic cell area 8.

By arranging this through-hole check pattern on unused basic cells and connecting 25 basic cells in multiple stages, at least 200 through-holes can be formed. - Utilizing 1% of the integrated circuit which has 10,000 basic cells (usually, at least one cell is unused) and arranging a through-hole check pattern as shown in Figure 2; If connected, 100 unused basic cells will yield 800
This means that through holes are connected in series, and the accuracy of determining the quality of through holes is improved.

FIG. 3 is a plan view of a second embodiment of the invention.

This embodiment is an example in which a through hole for inspection is provided in a wiring area that was not used when constructing a logic circuit.

In FIG. 3, 1 is a through hole, 2 is a first metal layer,
3 is a second metal layer, 9.9' is a basic cell column, 10 is a wiring area, and 11 is an unused wiring area within the wiring area 10. In this embodiment, twelve through holes for inspection are provided in the unused wiring area 11.

In this way, a through-hole check pattern is formed using a large number of unused wiring areas ftLIrf, several hundred to
It can be a check pattern with several dozen through holes. It can also be used in conjunction with a through-hole check pattern that uses unused basic cells. When the number of through holes is on the order of several hundred or more, the resistance component of the through hole becomes measurable in the conductive state, so that it becomes possible to make a determination based on the magnitude of the conductive resistance.

One of the through-hole check patterns may be connected to an empty pad, or a small pad for a probe may be sunk into an unused wiring area or an unused basic cell as shown in FIG. The other may be connected to the substrate tail, to an empty pad, or to a small pad for a probe. Furthermore, automatic placement and wiring can be performed by regarding the through-hole check pattern shown in FIG. 2 as one basic gate.

(Effects of the Invention) As explained in detail above, the present invention provides a through-hole for testing the quality of multilayer wiring connections by utilizing the element area or wiring area that was not used in the original configuration of the logic circuit. This has the effect that the number of through holes to be inspected can be increased without increasing the chip area, and the accuracy of determining the non-defective rate of through holes can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view of an example of a conventional through-hole check pattern, FIG. 2 is a plan view of a first embodiment of the present invention, and FIG. 3 is a plan view of a second embodiment of the present invention. . 1...Through hole, 2...1st metal I
ANj, 3... Second metal layer, 4... Cover, 6, 7... Probe pad, 8...
・Basic cell area, 9.9'...Basic cell column,]
0... Wiring area, 11... Unused wiring area. Agent Patent Attorney Oto Hara Figure 7 Figure Z

Claims (1)

[Claims] A master slice type semiconductor integrated circuit device in which elements constituting a logic circuit are regularly and repeatedly arranged on one principal surface of a semiconductor substrate, and required elements among the elements are connected with metal wiring to constitute a desired logic circuit. 2. A semiconductor integrated circuit device according to claim 1, wherein through-holes for testing the quality of connections between multilayer interconnects are provided in element regions and interconnect regions that are not used in the configuration of the logic circuit.