JPS60225930A - Printer interface in composite function cpu - Google Patents

Abstract

PURPOSE:To increase the function of a composite function CPU even by the limited number of pins, by adding a printer data register to a printer interface in the composite function CPU. CONSTITUTION:A composite function CPU103 outputs a printing data onto data lines DATA0-7, and generates a printer data strobe signal. The printing data is set to a printer data register 104, a control data is set to a control data register 105, and it is outputted as a strobe to a printer. The status for showing whether the printing data can be received or not is read by the composite function CPU103 through a printer busy signal line and the data lines DATA0-7. The number of pins to be used is decreased by using a bi-directional bus line.

Description

[Detailed description of the invention] [Technical field 1 The present invention uses a multifunction CPUk.

[Background Art] A system such as a terminal device or a personal computer that uses a microprocessor (
It consisted of a CPU (hereinafter referred to as a CPU) and its peripheral circuits. By the way, advances in semiconductor technology have made it possible to incorporate some of the peripheral circuits of a CPU into one package with the CPU, and this is now called a multi-function CPU.
It is called.

This multi-function CPU is effective in small-scale systems that directly drive input/output devices, but is not so effective in large-scale systems. In other words, in large-scale systems, the number of bins in the IC package is limited, so a multifunction CPU cannot be used, and a five-function CPU cannot be used.
It uses a combination of U and large-scale peripheral circuits.

Next, an example of a conventional multifunction CPU will be described.

FIG. 1 is a block diagram showing a conventional multifunction CPU and a keyboard, and in particular, its keyboard interface circuit.

In FIG. 1, ° complex function cpui is CPU (28
The multifunction CPU 1 includes a parallel interface (P108255) 3, which is a part of the peripheral circuit. This parallel interface 3 is a type of LSI, and is connected to boat B,
Boat C is used for the keyboard, and Boat A is used for other functions.

That is, port C of the parallel interface 3 is used for keyboard scan data and LED drive data, and port B is used as a keyboard return line input port.

Further, the decoder 4 receives the scan signal KB from the boat C.
The keyboard matrix scan lines KBYO-KBY9 are driven according to O to KB4. Driver IC6 is CAPS from boat C
The LED 7 is driven according to the signal.

The scan line and return line of the keyboard 5 are in contact with each other via key contacts (not shown). In other words, the 10 scan lines become O in sequence, but if a certain scan line is 0 and the contact corresponding to that scan line is pressed, the return line corresponding to that scan line becomes 0. Detects key presses.゛In the above conventional example, the keyboard matrix 5 and the ED driver IC 6 can be directly connected to the multifunction CPU 1, but in this case, the scan data signal (decoder 4
10 pins for output) and return signals KBXO to K
A total of 19 pins are required, including 8 pins for BX7 and 1 pin for caps signal.

However, as mentioned above, keyboard matrix 5 and L
If 19 pins are used when connecting the ED driver IC 6 to the multi-function CPU 1, there is a problem that if it is necessary to add another function, it is difficult to add it due to the limited number of pins. be.

FIG. 6 is a block diagram showing a conventional printer parallel interface, and FIG. 8 is a block diagram showing details of the conventional printer parallel interface.

In FIG. 6, the multifunctional CPUl0I sends printer data to data lines DATAO to DATA7,
The printer data is stored in the printer data register 102.
It outputs a printer data strobe signal to be latched and a strobe signal which is an output request signal for printer data PRDO to PRD7, and inputs a printer busy signal indicating whether printer data can be received.

The data lines DATAO-DATA7 are shared with the signal line of the memory interface.

This is to reduce the number of pins on the package, and the data line DA
A portion of the print data on TAO-DATA7 is set in the printer data register 102, and then outputted to the printer as printer data PRDO-PRD7.

However, even if there is a request to add a control signal, status signal, etc. in addition to the strobe signal and printer busy signal, there is a problem in that the request cannot be met. In other words, there is a problem in that there is a limit to further increasing the functionality of the multifunctional CPU under the limited number of bins.

[Object of the Invention] The present invention has been made by paying attention to the above-mentioned conventional problems, and is aimed at reducing the number of pins as much as possible when connecting a keyboard matrix, LED driver, and bus IC to a multifunction CPLJ. , provides a killboard interface in a multi-function CPU that can add pins with different functions.

The present invention also provides a multi-function CPU that can further increase the functionality of the multi-function CPU under a limited number of bins when a printer is connected to the multi-function CPU by adding a data register. It provides a printer interface for

The present invention further provides a CPLJ interrupt control device that can further expand the functions of a multifunction CPU.

The present invention also provides a multifunction OPU that can be managed on the system to prevent confusion when the functions of the multifunction CPU are further expanded one after another.

SUMMARY OF THE INVENTION] The present invention uses a bidirectional pass line in a multifunction CPU including a CPU and peripheral circuits of the CPU to output a keyboard matrix scan data signal and to output a keyboard matrix return signal. It is something to read.

The present invention also provides a multi-function CPU including a CPU and a peripheral circuit of the CPU, which operates in a level mode in which a level signal related to a printer is used and a printer strobe mode in which the level signal is used as a strobe signal. It has mode designation means for designation.

Furthermore, the present invention secures sufficient pins by making frequent use of pins having other functions by specifying the mode.
Use that pin to control signal level status or complex function C.
It has a register that includes an interrupt request port for viewing the internal state of the PU and a bit that disables or enables the interrupt.

The present invention also provides an LSI 1 [Embodiment of the Invention] in a multifunctional CPLI including a CPU and peripheral circuits of the CPU. FIG.

The complex function CPLJ11 has a CPU (Z80)12 and
It consists of a parallel interface (PI08255) 13, a keyboard scan data output buffer 14, a keyboard scan timing control circuit 15, and a system/interrupt control circuit 16.

The keyboard matrix prohibition signal 25 is for prohibiting the return signal, and the internal bus switch signal 24a is for putting the output signal P CO-P C7 of the port C on the data lines xO to x7. The keyboard strobe signal 24 also transmits the keyboard scan code on the keyboard scan/return data line (XO-X7) 17 to the CAPS/keyboard register 18.
This is the signal to be set to .

Further, the driver IC 19 drives the LED 20.

The decoder 21 scans the keyboard matrix 23 with keyboard scan lines (KBYO to KBY9).
) 22. The system/interrupt control/status signal 26 is a signal that can be newly used due to the expansion of the keyboard interface.

FIG. 4 is a block diagram for selecting the basic keyboard interface function (the function shown in FIG. 1) 31 or the extended keyboard interface function (the function shown in FIG. 2) 32.

Each signal from the basic keyboard interface function 31 and the extended keyboard interface function 32 is -selector 3.
After being selected by 3.34.35, the composite function CP
It is output from U11.

FIG. 5 is a diagram showing the functions of the terminals in each keyboard interface mode (ie, basic mode or extended mode).

Next, the operation of the keyboard interface will be explained.

The CPU (280) 1°2 shown in FIG. 2 first connects the port C of the parallel interface (PI08255) 13
Write the keyboard scan code and LED lighting control data in . Then, as shown in FIG. 3, when the write is performed to port C, the keyboard scan timing control circuit 15 outputs the keyboard matrix prohibition signal 25, so that the keyboard scan/return data line (XO to X7) 17 is output. The return signals (KBXO to KBX7) of port C are inhibited, and the output PC of port C is
O-PC7 is output.

Then, after a predetermined period of time, the keyboard scan timing control circuit 15 outputs the strono signal 24 (becomes HIGH), so the output PCO-PC of port C
7 is output via buffer 14 onto keyboard scan/return data lines (XO-X7) 17.

On the other hand, when the keyboard strobe signal 24 becomes HIGH, the keyboard scan code (4 bits) and LED lighting control data (1 bit) output on the data line (XO to X7) 17 are set in the CAPS/keyboard register 18. be done. When the keyboard mode signal becomes LOW again, the decoder 21 is enabled, so it decodes the keyboard scan code (4 bits) from the keyboard register 18 and drives 10 keyboard scan lines (KBYO to KBY9) 22.

When the operator operates the keyboard, keyboard return data is output on the keyboard return lines KBxO-KBX7, and the keyboard is sent to port B of the parallel interface 13 via the keyboard scan/return data lines (XO to X7) 17. Return data is input.

Based on the keyboard return data read from port B and the keyboard scan code written to port C, the CPU (280) 12 selects the
Detect which key was pressed.

As described above, by providing the extended keyboard interface 32 in addition to the basic keyboard interface 31, system/interrupt control/status signals (9 signals) can be newly used as described below.

(1) Yl: Forced interrupt request signal (cannot be masked) (2)
Y2: Lotus IJ Quest 7. t-signal (used when holding CPUZ80 and performing DMA control) (3) Y3: Bus acknowledge signal (used when holding CPtJZ80 and performing DMA control) (4) Y4: CPU stop Status signal (5) Y5:
External interrupt request signal level 7 (6) Y6: External interrupt request signal level 1 (7) Y7: External island sending request signal level 2 (8) Y8: External interrupt request signal level 3 (9) Y
9: External interrupt request signal level 4 The driver IC 19 uses the output data from the CAPS register 18 to
Controls and drives the lighting of the LED 20 that displays the APS lock status.

As shown in FIG. 4, a keyboard mode signal 36 from the outside is used to switch between outputting a basic keyboard interface signal or an extended keyboard interface signal. In other words,.

When the keyboard mode signal 36 is LOW, the basic keyboard interface signal is selected by the selector 33, 34, 35, and the keyboard mode signal 36 is HIGH.
When H, the extended keyboard interface is selected by selectors 33, 34, 35.

7. For small-scale systems, use the basic keyboard interface mode that allows you to connect the keyboard matrix directly without using peripheral circuitry; for large-scale systems, it is recommended to add some peripheral circuitry. The system/interrupt control/status ramp is also available via an extended keyboard interface as is the case with scale systems. This has the advantage that the same multi-function CPU can be used for both small-scale and large-scale systems.

FIG. 7 is a block diagram showing an embodiment of the present invention,
FIG. 2 is a block diagram illustrating an extended printer parallel interface.

The multifunction CPU 103 has a printer data register 10.
In addition to 4, a control data register 105 and a status boat circuit 106 are added, so that an option I10 interface can also be connected.

FIG. 9 is a block diagram showing an extended printer eraser section provided in the multifunction CPU 103 shown in FIG.

In FIG. 9, the CPU (280) 121 and the address Y coder 1'22 for the printer and option I10 are shown.
, an AND gate 123 that generates a printer data strobe signal, an AND gate 124 that generates a printer control strobe signal, and an AND gate 125 that generates a printer status strobe signal.

FIG. 10 is a block diagram for switching between the basic printer interface (the interface shown in FIG. 8) 133 and the extended printer interface (the interface shown in FIG. 9) 134.

Respective signals from each printer interface 133, 134 are sent to selectors 136, 137.

Therefore, it is selected and output from the multifunction CPU 131. Note that the flip 70 knob 135 is connected to the selector 136.
137 is held.

Next, the operation of the above embodiment will be explained.

First, in FIG. 7, the multifunction CPU 103 outputs print data onto data lines DATAO to DATA7 and generates a printer data strobe signal -. By this printer data strobe signal, print data is set in the printer data register 104, and printer data control data is transferred to the data line DAT.
Output on A O~DATAI to generate a printer control strobe signal.

Also, depending on the printer control strobe signal,
Part of the control data is set in the control data register 105 and output to the printer as a strobe. The printer picks up print data on printer data lines PRDO-PRD7 according to the strobe signal.

On the other hand, the printer outputs a status indicating whether print data can be received or not on the printer visible signal line.

Composite function CPtJ 103 can generate a printer status strobe signal and read the busy status from the printer via status port 106 and data lines DATAO-JDATA7.

Note that the control data register 105 can have a maximum of 8 bits, of which 1 bit is used as a strobe signal for the printer interface, while the other 7 bits can be used for control for the Option I10 interface.

Also, one bit of status port 106 is used as a printer busy signal for the printer interface, while the other seven bits can be used as data or status input ports for the Option I10 interface.

FIG. 9 is a block diagram of the extended printer interface section, and is a diagram showing a generation circuit for each strobe signal.

In FIG. 9, when generating a printer data strobe signal, the CPU (280) 121 generates an I10 address 91 on the address lines ADRO to ADR7.
H (G1 is a hex code), a write strobe signal, and an I10 request signal.

The I10 address decoder 122 decodes the address and generates the 10 address 91H select signal. A
ND gate 123 ANDs the I10 request signal and generates a printer data strobe signal. The printer strobe signal and printer status strobe signal are also generated using the same procedure.

As shown in FIG. 10, a Noritsubu flop 135 holding printer interface selection information allows switching between using basic printer interface signals and extended printer interface signals.

That is, when the printer strobe mode signal that is the output of the flip-flop 135 is LOW, the selector 1
36 selects and outputs the printer strobe signal of the basic printer interface, and selector 13
7km, the printer busy signal is selected and sent to the basic printer interface.

On the other hand, when the printer strobe mode signal is HIGH, the selector 136 selects and outputs the printer control strobe signal of the extended printer interface 134, and the selector 137 selects and outputs the printer status strobe signal.

The flip-flop 135 is connected to the CPU (Z80)1
31 allows for free control of set/reset.

Therefore, in a small-scale system, a basic printer interface mode can be used in which a printer can be connected by simply adding the printer data register 104 shown in FIG.

In addition, in a large-scale system that requires the option ■/°0 interface, an extended printer interface mode can be used by adding a control data register 105 and a status port 106 (shown in FIG. 7). .

FIG. 11 is a diagram showing one embodiment of the present invention, and is a block diagram showing registers and ports that control extended functions of a multifunction CPU.

Figures 12 and 13 are diagrams showing the format of each register and port and the function of each bit.

Next, with reference to FIGS. 11 to 13, the expanded functions of the multifunction CPU will be explained, and the control procedure for the peripheral circuits incorporated in the multifunction CPU will be explained.

The CPU (280) 201 has an internal mode register 207, an internal status board 208, an interrupt control register 209, and an interrupt status board 210, and uses these to control extended functions and peripheral circuits. It is.

The address signals on address lines ADRO to ADR7 output from the CPU (280) 201 are 1-coded by the I10 address decoder 202 and sent to each register/
Select signals for boats 207.208 and 209.210 are output.

AND gates 203-206 generate register/boat strobe signals to set output data on the data line to each register or read status port data onto the data line.

FIG. 12 is shown in FIG. 11. 3 is a diagram showing the functions of each bit in an internal mode register 207. FIG.

Bit O: This bit is input to the O8 terminal (terminal for bit 0) of the clock generator (T6497) for CPLI (280) and specifies the startup time.

Bit 1: MSI terminal (terminal for bit 1) of the clock generator (T6497) for the CPU (280)
bit that is input to stop the output of the clock.

Bit 2: MS2 terminal of clock generator (T6497) for CPU (280) (terminal for bit 2)
Bit input to specify stop mode.

- Here, the clock generator (T6497) is incorporated into the multifunction CPU 201 as one element of the peripheral circuit of the CPU (280).

The CPU (280) 201 can read the ID number of the LSI from the internal status board 208 shown in FIG. Even if the CPU (280) 201 is used as a multi-function CPU, the peripheral circuits to be built in will differ depending on the application, so by changing the ID number, the type of multi-function CPU can be notified to the software. In other words, when the use of an LSI is changed (updated), the I[> number is changed so that the use of that LSI can be reliably identified.

Bit 3 Bit that specifies the Niblinter interface to extended mode.

This corresponds to the printer interface flipflop 135 described in FIG.

Bit 4: Set memory interface mode to SRAM-
Bit to specify 8K.

This bit selects whether to use SRAM-2K or SRAM-8K.

FIG. 13 is a diagram showing the function of each bit in the interrupt control register 209 shown in FIG. 11 and the function of each bit in the open interrupt status port 210.

Since the CPU (280) 201 has only one INT interrupt terminal, the peripheral circuit expands the interrupt request signal to eight levels. That is, the interrupt control register 209 shown in FIG. 11 controls enabling/disabling of the extended interrupt request signal.
The interrupt status port 210 allows the CPU (2
80) 201 can check which extended interrupt request has occurred.

Note that bit 5 is the interrupt status for the printer interface, and bit 6 is the interrupt status for the keyboard interface.

lNT1-INT4. INT7 is an interrupt request from outside the multifunction CPU, and is valid when the keyboard interface is used in the extended mode.

In other words, the interrupt status board has each bit set to "1".
The respective interrupts are enabled only when each bit becomes "1", and each interrupt is disabled only when each bit of the interrupt control register becomes "1".

That is, immediately after the power is turned on, each bit of the interrupt status port becomes "0", and interrupts are not possible. At that time, each bit of the interrupt control register also becomes "0", and interrupts cannot be disabled. After that, if you want to cause an interrupt, you can set each bit of the status port to "1" according to the program, and if you want to disable interrupts, you can set each bit of the control register to "1" according to the program.

The above embodiment may also be provided with an interrupt request boat that looks at the pin state of a signal or the internal state of the CPU, and a bit that disables or enables the interrupt.

[Effect of the invention] The present invention provides a keyboard matrix and an LED driver I.
When connecting C to a multi-function CPU, the number of pins can be reduced as much as possible, and this has the effect that pins having different functions can be added.

The present invention also provides that by adding a printer data register, when a printer is connected to a multifunction CPU, the functionality of the multifunction CPU can be further increased under a limited number of pins. have an effect.

The present invention further has the effect that the functions of the multifunction CPU can be further expanded.

[Brief explanation of the drawing]

FIG. 1 shows a conventional multifunction CPU and keyboard, and in particular, a block diagram showing its basic keyboard interface circuit, and FIG. 2 shows an embodiment of the present invention, a block diagram showing an extended keyboard interface. Fig. 3 is a time chart of the above embodiment, Fig. 4 is a block diagram for selecting the basic keyboard interface 1 ace function or extended keyboard interface function, and Fig. 5 is a time chart of the above embodiment.
6 is a block diagram showing a conventional printer parallel interface, and FIG. 7 is a block diagram showing an embodiment of the present invention, which is an extended printer parallel interface. FIG. 8 is a block diagram showing details of the printer parallel interface shown in FIG.
The figure is a block diagram showing the extended printer interface section provided in the multifunction CPU shown in Fig. 7, and Fig. 10 shows the basic printer interface (the interface shown in Fig. 8@) and the extended printer interface (the interface shown in Fig. 9). A block diagram for switching between
FIG. 11 is a diagram showing one embodiment of the present invention, and is a block diagram showing registers and ports that control extended functions of a multifunction CPU. FIG. 12 is a block diagram showing the formats of internal mode registers and internal status ports, and each FIG. 13 is a diagram showing the formats of the interrupt status port and interrupt control register, and the functions of each bit. 1.11,101,103,121,131゜201・
...Multifunction CPLJ, 13...Parallel interface, 15...Keyboard scan timing control circuit, 23...Keyboard matrix, 24
...Keyboard strobe signal, 24a... Internal bus switch signal, 25... Keyboard matrix prohibition signal, 31... Basic keyboard interface, 32... Extended keyboard interface, 33
．． 34.35...Selector, 36...Keyboard mode signal, 104...Printer data register, 10
5... Control data register, 106... Status port circuit, 132... Printer printer strobe, 133... Basic printer interface, 1
34...Extended printer interface, 135...
Flip-flop, 136.13-7...Selector,
207... Internal mode register, 208...
- Internal status port, 209... Interrupt control register, 210... Interrupt status port. Patent applicant: ASCII Co., Ltd. Figure 1 Figure 4''-11 Figure 2 jlilP!, 16 (Buttocks: East use)

Claims (1)

[Claims] A multifunctional CPU including a CPU and peripheral circuits of this CPU.
In a multi-function CPU, the CPU is characterized by having a mode specifying means for specifying one of a level mode in which a level signal related to the printer is used and a printer strobe mode in which the level signal is used as a strobe signal. printer interface.