JPS6022540B2 - Transmission control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information transmission control method in a unidirectional transmission system.

Here, in order to make the explanation more concrete, a loop transmission system will be used as an example. The basic configuration of the loop transmission system is simple, as shown in FIG. 1, in which one transmission line L is configured in a loop shape.

After calculation, each device P,, P2, consisting of terminals, etc.
, Pm transmit and receive data by jointly using this single loop transmission path L in a time-division manner. Stations C, C2..., Cn consisting of communication control devices are installed at arbitrary positions on the loop transmission path L, and each device P,, P2..., Pm is connected to the nearest station. Connect to. Each station C, C2, . . . , Cn does not necessarily have to be connected to a device. For example, stations C5 and C8 in FIG. C, C
A station to which no equipment is connected, such as 8, functions equivalently to a simple transmission line L. On the loop transmission line L, hit'serial data D circulates in one direction as indicated by the arrow. Each station has a control function that transfers only the data addressed to its own station among the data circulating on the loop transmission path L to the equipment connected to its own station, and a control function that transfers only the data addressed to its own station to the equipment connected to its own station. It has a control function to transfer data onto the loop transmission line L. In conventional stations, when transmitting data to a loop transmission path, several methods are employed to transmit the transmission data to the loop transmission path so as not to overlap with data circulating around the loop transmission path.

Among these methods, shift is the method that allows transmission of data with almost no waiting time, regardless of how busy the loop transmission path is. There is a method called the register or insert method. With this method, the waiting time at the station is less than the time of one block of data during any overload. The hardware configuration of the station is as shown in FIG.
SR, transmission shift register TRS, and switch SW
Consisting of Usually the switch is connected to terminal "100",
On bypass.

Data blocks on the loop transmission path are constantly monitored by the receive shift register RSR. Now, it is assumed that a data block A and a data block B consecutive to block A, as shown in FIG. 3a, are input to the input of the station. At the station switch SW,
Bu.

Assume that when block A is passing through, a transmission request for block ○ is generated, and it is set in the transmission shift register TSR. When the last bit of block A has passed, the switch SW is switched to the terminal 102. In this state, the transmission data block D is sent onto the loop transmission path. In parallel with this, the bits of data block B are sequentially input to the reception shift register RSR. When the transmission of the data block D is completed, the switch SW is switched to the terminal 101, and the data block B, which has been once input to the reception shift register RSR, is subsequently sent out to the loop transmission path. Therefore, the output of the station is such that the transmitted data block D is
Block A is inserted between data blocks A and B.
? The output is in the order of ○ and B. When the receive shift register RSR becomes empty or when the data sent by itself is returned, switch SW to terminal 100'.
Return to initial state. In this method, the last bit of the block being received must be sent before the sending block D can be sent. It has the disadvantage of being long.

The present invention has been made in order to eliminate the drawbacks of the above-mentioned follow-up technology.

This invention provides a simple information transmission control system that can transmit a transmission data block D to a transmission path without waiting for the transmission of the final bit of a block. A feature of the present invention is that if a request for transmission of transmission block D occurs while transmitting bits in the middle of reception data block A, transmission of the remaining bits of reception block A that will be received thereafter is interrupted, and the transmission block The reason is that block D is first transmitted, and then received block A, whose transmission was interrupted, is transmitted from the first bit to the last bit.

First, the principle of the present invention will be explained based on FIGS. 4a, b, and c.

It is now assumed that the station sequentially receives received data blocks X, A, B, and Y shown in FIG. The received data block X is transmitted as is as shown in FIG. While receiving block A with a long block length,
Assume that a request to transmit a transmission data block D occurs at a timing indicated by T in FIG. The part of the received data block A that has already been received, that is, the leading part A' of the block A, is "as shown in c in the same figure, but the remaining part of the data block A that is received from the loop transmission path is The subsequent transmission is interrupted and the transmission data block D is transmitted as shown in c of the figure.After that, all bits of the reception block data A from the first bit to the last bit are transmitted.Then, the reception data block D is transmitted as shown in c. The received blocks B and Y following block A are transmitted as shown in c of the same figure.In addition, when the incomplete data block A' in Fig. 4 is received at the station, there is a known method for removing it. , the explanation is omitted here.

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 5 is an explanatory diagram of an embodiment of the present invention, showing the configuration of station Ci. Based on the data flow within station Ci, station C is divided into five threads as follows. ■Bypass line system Loop transmission line L on the left side, receiver 10, parallel signal line 1
1, selector 20, transmitter 30, right loop transmission line L
A string for transmitting the data received by station Ci as is.

■ Storage system for received data A system for writing received data from the parallel signal line 11 to the received data storage device 44, a processing device 40 for writing the received data to the storage device 44, and a system for storing the address of the storage device 44. A system consisting of address registers 41 and 42 and a received data storage device 44.

■ Received data import system A system for reading out data to be sent to device P from among the received data stored in the received data storage device 44 and transmitting it to device Pi.
0, an address register 71 for storing the read address of the storage device 44, and a processing device 80.

■ Transmission data temporary storage system A system for setting transmission data from the device Pi into the transmission data storage device 82, which stores the address of the processing device 80 and storage device 82 for writing the transmission data in the storage device 82. A system consisting of address registers 81 and 84 for

■ Transmission control system for transmission data and reception data A system corresponding to the main part of the present invention for controlling the transmission of transmission data with priority over reception data, which includes a processing device 60 for controlling transmission, and reception data storage. Address register 7 for storing an address for reading received data from device 44
0. A system consisting of an address register 62 that stores an address for reading out transmission data from a transmission data storage device 82, and a plurality of address registers 83.

○} First, the operation of the bypass line system will be explained.

The receiver 10 receives the received data sent in a time series from the loop transmission line L on the left side of FIG. 5, converts this time series received data into parallel received data in units of 8 bits, The signal is output to a signal line 11 consisting of a main line. The parallel-converted received data is applied to a selector 20 coupled to a signal line 11. The selector 201 is also connected to eight loose signal lines 64 for applying parallel information from a processing bag direct 60, which will be described in detail later. The selector 20 selectively outputs either the data on the signal line 11 or the data on the signal line 64 to the three transmitters based on the signal on the signal line 65 (details will be described later). When the flag signal is 0, data on the signal line 11 is selected, and when the flag signal is 1, data on the signal line 64 is selected. The transmitter 30 converts the parallel data sent via the selector 20 into serial data and sends it to the loop transmission line L on the right side of the figure. Therefore, when the flag signal of the signal line 65 is 0, the received data of the station Ci is bypassed in the order of the signal line 11 and the selector 20, and when the flag signal is 1, the received data is bypassed to the selector 20'.
This will prevent it. To explain the operation of the bypass line system corresponding to a, b, and c of FIG. 4, when the received data x shown in a of FIG. Bypassing of the received data is performed, and data X is transmitted at substantially the same timing as the reception timing of received data X, as shown in FIG. However, when a request to transmit the transmission data D occurs at the timing indicated by T in FIG. 5B while the reception data A is being received, the flag signal changes from 0 to 1, and the bypass of the reception data is prevented. This state persists until the transmission of received data block B is completed. When the transmission of received data B is completed, the flag signal returns to 0 again, allowing bypassing of the received data, and bypassing of received data Y is performed.
'2} Next, the operation of the received data temporary storage system will be explained using FIGS. 5 to 8 a, b, c, and ().

The processing unit 4 performs processing according to the flow chart shown in FIG. The processing device 40 includes, although not shown,
A storage device (used only by the processed bag counterfeit 40) is provided inside. The received data storage device 44 has a storage capacity sufficient to prevent overflow due to the amount of data flowing through the transmission path L (the minimum address is RARmim and the maximum address is RARmax).

)have. As shown in FIG. 8a, when the power of station Ci is turned on at start 401, processing device 4 executes processes 402 to 404 for setting initial values, and initializes registers 42, 41, and GAR 50. Perform value settings. The address registers 42 and 41 include the processing device 40
The minimum address value RARmin of the internally stored received data storage device 44 is set. On the other hand, address register group OAR50 consisting of a plurality of address registers is cleared to 0. At this time, the value of GAR50 cleared to 0 is outside the range of RARmin to RMRmax, and the value of GAR50 that is cleared to 0 is outside the range of RARmin to RMRmax.
It can be clearly distinguished from values in the range n to RARmax. The value RAR of the address register 42 is the data block that is currently being received when data is currently being received, the data block that is to be received when it is not currently being received, and a flag (hereinafter referred to as Indicates the address of the received data storage area (referred to as the transmission flag signal). The value RAR2 of the address register 41 is the parallel line 1
This is an address for specifying a storage area when writing the 8-bit data currently being sent from the receiver 10 via 1 to the storage device 44. Next, process 405 is executed, and the value RAR2 of register turtle 1 is converted to the value RAR of register 42.
Add 1 to . Immediately after turning on the power, be sure to use RAR.
2<RARmax, but as data is repeatedly received, the final address RAR of the received data storage device 44
Since up to max is used, the determination is made by executing process 406.

As a result, if RAR2>RARmax, processing 407 turns on the overflow flag of the storage area inside the processing device 40 and sets RAR,41=RARmin.
Execute 408. Furthermore, a process 409 is executed to update the contents of the RAR 241 by 1, and processes 410 to 412 similar to processes 406 to 408 are executed. In this way,
For each data block, storage areas for storing the transmission flag and the data length of the data block are secured at address addresses RAR, , RAR, 11, respectively. Subsequently, it is determined whether data is being applied to the signal line 11 by executing process 413. If there is no received data, a signal 45 (hereinafter referred to as
This is called a pidgey signal) is reset by process 414. On the other hand, if there is received data, the pidsy signal 45 is set to 1 by the process 415 shown in FIG. 8b. As shown in FIG. 7 outside the received data, the first byte indicates the source address. The source address is the one to which the source station adds its own address. Return to Figure 8 and continue the explanation. In process 416, it is determined whether the first byte of the received data is the th station address. First, the case of self-transmitted data will be explained. In the case of self-issued bond data, processes 427 to 430
Execute. That is, when executing processes 428 and 429, the signal 46 (hereinafter referred to as "selector switching request signal") to the processing device 60 is set to 1. If the selector switching request signal is 1, the processing device 60' is forced to The flag signal 65 is set to 1. Through processes 428 and 429,
The received data is read (inputted but not written to the storage device) until the data block is completed. This process 4
27 to 429 have the following meanings when explained from another perspective. Since the transmission system is on a loop, the transmitted data must be erased somewhere on the loop.
Therefore, in this method, the data is erased when it goes around the loop and returns to the source station. but,
When executing process 427, the address field (7th
If the selector 20 has selected the signal 11 by the flag signal 65, the first byte shown in the example shown in the figure is transmitted to the loop again. Next, in process 416,
If the received data is not self-issued bond data, processing 417 and subsequent steps are executed.

First, in process 417, the value RA of the address register 41
The 8-bit received data is written to the address of the received data storage device 44 indicated by R2. Next, the value RAR2 of the address register 41 is increased by 1, and if the value exceeds the final address RARmax of the received data storage device 44, processes 420 and 421 are executed, and the over flag is turned ON.
The initial value RARmi is set to the value RAR2 of the address register 41.
Set n. If not, the process moves to step 422. Next, when the first byte is received, it is determined in process 422 whether data block reception is complete. First, in the case of receiving data of only 1 byte, processes 423 to 426 are executed, and the address register 41 value RAR2 is decreased by 1. Also, if processes 420 and 421 are being executed, process 42
Execute 5,426 to return to the state immediately before data reception,
Returning to process 413, the process waits until the next received data arrives. This process is for removing the received data of only the address part that is transmitted on the loop again when the above-mentioned processes 427 to 428 are executed. Next, the case of normal received data will be explained.

If the result of determination in process 422 is that reception of the data block is not complete, the process continues to process 431 shown in FIG. 8c. Processing 43
By executing steps 1 to 437, the received data is written into the received data storage device 44 one after another. The updating of the address register, etc. is the same as the method already described, and will therefore be omitted. When the reception of the data block is completed, the presence or absence of the flag signal 65, which is the output of the processing device 60, is checked in step 43.
8, and if the flag signal 65 is 1, 1 is set, and if it is 0, 0 (hereinafter referred to as the transmission flag) is set to the corresponding address of the received data storage device 44 indicated by the value RAR of the address register 42. Execute 439 or 440. Next, the received data length is determined by executing process 441 and turning on and off the overflow flag in process 442.
, 443. Next, process 4
44, the contents of the address register RAR, 42 are converted into an address register group GA consisting of a plurality of address registers.
R50 free register (register in reset state)
Set to . Subsequently, processes 445 to 447 are executed,
The value RAR of the address register 42 is increased by 1, and the data length obtained earlier is written to the corresponding address of the received data storage device 44 indicated by the increased value RAR. Finally, processes 449 and 450 are executed, and the address register RA
R, 42, initialize the overflow flag, process 40
The process returns to step 5 and begins receiving processing for the next received data block.
Through such a series of processes, for example, if the received data A (A, ~) shown in FIG. As shown in the figure, the transmission flag is at address 1, and the transmission flag is at address 2.
Data length in address (data length in this case is 7), 3 to 9
Data A, ~A7 are written to the address. Note that the data length is defined as one plow it. '3' Next, the operation of the received data acquisition system will be explained based on FIG.

The process shown in FIG. 9 is executed by the processing device 8 shown in FIG. 5, and is a process for sending the received data written in the received data storage device 44 to the device Pi. When the station Ci is powered on, the processing device 80 starts 8.
01, and register initialization processing 802 to 805 is executed. Processes 802 to 804 are initialization for transmission processing to be described later, and processes 802 and 803 set the minimum address TARmin of the transmission data storage device 82 in the address registers 84 and 81. Processing 804 executes 0 clearing of a plurality of address register groups OAT83. Process 805 initializes the address register 71 for reading the contents of the received data storage device 44. Next, processing 806 is executed to determine whether the same value as the value MAR of the address register 71 is stored in the address register group GAR50. Value M of address register 71
If there is the same value as AR, processing 807 causes register 7 to be set.
A value MAR of 1 is written to the storage area Top in the processing device 80. Further, a transmission flag is stored at the address of the received data storage device 44 indicated by the value MAR, and a process 808 is executed to write the transmission flag into the processing device storage area FLG. Next, the value MAR is updated by processes 809 to 811. At this time, the received data storage device 4
If the value MAR exceeds the maximum address RARmax of 4, the 1-bit register FF set by the processing unit 60
Depending on the contents of steps 1 and 90, processing 813 or 814 is executed. The operations of the 1-bit registers FF1, 90, FF2, and 91 executed by processes 812 to 814 are as follows. This indicates which of the processing devices 80 and 60 first continued up to the last address RARmax of the received data storage device 44, and if the processing device 80 made the request first, FFI: 0, FF2=1, processing device If 60 made the decision first, FFI=1 and FF2=0. Furthermore, the processing device that reads the data later sets FFI=0 and FF2=0. Next, processing 815 is executed to calculate the byte length of the data book of the received data in the storage area CNT in the processing device 80.
Write to. Next, execute processes 816 to 821 to update address register 7 1-value MAR, FF1, 90, FF
2. Process 822 while performing the set and reset operations of 91.
, 823, and reads the data from the received data storage device 44 and sends it to the device P. This series of processing
Processes 824 and 825 are executed and repeated until CNT=0, and reading of the received data block is completed. When the reading of the data block is completed, “Processing 826 to 8
31 is executed, the value MAR of the address register 71 is updated, and FF1, 90, FF2, 91 are set and reset, and then FLG is determined in process 832. FL
G indicates the transmission flag of the received data block, and F
When it is LGio, it indicates erasure of the corresponding data, and when it is 1, it indicates that erasure of the corresponding data is prohibited. Therefore, when FLG=0, "process 834 is executed to clear the contents of the storage area Top in the processing device 80 and the registers in the address register group GAR50 that have the same contents. With the above, the reading of a series of data blocks is completed. Then, the process returns to step 806 to read the next received data block. {4} Next, the operation of the transmission data temporary storage system will be explained based on FIGS. 10a and 10b.

The processing shown in FIGS. 10a and 10b is executed in the processing device 80. While executing the received data import system mentioned above,
Due to the interruption of the transmission request signal 75 from the device Pi, processing 8
Entering the start of 50. First, the values of the address registers 81 and 84 that are initialized in advance, TAR2, TAR,
Accordingly, processing 851 is executed. Next, similar to the address register processing of the received data storage system, processes 852 to 854 are performed.
, 855 to 858, and address register TAR2
81 update twice. At this time, when the value TAR2 of the address register 81 exceeds the final address TARmax of the transmission data storage device 82, the overflow flag of the storage area in the processing device 80 is turned ON. Next, process 8
59 is executed to determine whether the transmission data is released to the signal line 76 or not. If there is no transmission data, processing 859 is repeated until transmission data is prepared. Processing 859
If the transmission data is present, processing 860 is executed and the transmission data is written to the address address of the transmission data storage device 82 indicated by the value nAR2 of the address register 81. Subsequently, the update of AR2 of the address register 81 is executed by processes 861 to 864, and the process is repeated from process 859 until the data block is completed by executing process 865. Next, process 866 is executed, and depending on whether the overflow flag is turned ON or OFF, process 867 or 868 is executed.
Execute and calculate the data length. Execute process 869~
The value TAR of the address register 84 is set in an empty register of the plural address register group GAT83. Next, the value AR of the address register 84 is updated by executing processes 870 to 872, and the data length obtained earlier is written to the address address of the transmission data storage device 82 indicated by the value TAR of the address register 84. Finally, processes 874 to 875 are executed, the value TAR2 is set to the value TAR of the register 84, and the overflow flag is set to FF, thereby ending the operation of Ichigo.

By executing the process 876, the operation of the processing device 80 returns to the received data acquisition type process at the time when the interruption of the transmission request signal 75 occurs and continues. {51 Finally, the operation of the transmission control system for transmitting data and receiving data will be explained with reference to FIGS. 11a to 11h'.

The series of processes shown in FIG. 11 a to h are executed by six processing devices. In process 601, when the power of station Ci is turned on, the value QTR of the reception data storage device 44 and the address register 70 for sending is stored in the transmission data storage device 82.
The value PTR of the offer address register 62 is executed by initial setting processes 602 and 603 using the respective minimum address values RARmin and TARmin. Next, processing 604 is executed to determine whether the address register group 83 has the same value as the value PTR of the register 62. This process 604 is a process for determining whether transmission data is written in the transmission data storage device 82. If there is no transmission data, the process moves to execution of process 622 shown in FIG. 11c. On the other hand, if there is transmission data, the address register 62
The value PTR is written in the storage area TopA in the processing device 60. Subsequently, processes 606 to 608 are executed to update the value PTR of the address register 62. Next, the data length of the transmission data is retrieved from the transmission data storage device 82 and written into the area CNTA of the storage device within the processing device 60. Here, the selector 20 and the processor 4 output 1 as the flag signal 65. Next, processing 611-6
Steps 614 and 615 of updating the value PTR of the address register 62 by executing step 13, reading the transmission data from the transmission data storage device 82, and outputting the read transmission data to the signal line 64 in order to send it to the selector 20. , after updating CNTA by executing process 616, repeating until CNTA=river by executing process 617. Now you can send the send data block. Next, address register 6
The value PTR of 2 is updated through processes 618 to 620, and finally, the value of the register in the address register group GAT83 that matches the value of TOPA corresponding to the data that has been transmitted is reset to 0. Subsequently, the process returns to step 604 and processes the next transmission data. Next, a description will be given of a process when there is no data to be transmitted after executing process 604.

First, the process 622 shown in FIG. 11c is executed to determine whether the plurality of address register groups GAR50 are all in the reset state, that is, the received data block. It is determined whether there are any data blocks to be transmitted again.
If the received data needs to be retransmitted, the process moves to step 626 shown in FIG. 11d. If there is no received data to be retransmitted, processes 623 to 625 are executed, and the process returns to process 604.
By executing the process 623, the processing device 40 outputs the selector switching request signal 4 that outputs the self-transmitted data block to the received signal.
6 is set to 1, and if the selector switching request signal 46 is 1, the flag signal reset process 625 is not executed. Similarly, processing 624 is executed to generate a busy signal 4 which the processing device 40 is receiving.
5 is determined. If the busy signal is set to 1, reset processing 6 of the flag signal 65
Do not execute 25. Under the above condition, that is, when the selector switching request signal 46 and the busy signal 45 are both 0, the flag signal is reset. As a result, the selector 2 switches to connect the signal line 11 to the transmitter 30.
Next, the operation will be described in the case where the address of the received data storage device 44 in which received data is written is set in a plurality of address register group OARs 50.

First, the process 626 shown in FIG.
Write to TA. Next, a plurality of address register groups GA
Among the registers of R50, the value QT of address register 70
It is determined whether there is a register having the same value as R. If yes, the process moves to process 635 shown in FIG. 11e. If there is no value, the value QT of the address register 70 is changed by executing the process 634.
R matches the contents of STA (QTR is RARmin
to RARmax), or by executing process 627, a register having the same value as the value QTR of the address register 70 is added to the address register group GAR50.
Processes 628 to 633 are executed until it is determined that the condition exists. Processes 628 to 630 process the value QT of the address register 70.
This is R update processing. Further, the value QTR of the address register 70 is the final address RAR of the received data storage device 44.
When mAx is exceeded, processes 631 to 633 are executed. When processing 631 is executed and FF2 and FF91 are set to 1, the value MAR of the address register 71 is changed to the value QTR of the address register 70 by the operation of the processing device 80.
This indicates that the RARmax has been exceeded earlier, and FF2 is reset to 0 according to the previously described rules. On the other hand, F
If F2=0, set FFI:1. Here, in process 634, if the value QTR of the address register 70 matches STA, the process returns to process 604. Next, a case will be described in which the start address of the received data written in the received data storage device 44 is found.

Process 635 for reading data in the received data storage device 44 whose address is indicated by the value QTR in the address register 70
is executed, processing 636 is executed, and it is determined whether the data is flagged data or not. Flagged data indicates that the flag signal 65 was set while the processing device 40 was writing received data to the received data storage device 44, and is data that requires retransmission. Data that requires resending (data with a flag) has a value of 1 after execution of process 635. At this time, after executing process 636, the process moves to ``process 643.'' Meanwhile, ``
If the data is not flagged data, processes 637 to 642 are executed, the value QTR of the address register 70 is updated, the 1-bit registers FF1 and FF2 are set or reset, and the process returns to process 604. Next, the flagged data (
The operation when there is data to be retransmitted will be explained.

First, process 643 is executed to write the value QTR of the address register 70 to the area TOPB of the storage device in the processing device 68.

In the same manner as the method described above, processes 644 to 649 are executed to update the value QTR of the address register 70 and operate the 1-bit registers FF1 and FF2. Subsequently, the data length is retrieved from the reception data storage device 44 whose address is indicated by the value QTR of the address register 70, and the data length is inputted to the processing device 60.
Write to internal storage area CNTB. Next, processing 651-6
56 and ``Update value QTR of address register 70,''
Manipulate 1-bit registers FF1 and FF2, and execute processes 657 and 658 to obtain the value QT of address register T8.
Data is retrieved from the received data storage device 44, where R indicates an address, and the data is transmitted from the transmitter 3 via the selector 20, and this process is repeated until ~CNTB:0 is reached by executing processes 659 and 660. When the data transmission is completed, processes 661 to 666 are executed,
The value QTR of the address register TO is updated and the 1-bit registers FF1 and FF2 are operated. Subsequently, by executing processes 667 to 66, processes 678 and 6
Select one of the 7 turtle treatments. Step 670: Step 670. Step 671 clears the register with the same content as TOPB in the address register group 50. Step 671 clears the data (flag) in the received data storage device 44 to which TOPB indicates the address. . In other words, processing 67 is equivalent to clearing the received data that has been retransmitted, and processing 671 is equivalent to clearing the received data that has been retransmitted, but
The data has not been completely captured by the processing device 80,
This is a process that erases only the flag and allows the processing device 80 to clear the received data after completing the capture. First, in order to execute process 670, "Through execution of processes 667 to 669, if FF2=1, FFI:FF2=0 and QTRSMAR. In the first case, the operation of the processing pupil 80 Now address register 71 value MAR
This indicates that the final address of the received data storage device 4 has been reached before the value QTR of the address register 70 accompanying the operation of the processing device 60, and the device P
This indicates that the import into I was performed first. Also the second
The case is also the same as the first case, but in this case, the value QTR of the address register 70, the value QTR of the address register 7
This is a case where both values MAR of 1 have not reached the final address of the received data storage device 44. On the other hand, “Processing 6
In order to execute 71, if FFI=1, "FFI=
This is the case when FF2=0 and QTR>MAR. this is,
This is simply contrary to the state when processing 670 is executed. By executing the above process, the re-reception of the received data is completed for each data block, and the process returns to the process 604.
Finally, “Selector activation request signal 4 in processing device 60
The operation related to 6 will be explained based on FIG.

If the processing device 60 detects self-transmitted data and outputs the selector switching request signal 46 while the processing device 60 is executing the processing shown in FIGS. An interrupt occurs and processing 690 in FIG.
The flag signal 65 is set, and the process returns to the execution of the processes shown in FIGS. 11a to 11h when the interrupt occurs. Processing 69
Setting the flag signal 65 by executing 0 will not cause any state change if the flag signal 65 is already being set. On the other hand, if it is in the reset state, the flag signal 65
is set to 1. Further, the flag signal 65 is reset only when the process 626 of FIG. 11c is executed. This completes the explanation of all operations related to station Ci, but each processing device 40, 60,
The illustration of the 80-inch memory card is omitted.

These storage devices in processing devices are composed of two types: nonvolatile memory whose contents are not erased even when the power is turned off, and rewritable memory. The former records the minimum address value, final address value, etc. of the received data storage device 44 and the transmitted data storage device 82 used for initial setting of each address register. The latter stores the data length used in each processing process. As explained above, according to the present invention, it is possible to transmit a block of transmission data without waiting until the last bit of the data block being received is transmitted, and at the same time Data blocks can also be reliably transmitted to the loop transmission path, and the received data blocks can be easily received without complex processing.

[Brief explanation of the drawing]

Figure 1 is a diagram of a loop transmission system, Figure 2 is a configuration diagram of a subordinate station, Figure 3 is an explanatory diagram of a conventional transmission method,
FIG. 4 is a diagram explaining the principle of the transmission method of the present invention, FIG. 5 is a configuration diagram of a station for implementing the method of the present invention, and FIG.
The figure is a diagram showing an example of how received data is stored in the received data storage layer, FIG. 7 is a diagram showing an example of data flowing through the transmission path L, and FIG. 8 a? b, c, and d are flow diagrams of processing for writing received data into a received data storage device;
Figures a and b are flowcharts of the process of writing the transmission data sent from the device into the transmission data storage device, and Figure 11a
~h is a flow diagram of the process of transmitting data from the transmission data storage device and the reception data storage device via the selector and the transmitter, and FIG. A flow diagram of signal switching processing is shown. 10: receiver, 20: selector, 30: transmitter, 40:
Processing device, 44: Reception data storage device, 60: Processing device, 80: Processing device, 82: Transmission data storage device. Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 8 a Figure Ship Figure 8 b Figure 8 c Figure 8 d Figure 9 a Figure 9 b Figure 10 a Figure 10 Figure b Figure 11e Figure 11a Figure 11b Figure 11c Figure 11d Figure 11f Figure 11g Figure 11h Figure 12

Claims (1)

[Scope of Claims] 1. In a method of transmitting data blocks between a plurality of devices connected to a transmission path, means for transmitting and storing all bits of each received data block in each device to another device. and means for interrupting the transfer of the received data block and transmitting the transmitted data block when a request to transmit its own transmitting data block occurs during the transfer of the received data block, and interrupting the transfer after the transmission is completed. 1. A transmission control system comprising means for retransferring all bits of the received data block from the first bit to the last bit. 2. In a method of transmitting data blocks between a plurality of devices connected to a unidirectional transmission path, each of the devices has means for transferring and storing the received data block from the upstream device to the downstream side. and means for interrupting the transfer of the reception data block and transmitting the transmission data block when a transmission request for the transmission data block is generated from the device during the transfer of the reception data block; A transmission control system characterized by comprising means for retransmitting all bits of the temporarily stored received data block whose transmission was interrupted after completion of the transmission. 3. The transmission control method according to item 1 or 2, in which interrupt priorities are equal between each device. 4. The transmission control method according to one item selected from the first to third items, in which the identification codes indicating the beginning and end of the data block are the same.