JPS60224256A - Composite type semiconductor device - Google Patents

Composite type semiconductor device

Info

Publication number
JPS60224256A
JPS60224256A JP59080564A JP8056484A JPS60224256A JP S60224256 A JPS60224256 A JP S60224256A JP 59080564 A JP59080564 A JP 59080564A JP 8056484 A JP8056484 A JP 8056484A JP S60224256 A JPS60224256 A JP S60224256A
Authority
JP
Japan
Prior art keywords
terminals
frame
terminal
gate
thyristor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59080564A
Other languages
Japanese (ja)
Inventor
Toshihiro Nakajima
中嶋　利廣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59080564A priority Critical patent/JPS60224256A/en
Publication of JPS60224256A publication Critical patent/JPS60224256A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/01—Chemical elements
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To obtain a highly reliable composite type thyristor array without generating discharge in a high withstanding voltage element, by making the distances between the outermost terminals and their neighboring terminals wider than the distances between other terminals. CONSTITUTION:The distances between outermost terminals, e.g., anode terminals 12 and 13 and their neiboring terminals are made wider than the distances between other terminals. For example, a thyristor chip 3 is die-bonded to the diebonding parts of anode terminals 12 and 13 of a frame by a conducting material such as solder 5. Then, a gate part 5 of the thyristor chip 3 and two gate-terminals 6 and 7 of the frame and a cathode part 8 of the thyristor chip 3 and a cathode terminal 9 of the frame are wire-bonded by a conducting material such as Al wires 10, respectively. Then, the two anode terminals 12 and 13 of the frame, the cathode terminal 9 of the frame, parts of the gate terminals 6 and 7 of the frame, the thyristor chip 3 and the Al wires 10 are molded by sealing resin such as an epoxy resin 11.

Description

【発明の詳細な説明】 ［発明の技術分野］ この発明は、複合形半導体装置、特にその端、子閤距離
にかかる改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a composite semiconductor device, and particularly to improvements in the edge and contact distances thereof.

近年、複合形半導体装置は市場の要求により小形化へと
進んでおり、今後数多く出現すると思われる。特に中小
容量サイリスタやパワートランジスタの分野で脚光を浴
びており、数へから数１０Ａの領域で大幅に増大するも
のと予測される。In recent years, composite semiconductor devices have been becoming smaller due to market demands, and it is expected that many more will appear in the future. In particular, it is attracting attention in the field of small and medium capacitance thyristors and power transistors, and it is predicted that the number will increase significantly from several tens of amperes.

第１図は従来の複合形半導体装ばのうち特に複合形サイ
リスタアレイを示すものである。以下、この従来の複合
形サイリスタアレイの製造方法を説明しながら構造を明
らかにする。FIG. 1 particularly shows a composite thyristor array among conventional composite semiconductor devices. Hereinafter, the structure of this conventional composite thyristor array will be clarified while explaining the manufacturing method.

外部端子を持つフレームの図において左右端の７ノード
端子１．２のダイポンド部にサイリスタチップ３をはん
だ４等の導電材料によりダイポンドする。次に、サイリ
スタチップ３のゲート部５とフレームの２つのゲート端
子６．７およびサイリスタチップ３のカソード部８とフ
レームのカソード端子９をそれぞれＡｉワイヤ１０等の
導電材料でワイヤポンドする。そして、フレームの２つ
のアノード端子１．２、フレームのカソード端子９、フ
レームの２つのゲート端子６．７の一部、サイリスタチ
ップ３、およびＡＡワイヤをエポキシ樹脂１１等の封止
樹脂によりモールドする。さらに、フレームのタイバを
切断することにより複合形サイリスタアレイが得られる
。前記複合形サイリスタアレイの各端子は等ピッチ間隔
で配設され、２つのサイリスタに共通のカソード端子９
が中央に設けられ、該カソード端子９の両外側に２つの
ゲート端子６，７、さらに該ゲート端子６゜７の両外側
に２つのアノード端子１，２が配設されている。In the diagram of the frame having external terminals, the thyristor chip 3 is die-bonded to the die-pound portion of the seven node terminals 1.2 at the left and right ends using a conductive material such as solder 4. Next, the gate portion 5 of the thyristor chip 3 and the two gate terminals 6.7 of the frame, and the cathode portion 8 of the thyristor chip 3 and the cathode terminal 9 of the frame are wire bonded with conductive materials such as Ai wires 10, respectively. Then, the two anode terminals 1.2 of the frame, the cathode terminal 9 of the frame, parts of the two gate terminals 6.7 of the frame, the thyristor chip 3, and the AA wire are molded with a sealing resin such as epoxy resin 11. . Furthermore, a composite thyristor array can be obtained by cutting the tie bars of the frame. The terminals of the composite thyristor array are arranged at equal pitch intervals, and a cathode terminal 9 common to the two thyristors is provided.
is provided at the center, two gate terminals 6 and 7 are provided on both sides of the cathode terminal 9, and two anode terminals 1 and 2 are provided on both sides of the gate terminal 6.

しかしながら、上記従来の複合形サイリスタでは、各端
子位値に起因して、絶縁耐力の面で信頼度に欠ける重大
な欠点があった。すなわち、各端子間の距離が狭い場合
、高耐圧素子ではゲート端子とアノード端子間で放電を
発生し、信頼性に欠けるという欠点があった。However, the above-mentioned conventional composite thyristor has a serious drawback of lacking reliability in terms of dielectric strength due to the potential value of each terminal. That is, when the distance between each terminal is narrow, a high voltage element has the drawback that discharge occurs between the gate terminal and the anode terminal, resulting in a lack of reliability.

［発明の概要］ この発明はかかる欠点を除去する目的でなされたもので
、最外端子とその隣にある端子との間の距離を他の端子
間の距離よりも広くすることに、より、高耐圧素子にお
いても、放電を発生させることなく信頼性の高い複合形
サイリスタアレイを提供するものである。[Summary of the Invention] This invention was made for the purpose of eliminating such drawbacks, and by making the distance between the outermost terminal and the terminal next to it wider than the distance between the other terminals, The present invention provides a highly reliable composite thyristor array that does not generate discharge even in high-voltage devices.

［発明実施例］ 第２図はこの発明の一実施例を示す平面図である。最外
端子を７ノード端子１２．１３とする。[Embodiment of the Invention] FIG. 2 is a plan view showing an embodiment of the invention. The outermost terminal is the 7 node terminal 12.13.

ここで、該アノード端子１２．１３とその隣にある端子
との間の距離を他の端子間の距離よりも広くすることが
特徴となっている。そのＩＪ造方法は従来のものと同様
であるが、繰返すと、フレームのアノード端子１２．１
３のダイボンド部にサイリスタチップ３をはんだ４等の
導電材料によりダイボンドする。次に、サイリスタチッ
プ３のゲート部５とフレームの２つのゲート端子６．７
およびサイリスタチップ３のカソード部８とフレームの
カソード端子９をそれぞれＡｌｌワイヤ１０等の導電材
料でワイヤボンドする。そして、フレームの２つのアノ
ード端子１２．１３．フレームのカソード端子９、フレ
ームのゲート端子６，７の一部、サイリスタチップ３お
よびＡｌワイヤ１０をエポキシ樹脂１１等の封止樹脂（
よりモールドする。さらに、フレームのタイバを切断す
ることにより、複合形サイリスタアレイが得られる。Here, the feature is that the distance between the anode terminal 12, 13 and the terminal next to it is wider than the distance between the other terminals. The IJ construction method is the same as the conventional one, but to repeat, the anode terminal 12.1 of the frame
The thyristor chip 3 is die-bonded to the die-bonding portion 3 using a conductive material such as solder 4. Next, the gate part 5 of the thyristor chip 3 and the two gate terminals 6.7 of the frame
The cathode portion 8 of the thyristor chip 3 and the cathode terminal 9 of the frame are wire-bonded using a conductive material such as an All wire 10, respectively. and the two anode terminals 12.13. of the frame. The cathode terminal 9 of the frame, part of the gate terminals 6 and 7 of the frame, the thyristor chip 3 and the Al wire 10 are sealed with a sealing resin such as an epoxy resin 11 (
More molded. Furthermore, by cutting the tie bars of the frame, a composite thyristor array can be obtained.

本発明にかかる複合形サイリスタアレイに＾電圧を印加
させるとゲート端子とアノード端子間に高電圧がかかる
が、本発明によれば、ゲート端子とアノード端子間の距
離が他の端子間の距離より広くされているため、高耐圧
素子においても放電が生じることがない。When a voltage is applied to the composite thyristor array according to the present invention, a high voltage is applied between the gate terminal and the anode terminal, but according to the present invention, the distance between the gate terminal and the anode terminal is longer than the distance between other terminals. Since the width is wide, no discharge occurs even in high voltage elements.

なお、上記実施例では端子の数が５つのものを示したが
６つ以上でもよい。In the above embodiment, the number of terminals is five, but the number of terminals may be six or more.

さらに、上記実施例では、複合形サイリスタアレイを示
したが複合形トライアックアレイ、複合形トランジスタ
アレイであっても同様のことが言える。Further, in the above embodiment, a composite thyristor array is shown, but the same applies to a composite triac array or a composite transistor array.

［発明の効果］ 以上のように、本発明によれば、最外端子とその隣にあ
る端子との間の距離が他の端子間距離よりも広くされて
いるため、高耐圧素子に含まれる端子であって高耐圧が
要求されるものを最外端、子とすることにより、放電を
防止でき、信頼性の高い複合形半導体装置を得ることが
できる。[Effects of the Invention] As described above, according to the present invention, since the distance between the outermost terminal and the terminal next to it is wider than the distance between other terminals, By using the terminals that require a high withstand voltage as the outermost terminals, discharge can be prevented and a highly reliable composite semiconductor device can be obtained.

なお本効果を生せしめる方法としては全端子間の距離を
広くする方法はあるが、これではパッケージが大きくな
る欠点を生じる。本発明によれば°かかる欠点を除去し
、パッケージを小形化しつつ、放電防止をする効果があ
る。Although there is a method of increasing the distance between all the terminals to achieve this effect, this method has the disadvantage of increasing the size of the package. According to the present invention, such drawbacks can be eliminated, the package can be made smaller, and discharge can be prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の複合形サイリスタアレイの平面図、第２
図は本発明の複合形サイリスタアレイの平面図である。 図において、６．７．９は端子、１２は最外端子（アノ
ード端子）、１３は最外端子（７ノード端子）を示す。 なお、各図中同一符号は同一または相当部分を示すもの
とする。 代理人　大　岩　増　雄Figure 1 is a plan view of a conventional composite thyristor array;
The figure is a plan view of a composite thyristor array of the present invention. In the figure, 6.7.9 indicates the terminal, 12 indicates the outermost terminal (anode terminal), and 13 indicates the outermost terminal (7 node terminal). Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa

Claims (2)

【特許請求の範囲】[Claims] （１）　５個以上の端子が配列された複合形半導体装置
において、最外端子とその隣にある端子との間の距離を
他の端子間の距離よりも広くしたことを特徴とする複合
形半導体装Ｉｌ！。(1) A composite type semiconductor device in which five or more terminals are arranged, in which the distance between the outermost terminal and the terminal next to it is wider than the distance between the other terminals. Semiconductor equipment! . （２）　前記複合形半導体装置は複合形サイリスタアレ
イであって、最外端子をアノード端子とした特許請求の
範囲第１項記載の複合形半導体装置。(2) The composite semiconductor device according to claim 1, wherein the composite semiconductor device is a composite thyristor array, and the outermost terminal is an anode terminal.
JP59080564A 1984-04-20 1984-04-20 Composite type semiconductor device Pending JPS60224256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59080564A JPS60224256A (en) 1984-04-20 1984-04-20 Composite type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59080564A JPS60224256A (en) 1984-04-20 1984-04-20 Composite type semiconductor device

Publications (1)

Publication Number Publication Date
JPS60224256A true JPS60224256A (en) 1985-11-08

Family

ID=13721830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59080564A Pending JPS60224256A (en) 1984-04-20 1984-04-20 Composite type semiconductor device

Country Status (1)

Country Link
JP (1) JPS60224256A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1460689A3 (en) * 2003-03-17 2005-07-20 Analog Power Intellectual Properties Limited Electronic devices
US7148562B2 (en) 2003-10-31 2006-12-12 Mitsubishi Denki Kabushiki Kaisha Power semiconductor device and power semiconductor module
JP2015115464A (en) * 2013-12-11 2015-06-22 トヨタ自動車株式会社 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1460689A3 (en) * 2003-03-17 2005-07-20 Analog Power Intellectual Properties Limited Electronic devices
US6963140B2 (en) 2003-03-17 2005-11-08 Analog Power Intellectual Properties Transistor having multiple gate pads
US7148562B2 (en) 2003-10-31 2006-12-12 Mitsubishi Denki Kabushiki Kaisha Power semiconductor device and power semiconductor module
JP2015115464A (en) * 2013-12-11 2015-06-22 トヨタ自動車株式会社 Semiconductor device

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