JPS60224195A - Static semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the generation of a software error under normal environmental condition by providing a resistor satisfying a prescribed condition between a drain node and a gate node of a memory cell in a static semiconductor memory comprising 6 CMOS transistors (TRs). CONSTITUTION:A resistor RG is connected between a drain node A comprising an n-channel MOSTRQ1 and a p-channel Q3 forming a memory cell section and a gate node B in pairs with the node A. Similarly, a resistor RG is connected between a drain node A comprising an n-channel Q2 and a p-channel Q4 and a gate node B in pairs with the node A. In deciding the value of the resistor RG to satisfy the condition expressed in Equation I, a potential change DELTAV2 of the node A caused by an electric charge Q0 of the node B caused by an ionizing radiation particle in a drain depletion layer of the TR in an off state expressed in Equation II is <=1.05V, where Q0/CT is assumed as 30V and the generation of the software error under normal environmental condition is prevented. In Equation, RT is a larger on-resistance between n-channel and p-channel TRs and CG, CT are capacitances of gate and drain nodes.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a 0MO8 (complementary 1t, MOS) transistor) 6
Static shop R consisting of transistor memory cell section
The present invention relates to a static semiconductor memory constituting an AM (random access memory), and particularly to a static semiconductor memory that takes measures against soft errors.

(Prior Art) Malfunctions of semiconductor memories caused by ionizing radiation particles are generally called soft errors or single event upsets, and are a well-known phenomenon. Soft errors are caused by charges generated inside semiconductor memory by ionizing radiation particles.
It is caused by gathering at a specific node inside the semiconductor memory and changing the potential at that node.

Next, the mechanism by which ionizing radiation particles cause soft errors in conventional OCMO86) transistor static memory cells will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a conventionally used transistor static memory cell (0MO86).

In the figure, Qt and Qt are n-channel #MO8$ for cells.
/transistor (hereinafter referred to as nMO8T), Q, ,Q
4 is a p-channel NIO S synristor for cells (
Hereinafter, it will be referred to as PMO8T. ), and Qs + Qa is IIMO8T for the transfer gate.

pMO8TQs and nMO8TQ, or on, nMO8
TQl , I) MO8T Q4 , n MO8T
Consider the case where Qs −Qa is off.

Now, when ionizing radiation particles pass through the depletion layer of the drain junction of nMO8TQs, electron-hole pairs are generated in the depletion layer. Since a reverse bias is applied to the drain junction of nMO8T Q, a negative charge Q is induced at the drain node A. If the capacitance of drain node A is C, the potential of drain node A decreases by Q/C. This drop in potential can be seen on nMO8T! and is transmitted to the gate of pMO8TQ4. If Q/C is close to the power supply voltage VCC, then I) MO8TQ.

There is a possibility that the inverter composed of nMO8TQ* and nMO8TQ is inverted, and the entire memory cell is inverted.

Similarly, nMO8TQ and pMO8T Q4 are turned on,
nMO8TQ*, I) MO8TQ8. , nMO8TQs
, Qa is off, ionizing radiation particles incident on the drain junction depletion layer of I) MO8TQ may induce a positive charge in the drain node, causing the memory cell to invert.

As described above, the conventional 0MO8,6) transistor static memory cell has the problem of causing soft errors.

(Object of the Invention) An object of the present invention is to provide a static semiconductor memory that does not cause soft errors in natural environments by solving the above-mentioned problems.

(Structure of the Invention) The static semiconductor memory of the present invention is 0MO86)
In a static semiconductor memory including a transistor memory cell section, a resistor is provided between a drain node of the memory cell section and a gate paired with the drain node, and the resistance value of the resistor is RG.

The capacitance value of the gate node is CG, the capacitance value of the drain node is CT, the n-channel MO connected to the drain node8) On-resistance of the transistor and the p-channel MO
8) RT the larger resistance value of the on-resistance of the transistor.
When 10 CT RT≦CGR.

It consists of the following relationship.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram of a transistor static memory (0MO86) according to an embodiment of the present invention.

In this embodiment, in a static semiconductor memory consisting of a 0M086) transistor memory cell section, a resistor RG is provided between a drain node of the memory cell section and a gate node B paired with the drain node; The resistance value is RG s The capacitance value of the gate node B is CGs The capacitance value of the drain node is 01 The on-resistance of nMO8TQ1°Qt connected to the drain node A and pMO8TQ
s, and the larger resistance value of the on-resistances of Q4 is defined as RT, and the relationship is 10CTRT≦CGRG.

Next, it will be explained that the above object is achieved by this embodiment.

The ionizing radiation particles with the greatest ionizing power in the natural environment are iron ions contained in galactic cosmic rays.

Iron ions can generate up to 0.3 pc/μm of electron-hole pairs in silicon crystals. Among the electron-hole pairs generated by iron ions, only the charges generated in the drain depletion layer of the off-state transistor cause soft errors.

This is because charges generated outside the depletion layer gradually flow into the drain node by diffusion, and are released from the on-state transistor to the power supply or ground line without changing the potential of the drain node, and are released into the memory cell circuit. This is because it does not affect the operation.

On the other hand, the charges generated in the depletion layer can escape from the transistor that is in the on state quickly enough.
Since they are concentrated at the drain node due to the electric field, they change the potential of the drain node, which in turn causes soft errors. Charges similarly collect in the drain depletion layer of a transistor in the on state, but the width of the depletion layer is much narrower than in the off state, so this effect can be ignored.

Now, there is a charge Q at the drain node of the off-state transistor.
Consider the case where o gathers. An equivalent circuit diagram of a conventional memory cell in this case is shown in FIG. Node 1 is off, drain node I GT is the capacitance value of drain node 1, R
T is the on-resistance value of the transistor in the on-state,
Node 2 is the gate node of the pair of transistors, and node ICG is the capacitance value of gate node 2.

When charge Qo is collected at drain node 1 by ionizing radiation particles, the potential of drain node 1 is Qo/(CG+CT
) only changes. In a conventional memory cell, gate node 2
The potential of will also change by the same amount.

Now, in the case of iron ions, they pass through a drain depletion layer of about 10 μm at maximum in a general memory cell, so the charge Q
The maximum value of o is approximately 3 pC.

Since CG+CT is about 0.19F in the case of a general memory cell, the potential of the drain node 1 changes by about 30V at maximum.

FIG. 4 is an equivalent circuit diagram of this embodiment shown in FIG. 2.

A charge of maximum Qo is generated at drain node 1 by iron ions, but due to resistance RG, it is immediately transferred to gate node 2.
I can't get it across. In the case of a general memory cell, CT≧CG, and in the present invention, RGC,≧l0RTCT, so it can be approximated as lRr<R,1, and the potential change Δ■ at the drain node 1 is expressed by the following equation. , potential change ΔV at gate node 2
, is expressed by the following formula.

According to the present invention, if l0CTRT≦CGR, then the following holds true. Now, assuming that iron ions are incident, QO/CT=30V
Then, a CMOS memory cell that operates at a power supply voltage of ΔV≦1.05V and al, 2■ or more will not cause a soft error.

Generally, diffused resistors or polycrystalline silicon resistors are used as resistors in semiconductor devices, but diffused resistors are unsuitable because they collect charges from ionizing radiation particles in their own depletion layer, causing soft errors. It is. Therefore, it is preferable to use polycrystalline silicon for the resistor R.

(Effects of the Invention) As described above, according to the present invention, due to the above structure, a static board conductor memory that does not cause soft errors in a natural environment containing iron ions in galactic cosmic rays. can be provided. The present invention enables CMOS to be used in equipment onboard satellites where soft errors caused by cosmic rays are a concern.
Static semiconductor memory can be used, and its effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional 0MO86) transistor static memory cell, FIG. 2 is a circuit diagram of a 0MO86) transistor static memory cell according to an embodiment of the present invention, and FIGS. 3 and 4 are the same as those shown in FIG. and the equivalent circuit diagram in Figure 2. 1...Drain node, 2...Group/gate node,
A...Drain node, B...Gate node, cG-old...Gate node capacitance, G...Drain node capacitance, RG...Resistance, RT・・・・・・
・On resistance, Q, , Qt, Qa, Qa...
...N-channel MO8 transistor, Qs s Q
4...p channel MO8) transistor, vcc
······power supply. Agent Patent Attorney Susumu Uchihara S Figure 3 Figure 4

Claims (2)

[Claims] (1) In a static semiconductor memory consisting of a 0MO86 transistor memory cell section, a resistor is provided between a drain node of the memory cell section and a gate node paired with the drain node, and the resistance value of the resistor is set to RG, The capacitance value of the gate node is CG, the capacitance value of the drain node is 0, and the larger of the on-resistance of the n-channel MO8) transistor and the on-resistance of the p-channel MO8) transistor connected to the drain node. When the value is RT, 10 CT RT≦ Ca R. A static semiconductor memory patented for having the following relationship. (2) A static semiconductor memory according to claim (1), wherein a polycrystalline silicon resistor is used as a resistor provided between a drain node of the memory cell portion and a gate node paired with the drain node.