JPS60224190A - Dynamic ram - Google Patents

Abstract

PURPOSE:To attain high speed operation with simple constitution by bringing a data input buffer into the operating state with a row system timing signal to attain writing from the low level of a write enable signal to a memory array. CONSTITUTION:A data input buffer DIB is brought into the operating state by a high level row system timing signal phiin formed and generated from a timing signal generating circuit TG by using the low level of a row address storobe signal RAS' at the operation of read modified writing. Then after the end of the read, when a write enable signal WE' is brought into a low level, the memory arran is written immediately via complementary data lines CDL and CDL'. Thus, the delay time for data fetch is eliminated in comparison with the case that the buffer DIB is brought into the operating state after the signal WE' reaches a low level, and the writing after the read is quickened with simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a dynamic RAM (random access memory), and relates to, for example, a technique effective for use in a dynamic RAM including read-modify-write functions. It is something.

[Background technology]

The read-modify-write function is known as one of the operations in dynamic RAM (Nikkei Electronics Magazine, April 18, 1977 issue, pages 65-7).
(See 3).

In the conventional dynamic RAM, the data buffer is brought into operation by a timing signal generated by the write enable signal WE, so for example, the above-mentioned read/modify/write operations result in wasted operating time. This has been revealed through research by the inventor of the present application. In other words, in a read/modify/write operation, the read operation is performed first, so even though the memory array is already in the selected state, the data cover sofa does not operate until the write enable signal -Wl becomes low level. Since the write signal is taken in after entering the state, this operation time is added to the write cycle.

[Purpose of the invention]

An object of the present invention is to provide a dynamic RAM with a simple configuration and high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by keeping the data input cover sofa in an operating state by a row-related timing signal, writing to the memory array can be performed immediately by the low level of the write enable signal.

〔Example〕

FIG. 1 shows a circuit diagram of a main part of an embodiment of a dynamic RAM according to the present invention.

In the example circuit shown in the figure, an n-channel MO3FE
I G F E T (I n5ula
tedGate Field Effect Tran
This will be explained using the example ``sister''.

A 1-bit memory cell MC, as shown as a representative, has an information storage capacitor Cs and an address selection M
The information of logic "1" and "0" is stored in the form of whether the capacitor Cs has a charge or not.To read the information, turn on the MO3FETQm and connect the capacitor C3 to the common data line. DL and senses how the potential of the data line DL changes depending on the amount of charge accumulated in the capacitor Cs.

The memory cells MC are formed small and the common data line D
Since many memory cells are connected to L to form a highly integrated and large capacity memory matrix, the relationship between the capacitor Cs and the stray capacitance Co (not shown) of the common data line DL is Cs/Co. The ratio becomes a very small value.

Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs becomes a very small signal. A dummy cell DC is provided as a reference for detecting such a minute signal. This dummy cell DC is manufactured under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is half that of the capacitor C8 of the memory cell MC. Capacitor Cd, prior to addressing,
It is charged to ground potential by MOSFETQd'.

As described above, since the capacitance value of the capacitor Cd is set to about half that of the capacitor Cs, a reference voltage equal to half of the read signal from the memory cell MC is formed.

In the figure, SA is a sense amplifier that expands the difference in potential change caused by the addressing into a sensing period determined by a timing signal (sense amplifier control signal) φPal+φpa2 (its operation will be described later).
, its input/output nodes are coupled to a pair of parallelly arranged complementary data lines DL, DL. complementary data line DL,
The number of memory cells coupled to DL is made equal to increase detection accuracy, and one dummy cell is coupled to each of complementary data lines DL, DL. Furthermore, each memory cell MC is coupled at the intersection between one word line WL and one of the complementary data lines.

Since each word line WL crosses both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component crosses both data line pairs DL.
, DL, and are canceled by the differential sense amplifier SA.

In the above addressing, complementary data lines DL, D
When a memory cell MC coupled to one of the data lines L is selected, one of the pair of dummy word lines DWL, DWL is selected so that the dummy cell DC is always coupled to the other data line.

The sense amplifier SA has a pair of cross-wired MO3
FETQ1. Q2, and due to these positive feedback effects,
A minute signal appearing on complementary data lines DL, DL is differentially amplified. This positive feedback operation is performed in two stages, and the MO3FE has relatively low conductance characteristics.
It starts at the same time that TQ7 starts to conduct by a relatively early timing signal φpa1, and based on the potential difference given to the complementary data lines DL and DL by addressing, the higher data line potential is at a slow speed, and the lower one is at a faster speed. Together, the gap widens and declines. At this time, at the timing when the above-mentioned difference potential becomes large to a certain extent, the MO3FETQB is changed to a relatively large conductance characteristic.
is made conductive by the timing signal φpa2, so the potential of the lower data line drops rapidly. Like this 2
By operating the sense amplifier SA in stages, the drop in the higher potential is prevented.

In this way, when the lower potential drops below the threshold voltage of the cross-coupled MO3FET, the positive feedback operation ends, and the higher potential drops below the power supply voltage Vcc (while remaining at a potential higher than the above threshold voltage). , the lower potential eventually reaches the ground potential (GV).

During the above-mentioned addressing, the stored information in the memory cell MC, which was once about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, if the high level drops to a certain level or more with respect to the power supply voltage Vcc, a malfunction will occur where the data will be read as logic "0" while reading and rewriting are repeated several times. An active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR has the function of selectively boosting only high level signals to the potential of power supply voltage Vcc without having any effect on low level signals.

A data line pair DL, which is shown as a representative in the figure,
DL is MO3FETQ that constitutes column switch CW
3. Common complementary data line pair CDL, CDL via Q4
connected to. Similar MO3FETQ5. It is connected to the common complementary data line pair CDL, CDL via Q6. This common complementary data line pair CDL, CDL is connected to an input terminal of a data output buffer DOB including an output amplifier and an output terminal of a data manual buffer DIB.

Although not particularly limited, in this embodiment, the data manual buffer DIB includes an input buffer sofa that is activated by the timing signal φin, and a drive circuit that receives this output signal and forms drive signals for the common complementary data lines CDL and CDL. , and a gate circuit that transmits the drive output signal to the common complementary data lines CDL, CDL using a timing signal (not shown) generated by the write enable signal WE.

The row decoder and column decoder R, C-DCR receive the internal complementary address signal processed and formed by the address buffer ADB, form one word line, a dummy word line, and a column switch selection signal, and select a memory cell and a dummy cell. In other words, the address buffer ADB performs addressing of the applied external address signal AX.
It processes and forms an internal complementary address signal according to O to AXi, and sends the internal complementary address signal to the row decoder R-DCH in synchronization with the timing signal φar formed by the row address strobe signal RAS.

Row decoder R-DCR receives this internal complementary address signal and word line selection timing signal φX, and selects a predetermined word line and dummy word line. Also,
Address buffer ADB processes and forms an internal complementary address signal according to applied external address signals AYO to AYi, and sends it to column decoding C-DCH in synchronization with timing signal φaC formed by column address strobe signal CAS. Send. Column decoder C-
The DCR receives this internal complementary address signal and the data line selection timing signal φy to perform a data line selection operation.

Although not particularly limited, the timing generation circuit TG receives a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE supplied from external terminals, respectively, and forms various timing signals necessary for the above operations.

Next, read-modify-write operations in the dynamic RAM of this embodiment will be explained with reference to the timing chart shown in FIG.

The supplied address signal Ai is taken in as a row-related address signal AX (AXO to AXi) in synchronization with a change in the low level of the row address strobe signal RAS, and is transmitted to the row address decoder R-DCH.

As a result, the selection operation of the word line designated by the address signal At is performed.

Then, the next supplied address signal At is taken in as a column-related address signal AY (AYO-AYi) in synchronization with the column address strobe signal CAS.
It is transmitted to the column address decoder C-DCR.

As a result, a data line selection operation is performed.

In this embodiment, the row address strobe signal RA
The row system timing signal formed by the low level of S, for example, the timing signal φin formed by the same timing signal as the operation timing signal φar of the row address buffer, is set to high level to operate the input circuit forming the data manual buffer DIB. It is left in the condition.

The read signal of the memory cell selected by the addressing of the memory array MARY is sent out from the output terminal when the data output buffer DOB is activated by the high level of the timing signal φop formed by the column timing signal. After such a read operation is completed, when the write enable signal WE is set to low level, the drive signal already formed by the data manual buffer DIR is set to the common level by the timing signal formed together with the low level of the write enable signal WE. Since the data is transmitted to the complementary data lines CDL, CDL, writing is immediately performed to the memory cell in the selected state.

〔effect〕

(1) The data manual buffer is brought into operation by the row timing signal, and the already formed write drive signal can be immediately written into the memory array in synchronization with the low level of the write enable signal. Therefore, compared to a system in which the data manual buffer starts operating and takes in the data after the write enable signal becomes low level, the signal delay time in the data manual buffer can be substantially eliminated. This provides the effect that the write operation after the read operation can be performed at high speed.

(2) According to (1) above, multiple memory arrays MAR
In nibble mode, byte mode, etc., in which multiple bits of signals are written or read serially to each memory array by addressing Y at the same time, multiple bits can be written or read with one address setting. Since the delay time described above can be eliminated by applying the present invention, the overall operation time can be significantly shortened, or in other words, the operation can be made faster.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the timing signal φin that puts the data manual buffer into the operating state does not necessarily have to be the same timing signal as the row address signal, and at the latest, when the write enable signal WE in the read/modify/write operation becomes low level, the timing signal φin is already in the write drive state. Any device may be used as long as it utilizes a row-related timing signal that can form a . Furthermore, the specific circuit configurations of peripheral circuits such as address buffers, address decoders, data buffers, data output buffers, etc. can take various embodiments.

[Application field]

The present invention provides a dynamic RAM that multiplexes and supplies external address signals using an address strobe signal.
widely available.

[Brief explanation of the drawing]

FIG. 1 shows a dyna<7 type RAM to which the present invention is applied.
FIG. 2 is a circuit diagram showing one embodiment, and a timing chart showing an example of the read/modify/write operation. MC: memory cell, DC: dummy cell, CW: column switch, SA: sense amplifier, AR: active restore circuit, RC-DCR: row/column decoder, ADH: address buffer, DOB: data Output buffer, DI attorney Akio Takahashi 1st Figure R Hu 74 and ρ~Δ4

Claims (1)

[Claims] 1. A row address buffer and a column address buffer that take in multiplexed and supplied external address signals in synchronization with an address strobe signal, and a row address strobe signal that takes in a write signal supplied from a data input terminal. 1. A dynamic RAM comprising: an input buffer that captures the captured write signal in synchronization with a row timing signal formed based on the write enable signal; and a write circuit that transmits the captured write signal to a memory array in synchronization with a write enable signal. 2. The dynamic RAM according to claim 1, wherein the data manual buffer is activated by the same timing signal as the row address buffer. 3. The write circuit includes a drive circuit that receives the output signal of the input cover sofa that is activated by the row timing signal and forms a drive signal for the common complementary data line, and a drive circuit that synchronizes this drive signal with the write enable signal. 3. The dynamic RAM according to claim 1, further comprising a gate circuit for transmitting the data to the common complementary data line of the memory array.