JPS60222895A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

(Field to which the invention pertains) The present invention relates to a highly functional image display device that is easy to control and capable of high-speed reading and writing. (Prior Art) Fig. 1 shows the configuration of a conventional image display device, in which 1 is a flat display panel of mXn pixels using liquid crystal as a display element, row selection lines DR] to DRm and column selection. line DCI
-DCn is wired. 2 is a row selection circuit which selects one of the row selection lines DRI to DRrr+ and outputs 3V.
i column selection holding circuit; 4 is a B-bit data bus; The column selection holding circuit 3 transfers the display button signals of B bits 1 and 1 from the data bus 4 to the column selection lines DCI-1)Cn of 8
When transmitted to the book, the signal is held and the column selection lines DCI to DCn are activated or inactivated by that signal. Display pile 1 is line selection # One line D from DRI to DRm
When Ri is selected by the row selection circuit 2, the display element DS at the intersection of the row selection line DRi and column selection lines DCI to DCm
However, the signals are displayed in a bright or dark form depending on the activation/deactivation of the column selection lines DC1 to DCm. 5 is a frame memory of mXn bits, which is the same as the number of pixels of the display panel 1; 6 is a row selection circuit; 7 is a column selection circuit; information in the frame memory 5 is stored in B bits by the row selection circuit 6 and column selection circuit 7; Information is read and written one by one. 8 is a control circuit, 9°10, 11.
12 is a control line, and the selection circuits 2, 3, 6, 7 are connected to control lines 9, 10, . . . by the control circuit 8. II, +2, 13 is an external input bus. The display button signal displayed on the display panel 1 of this display device is stored in the frame memory 5. Therefore, in order to display a display button on the display panel 1, the row selection circuit 2 sequentially selects the row selection lines DRI to DRm, and sequentially reads out the display button signals corresponding to the rows from the frame memory 5 and connects them to the data bus. 4 to the column selection holding circuit 3. Normally, in order for the display panel 1 to look normal without flickering or flickering, one screen (one frame) of the display panel 1 is regularly displayed (refreshed) at least 30 times per second, as described above. There is a need. Display panel IK To display a new display button, the frame memory 5 is sent from the external input bus 13 via the control circuit 8.
It is necessary to write a display bang signal to the display. However, as mentioned above, since the display button signal is constantly transferred from the frame memory 5 to the display panel 1 via the data bus 4, the display button information from the external human power bus +3 is transferred to the frame memory 5 in a time-sharing manner. Write to ・2 required, control is multiple
It has the disadvantage that it takes a long time to complete the process. Figure 2 shows an active matrix circuit that has been adopted in large-area display panels in recent years, and 20 is a MOS
) transistor, 21 is a display element. ”; The drawbacks described above also apply when this circuit is used. That is, the MOS transistor 2o is turned ON when the row selection line DRi connected to the gate GK is selected, and transmits a display signal to the source S via the column selection line DCj connected to the drain. The source S is connected to the display element 21. The display element 21 displays brightness and darkness according to the display signal. If the row selection line DR4 is deselected here, the MOS transistor 20 is turned off and the display information is temporarily stored in the source S, but since the storage time is short at several milliseconds, refreshing is required as in the case of double series. . (Object of the Invention) In order to eliminate these drawbacks, the present invention aims to provide an image display device in which a regular storage function is added to the front panel.The drawings will be described in detail below. explain. (Structure and operation of the invention) Figure 3 (a11 is a circuit diagram of an embodiment of the present invention, Figure 3 (b)
) shows a timing diagram. In the figure, TrllA-TrmlA and TrllB-Tr
mlB is MOS) Langinuta, CIIA-Cm1A
and CIIB-CmlB are display elements, which are activated when a voltage is applied to both ends and inactivated when no voltage is applied, and display brightness and darkness. Here, the description will be made assuming a liquid crystal as the display element. MOS transistor TrllA, TrllB-Tr
The gates l'lJj of mlA and TrmlB and the row selection lines DRIA, DRIB-DRmA and DRmB, respectively, are
Each drain has column selection lines DCIA and DCI.
B is connected. Display element CI IA, CIIB
- One end of CmlA, Cm1B is MOS) transistor TrllA, TrllB-TrmlA. To the source of TrmlB, the other end is the timing line TIA,
Connected to TIB to TmA and TmB, respectively. Here, MOS transistor TrllA and display element C
The IIA constitutes a pixel cell 811A, and this pixel cell forms a matrix of mX n X 2. 1, 30 to 34 are MOS transistors, forming a Noritsubu flop. The clip-flop is a sense amplifier that reads and rewrites information stored in the pixel cells, and x and y are cross-coupled terminals with 70 knobs. MOS) transistor 30°31
A timing pulse φA is applied to the gate of the Mos transistor/transistor 34, and a timing pulse φ8 is applied to the gate of the Mos transistor/transistor 34. The drains of the MOS transistors 30 and 31 are connected to the power supply vDD, and the source of the MOS transistor 34 is grounded. 37.38 is the comparison voltage generation circuit 40-
1 to column selection lines DCIA and DCIB with comparison voltage Vre.
This is a MOS (MOS) transistor that supplies f, and a timing pulse φ1111 + φ1 can be applied to each gate. 39.40.41.42 are MOS transistors; Timing pulse φ1] is applied to the gate of 40, and timing pulse φ1. is applied to the gate of 41.42. ′ is applied a Ji-Koiru. MOS) transistor 39. 4I Dray: /kJ, XVc, 40.4
The drains of 2 are connected to YK, respectively. Also MOS
Tranogista 39. The source of 42 is the column selection line DCIA
, 40, 4] are connected to column selection lines DCIBK, respectively. 43 and 44 are MOS transistors for controlling external writing and reading, and each has a t7 timing pulse φ at its gate. 1φo8 is applied σ
The drains are connected to the input/output terminals DIA and DAB, respectively, and the north terminals are connected to the cross-coupled terminals X and Y of the flip-flops, respectively. Next, the operation of the present invention will be explained using FIGS. 3(a) and 3(b). Note that here, T1 to T6 indicate the time shown in FIG. 3(b), and all MOS transistors are N-channel M
OS) will be explained as a transistor. Also, Figure 3(b)
Regarding bright and dark writing, solid lines are displayed as bright and dotted lines as dark. First, the pixel cell 81 is connected from the outside via the input/output terminal DIA.
To write display data to 1A, timing pulse φ9
．． φII lφ11. φ4.1. and timing line TI
A Timing pulse φ is applied to all ground voltages, φ1. and sets the row selection line DRIA to a high voltage. As a result, the display signal input from the input/output terminal DIA is transmitted to the display element CIIA via the MOS transistors 43, 39 and TrllA.
(T,). MOS) transistor Trll
When the connection terminal between A and the display element CIIA is designated as XDA, the voltage of XDA corresponds to the bright/dark display signal and becomes more vP or the ground voltage. When the row selection line DRIA is grounded after the completion of rocking, a display signal is temporarily stored in the connection terminal XDA (T2). However, MOS h transistor Tr
Due to the leakage current of llA, etc., the voltage of the connection terminal XDA decreases from vP, and is grounded after several milliseconds. Therefore, in order to constantly store display signals in the pixel cells, it is necessary to periodically read out the display signals stored in the connection terminals XDA, detect and amplify them with a sense amplifier, and write them again. The procedure will be explained below. First, the timing pulse φ. 4. φ. 73, row selection line D
RIDRAB-DRmA, DRmB, timing pulse φ. ', φ8゜φ. 6. Set φ□9 to ground potential and apply timing pulse φゎ. Set φ to high voltage. As a result, the cross-coupled terminal x
, y and column selection lines DCIA and DCIB are charged to vPo (T3). Next, after setting the timing pulse φ9 to the ground voltage, the row selection line DRIA and the timing pulse φ
Set RA to high voltage (T4). At this time, column selection line DCI
A and the connection point XDA are Vl, and the voltage of
If the voltage is vPC-ΔV, the F is lowered to a voltage of vPC−ΔV. At this time, column selection line D
c] BK supplies the voltages "r'a, LΔ■" from the comparison voltage generation circuit 40-1 through the MOS) transistor 38. At this time, when the timing pulses φ and I are made high voltage, the connection terminal XDA becomes vp If so, the cross-coupled terminal X holds a voltage of V, and Y is grounded. Conversely, if the connecting terminal XDA is at the ground voltage, then X Y'iV,
. The voltage changes from -ΔV to ground voltage, and Y is V, . −
Maintains a voltage of 1. At this time again the timing pulse φ
If 4 is set to a high voltage, one of the X or Y terminals will return to ■7. . Then, the other voltage becomes the ground voltage, and a display signal is again written to the connection terminal XDA via the MOS transistor 39 and Trl IA (T5). That is, connection terminal
Even if the voltage of DA decreases from Vl to MOS transistor due to leakage, etc., the voltage of column selection line DCIA when row selection line DRIA is set to a high voltage is V, . If the display information is detected and amplified and rewritten while the difference is higher than -ΔV and the sense amplifier can detect and amplify the difference, the display signal stored in the pixel cell will be constantly stored. Similarly, if display signals stored in other pixel cells are detected and amplified by a sense amplifier and rewritten, there is no need to refresh using a frame memory or the like. Note that the liquid crystal, which is a display element, has a property that its characteristics deteriorate when a DC voltage is applied. Therefore, in the present invention, when the sense amplifier rewrites the pixel cell, the timing pulse φ is used. is grounded, φL is set to a high voltage, the rewrite signal is inverted, and the timing line TIA is set to the voltage of vl (T6). As a result, the mark IJI is placed on the display element CI IA.
The polarity of the voltage that has been inverted is reversed. By performing the above operation periodically, the polarity of the voltage applied to the display element is always reversed, and no deterioration occurs. This technology is applicable not only to cases where liquid crystal is used as a display element, but also to electroluminescence, which requires the application of an alternating current voltage.
It is also effective when using Note that V is used to read out display signals stored in pixel cells to the outside.
rC is a timing pulse φCAIφ, :1 . when the sense amplifier rewrites the pixel cell. By raising the voltage to a high voltage, it is output via the input/output terminals DIA and DAB. FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. 5o is a display panel composed of pixel cells having a self-memory function as shown in FIG. 3; 521i is a selection circuit for selecting a pixel cell; and 53 is a control circuit. Evening (Part 54 Karamote) J

[When a signal is input,
The control circuit 53 has a control line 55. Selection circuit 5 via 56
1. Select the desired pixel cell from 52 and connect it to the data bus 5.
A display signal is written to the pixel cell via 7. However, after that, since the pixel cells in the display panel store the display signals, there is no need for the control circuit to perform any control, and there is no need to provide a frame memory because the display is refreshed/refreshed. However, according to the present invention, the display signals stored in the pixel cells in the display panel can be read out to the outside, so it is possible to read out the display signals stored in the pixel cells in a specific area using the control circuit. , - by writing distribution signals to pixel cells in other areas, it is possible to easily move and copy figures. Note that even when using the display panel according to the present invention, the first
It is also possible to install a frame memory as shown in the figure. In this case, the control circuit performs display by directly cutting the display signal into the display panel, or by temporarily writing the display signal into the frame memory and then transferring the display signal from the frame memory to the display panel. Even in the case of [Izut], control is much easier than in the past, and writing can be performed at high speed. However, even if the capacitor CB (=1) is added to the terminal XD in the pixel cell of the present invention as shown in FIG. 5, the operation is the same.However, in this case, since the capacitance of the terminal There is an advantage that the voltage change of the column selection line DCIA when the sense amplifier detects the display signal of the pixel cell is small.However, in the configuration shown in FIG. 3, by irradiating the pixel cell with light from the outside, It is possible to write a display signal to a pixel cell.That is, in FIG.
When the voltage at the 1A connection terminal The target is grounded. Using this, when the timing line T]Δ is irradiated with the dawn light of the ground, the connection terminal XDA becomes ■1. It becomes grounded from
That is, writing from bright to dark is performed. Conversely, when the timing line TEA irradiates the dawn light of voltage V1+, the connection terminal
DAidV,. Similarly, it is grounded, but in this case the writing is from dark to bright. In this way, direct input of display signals from the outside to the pixel cells is very beneficial as the display panel can also serve as a graphical human-powered device. Incidentally, in order to improve the efficiency of writing using light or the like, it is also effective to connect a diode D to the connection end IXD as shown in FIG. In this case, if diode D is irradiated with light, the same operation will be performed. In the above description, light was used for writing, but the same operation can be performed using heat, electron beams, etc. if a fractional gear can be generated. (Effects) As explained above, the present invention allows the display panel to have a memory function, thereby making it possible to omit the frame memory that was conventionally necessary, and eliminating the need for controlling the reflex action. Therefore, the emergency V configuration is simplified and control becomes easier. Furthermore, since display signals can be read and written directly from the display panel, graphics can be moved and copied with simple control. However, it is possible to write display signals on the display panel by irradiating it with light or the like from the outside. Furthermore, by manually irradiating the entire surface of the display panel with a large pattern, it becomes possible to easily input a two-dimensional display signal.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional image display device 6, FIG. 2 is a diagram showing a conventional active matrix circuit, FIG. 3(a) is a circuit diagram of an embodiment of the present invention, and FIG. b) is a timing diagram, FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention, and FIGS. 5 and 6 are diagrams showing an embodiment of a pixel cell for ITI used in the present invention. It is. 1...display pie, le, 2,6 row selection circuit, 3
．． 7 ・・・・・・Column selection circuit, 4 ・・・・・・
Data bus, 5 --- Frame memory, 8
...Control circuit, 9 to 12 ...Control line,
13-・External human-powered bus, 20.30~: E, 37~
44・・・・・・MOS+・Ransistor, 21・・
... Display element, 40-1 to 40-n ... Comparison voltage generation circuit, 50- ... Display panel, 5
] + 52... Selection circuit, 53... Control circuit, 54... External human power line, 55.56......
...Control line, 57 ...Data bus, DR1
~DRm...Row selection line, DC] ~DCn ・
...Column selection line, DS ...Display element, Trl IA, TrIIB-TrmlA, Tr
mlB-・-MOS) transistor, CI IA,
CIIB-CmlA, Cm1li-.=display element,
CB...Capacity, D...Diode, DIA, DIR-...Input/output terminal, D
CIA, DCIB・・・Column selection line, DRI
A, DRI B-DRmA, DRmB-row selection line,
SI IA, SI IB-8mnA, SmnB-
--=-・Pixel cell, TEA, TUB-TmA, T
mB - Tying line, νφIl lφOAIφ0 to φ
111φl) lφ6I False IAIφR11...
...Timing pulse, X, Y ...°Cross couple terminal, XD, XDA ...Connection terminal. Patent Applicant: Nippon Telegraph and Telephone Public Corporation Figures 1-3, Figure 2, Figure 4, Figure 54, Figure 6

Claims (1)

[Claims] (11) A switching device in which electrodes are formed in a matrix on a semi-n-type layer formed on an insulating substrate such as glass or on a semiconductor substrate, and the intersection point of the electrodes can also be one or more transistors. The toco/dents and pixel electrodes are completely formed,
An image display device having a transparent electrode installed on the pixel electrode via a display element as a counter electrode includes means for writing and holding a c1 display signal in the capacitor, and a word for holding the same. Read out the number, detect and amplify it. (+iii 1-
- A double-image display device characterized by: -C. (2) Light as a means of writing the display signal to the capacitor.
The image display device according to claim (1), characterized in that it uses energy such as heat and electron beams. (3) Claim (1) is characterized by comprising means for inverting the signal at the time of rewriting.
The image display device described in section 2).