JPS60220429A - Microprocessor system - Google Patents

Abstract

PURPOSE:To attain high-speed processing with a microprocessor system with addition of less hardware by providing a microprogram memory which stores mixedly microprograms different in length of instruction words. CONSTITUTION:A ROM4 storing a microprogram contains an address of (4 bits X 2<k>) for 24 bits in an address of (20 bits X 8<k>), and a microprocessor 5 for 20 bits contains a program counter 51, instruction decoder 52, memory address switching circuit 53, ALU54 and a register 55 which latches the output of the ALU54. Furthermore, a memory 6 is added together with an AND gate 7 which secures an AND between upper two bits of a program address, two AND gates 8 which secure AND between the output of the gate 7 and upper two bits of a memory address, and two OR gates which secure OR between the outputs of the gates 8 and upper two bits of the output of the circuit 53. In such constitution, a microprogram system is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microprocessor system that requires high-speed processing.

[Background of the invention]

Like a reel-to-reel control magnetic tape device, 1
Microprocessor systems that calculate motor control current during tacho pulses must perform the calculations in a short amount of time. In particular, in order to increase the tape speed, shorter calculation times are required.

Taking logical operations as an example, conventionally, as shown in Figure 1, a 5-bit field 1 indicates an instruction code, a 6-bit field 2 indicates a constant, a memory address to perform a logical operation on, and stores the result. 8-bit field 3 and
A total of 20 bits, including 1 bit of parity P, constitute one microinstruction. When this instruction is executed, a logical operation is performed on the contents of the memory indicated by field 2 and the constant O of field 3, and the result is returned to the memory indicated by field 2. In the case of an unconditional jump, field 2 becomes the page address and field 3 becomes the intra-page address.

In the above example, field 2 of the memory address is 6 bits, so only 64 words of memory can be directly specified, but 256 words of memory are required for this microprocessor system to function as a device. Therefore, in order to calculate the contents of a memory that cannot be directly specified, it is necessary to move the contents of the memory that cannot be directly specified to a memory that can be directly specified, perform the calculation, and then return the result to the memory that cannot be directly specified. For this purpose, there are instructions to move the contents of the memory indicated by field 3 to the memory indicated by field 2, and vice versa, using field 6 as a memory address. In this way, three steps of instructions are required to perform one logical operation, and the calculation process takes time.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor system that can perform high-speed processing with little addition of hardware.

[Summary of the invention]

In order to obtain a microprocessor system capable of high-speed processing, the length of the microinstruction should be increased so that all memories can be directly specified. However, simply increasing the length of the microinstructions increases the number of P-ROMs that store the microinstructions, making it expensive.

In general, routines that require high-speed processing are part of all routines, and these routines often exist as a group.

Even if these routines are scattered in several places, it is easy to collect them in one place. In other words, by gathering routines that require high-speed processing into one microinstruction group,
By increasing the microinstruction length only in this part, it is possible to minimize the addition of P-ROM and to enable high-speed processing.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

Figure 2 shows a microinstruction for high-speed processing, consisting of a 5-bit field 1 indicating the instruction code, field 2 indicating the lower 6 bits of the memory address, field 3 indicating the constant, and the upper 2 bits of the memory address. It consists of a total of 24 bits, including 21 bits for the field, 2 bits for the 0 character, and 1 bit for the parity P. Since the memory address is 8 bits, 256 words of memory can be directly specified. Also, although the field 2Φ21 indicating the memory address is separated, it can be easily divided into □ during assembly processing.

FIG. 6 is a block diagram of the microprocessor system. The ROM 4 for storing microprograms has addresses of 20 bits x 8, and 4 bits x 2 for 24 bits added to the addresses. 20-bit microprocessor 5
Inside, a program counter 51, an instruction decoder 52, a memory address switching circuit 53, an ALU 54, and an AL
There is a register 55 that latches the U output. Also, memory 6
AND the upper 2 bits of the program address.
One D gate 7 ANDs the output of the AND gate 7 and the upper two bits of the memory address 21. Two AND gates 8 OR the output of the AND gate 8 and the upper two bits of the output of the memory address switching circuit 53. Two gates 9 constitute a microprogram system.

Next, the operation of the microprocessor system will be explained with reference to FIG. Microprogram address 1° is read from the program counter 51 by CLKl and supplied to the ROM 4, where the microinstruction 11 corresponding to address 10 is successively issued and supplied to the instruction decoder 52, ALU 54, and address switching circuit 53, and the 24-bit instruction is Then, the memory address 21 is supplied to the gate 8. The instruction decoder 52 decodes the instruction code 1 and sends the control signal to the ALU.
54 and an address switching circuit 53, and the address switching circuit 56 switches between field 2 and field 3 according to the control signal. There is a CL in the address switching circuit.
Also included is a latch that stores the memory storage address by K2.

If a 24-bit ROM is added to the upper 2k of the program address, the upper 2 bits of program address 10 are %H# at the time of a 24-bit instruction, so the output of gate 7 becomes H#, and gate 8 opens. state, and the memory address 21 is supplied to the OR gate 9 as is. In the case of a logical operation instruction, the address switching circuit 53 outputs the lower 6 bits of field 2 and the upper 2 bits of %L level. Field 21 is transmitted. Indirect addresses are not used when the address is 24 bits. The contents of the address corresponding to fields 2 and 21 are sent from the memory 6 to the ALU 54 via the XBUS 13. The ALU 54 calculates the values of the feel bar 3 and the XBUS 13 and sends the results to the register 55. CLKl to register 55
The operation of transmitting the calculation result to the register 55 takes the calculation result to the register 55 and outputs it to the YBUS 14 by CLK2, which is issued after the circuit delay from CLKl, which is performed at one timing. YBUS14 is stored in the memory 6 by CLK3 which is output after CLK2.

At the edge, CLK1 is output and the above operations are repeated to execute the program in sequence.

〔Effect of the invention〕

According to the present invention, by adding a small amount of program storage ROM and 5 gates, arithmetic instructions that were previously executed in 6 steps can be executed in 1 step, thereby making it possible to obtain a substantially high-speed microprocessor system. .

[Brief explanation of the drawing]

FIG. 1 is a display diagram showing a 20-bit microinstruction, FIG. 2 is a display diagram showing a 24-bit microinstruction according to an embodiment of the present invention, and FIG. 3 is a block diagram of a microprocessor system. 1... Instruction code, 2... Memory address, 3...
...Constant, 5...Microprocessor, 51...
Program counter, 52...Instruction decoder, 54...ALU. 55...Register.

Claims (1)

[Claims] 1. In a microprocessor system that consists of a microprogram storage memory, a microprocessor, and a work memory and can read one microprogram instruction in one access, a microprogram storage memory that stores a mixture of microprogram instructions with different instruction word lengths is used. A microprocessor system characterized by having