JPS60219880A - Shuffling circuit - Google Patents

Abstract

PURPOSE:To obtain the shuffling system in which a memory capacity of a substantial shuffling circuit is reduced by utilizing a time axis error correcting circuit in a digital reproducing device as a part of the deshuffling circuit. CONSTITUTION:A digital video signal recorded on a magnetic tape TP is fed to a PLL and block synchronizing signal detecting circuits 23a, 23b for detecting a clock signal via amplifiers 22a, 22b. An output of the circuits 23a, 23b is fed to erro detecting circuits 30a, 30b via serial/parallel converting circuits 24a, 24b, horizontal error correcting circuits 27a, 27b and vertical error correcting circuits 28a, 28b and further, its output is fed to time axis error correcting circuit and time axis expanding circuit in common use for de-shuffling circuit 31a, 31b. In using the time axis error correcting circuit as a part of the de-shuffling circuit, the memory capacity of the substantial de-shuffling circuits 32a, 32b is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF APPLICATION IN INDUSTRY-1- The present invention relates to a sharing method that is suitable for use in digital recording devices such as digital VTRs.

BACKGROUND TECHNOLOGY AND PROBLEMS In digital recording and reproducing apparatuses such as digital VTRs, it is common practice to perform shattering of digital signals on the recording side and to desharp the digital signals on the reproducing side.

For example, in a digital VTR that digitally records and reproduces a composite video signal, ζ is conventionally 20 to 3
A memory with a large capacity for 0 lines was required. This is because the chassis length of the digital composite video signal extends to several tens of lines.

Purpose of the Invention In view of the above points, the present invention is capable of utilizing a time axis error correction circuit in a digital TII generation system as a part of a deshuffling circuit, thereby reducing the memory capacity of the original deshuffling circuit. This is an attempt to propose a Sharafling method that can be used.

Summary of the Invention The Sharafling method according to the present invention is based on the A of the digital signal.
Divide the sample data of 1 solid ((liL, A is 2) into 8 data groups (however, B is 2) and C1l111 (however, C is 2), For each of these 0 data groups, the first Sharafling is performed between the sample data in each data group, and each of the above A sample data is converted into D (fixed (however, D is a power of 2) sample data). It is characterized in that it is divided into 0 unit data groups consisting of 0 (where E is 2), and a second shard ring is performed between the unit data groups of E (l & I).

According to the present invention, it is possible to obtain a deshuffling method in which the time axis error correction circuit in a digital tape playback device can be used as a part of the deshuffling circuit, and the memory capacity of the original deshuffling circuit can be reduced. I can do it.

Practical Example Hereinafter, an example in which the present invention is applied to a digital VTR will be described in detail. 1 and 2 show the recording thread and reproduction system of such a digital VTR, and the configuration of this digital Vi''R will be explained below with reference to these FIGS. Prior to explaining the recording system and reproduction thread in Figures and Figure 2, the configuration of the rotating magnetic head device will be explained. A recording rotary magnetic head and a reproducing rotary magnetic head are attached at an angular interval of, for example, 120°. It consists of a pair of very different rotating magnetic heads (head chips) arranged in close proximity. Then, the magnetic tape is wound and guided obliquely around this tape guide drum at an angle of, for example, 33 degrees.

Further, the digital video signal is magnetically transferred to a pair of rotating magnetic heads for recording so as to form a pair of closely spaced inclined recording tracks per 1/2 field, thus forming two pairs of inclined recording trunks per field. Record on tape. Then, the digital video signals of each pair of inclined recording trunks recorded in this way can be reproduced by the above-mentioned pair of raw rotary magnetic heads C1.

First, referring to FIG. 1, the recording circuit of this digital VTR will be explained. +11 is an input terminal for analog composite color video signals. The analog composite color video signal from input terminal +11 is passed through a low-pass filter. The pedestal clamp level detection signal from the sync separator circuit (4) is supplied to the clamp circuit (3) and the sync separator circuit II!&+4+ via the sync separator circuit (2).
3). The water+(i) and vertical synchronization signals from the sync separation circuit are supplied to the timing signal generation circuit (5).Furthermore, the composite color video signal from the clamp circuit (3) is supplied to the A/D converter 'Va161. It is converted to parallel 8-bit digital composite color video decoding (one line consists of 768 samples of data), and channel encoded to 1947
Each minute consists of 384 samples of data, and each channel's Sharaf ring circuit (
7a) and (7b).

These Sharafling circuits (7a) and (7b) each have a memory for 20 to 30 lines, for example, and write signals to the memory in response to timing signals from two timing signal generation circuits vR (51). The timing is controlled by these Sharaf ring circuits (7a).
, (7b) will be detailed later.

Outputs from the Sharaf ring circuits (7a) and (7b) are supplied to time axis compression circuits (8a) and (8b), respectively. These time axis compression circuits (8a) and (813) each have a memory with a capacity of, for example, 1/6 field, and the digital video signals from the Sharafling circuits (7a) and (7b) are stored in the memory for example 7 By writing with the Mllz clock signal and reading with the 8MIIz clock signal, the time axis is compressed by 11 times.

The outputs of the time axis compression circuits (8a) and (811) are sent to the CRC code signal addition circuit (9a) + < 91+)
! lq iIJ parity check code signal addition circuit (10a).

(10b) - Block address addition time 11'8 (1
/Add a block address every 6 lines) (lla
).

(llb) - Horizontal barity Chesokko F (A'
ij (-J adding circuits (12a) and (12b)) and an 8-8 conversion circuit (13a) for not reducing the amount of error when a bit error exists in the MSB.
, (13b), respectively. 8-8 conversion circuit (
13a).

The outputs of (13b) are sent to block synchronization signal addition circuits (14a), (14b)-preamplifier and boss lombre 1j addition circuits (15a), (15b), respectively.
- The delay compensation circuits (16a) and (16b) are sequentially connected to the parallel-to-serial conversion circuits (17a) and (17b).
) are supplied respectively.

Then C1 parallel-serial conversion circuit (17a), (17
The outputs of (b) are sent to scrambling circuits (18a) and (18
b). Scramble circuit (18a)
, (18b) are transmitted to the TTL and I! ,CLII! The outputs thereof are supplied to the reproducing rotary magnetic heads Ha and Hb, respectively, and recorded on the magnetic tape TP.

Next, referring to FIG. 2, the reproducing circuit of this digital VTR will be explained. The digital video signal recorded on the magnetic tape TP is transferred to the rotating magnetic tape H'a, H for reproduction.
After being regenerated by 'b, the amplifier (22a), (
22b) for clock signal detection via
(phase locked loop) and block synchronization signal detection circuits (23a) and (23b), respectively.

The outputs of the circuits (23a) and (23b) are serial-parallel conversion circuits ll! 3 (24a) and (24b) and is converted into an 18-bit parallel digital signal, the block synchronization signal and block address signal regeneration circuit (24b) is supplied to
5a) and (25b), respectively.

Note that when the block address is reproduced, the address of each sample data is also determined based on it.

The output of the reproduction circuits (25a) and (25b) is 8-8
Through the inverse conversion circuits (26a) and (26b), °ζ,
The signals are supplied to horizontal error correction circuits (27a) and (27b), respectively. Horizontal error correction circuit (27a), (27b
) outputs from the vertical error correction circuits (28a), (28
b) respectively.

Vertical error! The outputs of the f-stop circuits (28a) and (28b) are supplied to error detection circuits (30a) and (30b) via switching means (29a) and (29b). During shuttle playback (variable speed playback), the horizontal error correction circuits (27a) and (27b)
The output of the direct switching means (29a), (2rib)
The error detection times 'dK (30a), (30b
).

Soshi-C, error detection circuit (30a), (30b)
The output of is supplied to the time axis 1 to the difference correction circuit, time axis expansion circuit and deshuffling circuit (31a), (31b), respectively, and the output thereof is supplied to the deshuffling circuit (32a).
.

(32b) will be provided with people.

The circuits (31a) and (31b) each have a memory with a capacity for one field, for example, and store one field's worth of sample data using a block address as a prime during variable speed playback, so that one field's worth of sample data is stored. If so, then output it one after another and create a deshuffling circuit (32a)
, (32b). Actually, the same holds true during constant speed playback.

Also, the output of the circuits (30a) and (30b) is approximately 8M.
By writing to the memory with a 1lz clock signal and not reading it with a fixed 7 MHz clock signal, the time axis is extended.The time axis is also expanded by frequency modulating the write clock signal according to the time axis fluctuation. Error correction is being performed. Deshuffling circuit (32a)
, (32b) each have a memory capacity for 1/6 line. Incidentally, these circuits (31a).

(31b), (32a), and (32b) will be explained in detail later.

The outputs of the deshaping circuits (32a) and (32b) are supplied to a mixing circuit (33), channel decoded, and then supplied to an error correction circuit (34). The output of the error correction circuit (34) is supplied to a luminance/chromaticity separation circuit and a chromaticity phase normal rotation/inversion control circuit (35). The output of this circuit (35) is supplied to a horizontal, vertical and burst signal adding circuit (37) through a dark clip circuit and a limiter circuit (36), and in this circuit (37), a synchronizing signal source (38) is supplied. horizontal and vertical synchronization signals and burst signals are added to the digital color video signal. The output of the synchronization signal addition circuit (37) is supplied to the D/A converter (39), and the analog composite color video signal obtained from this is sent to the output terminal (41) via a low-pass filter and Bazza circuit (40). Output.

Next, referring to FIG. 3, the specific structure of the Sharaf ring circuits (7a) and (7b) in the recording circuit system of FIG. 1 mentioned above will be explained. A channel-coded 8-bit digital composite color video signal from the input terminal (42) is supplied to and alternately written to memories (44) and (45), and is alternately read from memories (45) and (44). The read digital composite color video signal is output to an output terminal (43). (46) is an address counter that counts the clock signal from the input terminal (46a) and generates an address signal, and the parallel 13-bit address signal from this counter is sent to the address selection circuits (48), (49) and the address counter. It is commonly supplied to encoders (50) and (51). This address counter (46) is connected to the timing signal generator (5).
), the start timing of counting for each field is controlled by the timing signal from Memory from line signal
(45), 1-inclusion into (46) is started.

Parallel 13-bit address signals from circuits (48) and (49) are supplied to memories (44) and (45), respectively. In the address selection circuits 19 (48) and (49), the address signal directly from the address counter (13) and the address signal encoded by the address encoders (50) and (51) are switched, respectively.
The switched address signals are stored in respective memories (44).
, (45).

(47) is a selection control circuit, which is an address counter (
46), and the obtained selection control signal is controlled by the address selection circuits (48), (49) and the memory (44).
) and (45). And memory (44
) is in the process of writing, the memory (45) is in the read state, and while the memory (45) is in the process of being written, the memory (44) is in the read state. However, a parallel 8-bit digital composite color video signal is written into the C1 memories (44) and (45) by the address signal from the address counter, and this is encoded by the address encoders (48) and (49). Sharing of the digital composite color video signal is performed by reading the digital composite color video signal using the address signal. In this case, color framing 1st-M4
The first sample data of the line signal whose color subcarrier phase is equal to that of the field signal is stored in the memory (44) or (
45) as sample data at address 0 (start address). Conversely, the digital composite color video signal is sent to the address encoder (50),
The address signal encoded by (51) is written into the memories (44) and (45), and it is read out by the address signal from the address counter (46), thereby eliminating the shattering of the digital composite color video signal. It may also be done.

Next, the Sharaf ring circuit (7a) of the recording circuit thread in Figure 1
Regarding the method of Sharafling in (7b),
C.Explain. In this embodiment, as shown in FIG.
24) Divide into 2' (-8) data groups, and for each of these 8 data groups, perform the first Sharafing among the 1024 (unique) sample data in each data group, and As shown in figure fA7 < 213 (
-8192) sample data for each 2' (=8)
(2 ” consisting of 161 sample data (= 10
The data is divided into 24) unit data groups (indicated by double circles), and the second Sharaf ring is performed between these 1024 unit data groups. In this embodiment, these first and second Sharafings are carried out simultaneously, but they can also be carried out in two stages, in which case either one may be carried out first.

First, as shown in FIG.
92 (The sample data for each fil is not arranged in order in the row direction to form a matrix of 8 rows and 1024 columns. In other words, the sample data is 1024 from the 1st column of the 1st row.
column, then from the 1st column of the 2nd row to the 1024th column, and finally to the 8th row, the 1024th column. Then, the matrix of 8 rows and 1024 columns in FIG. 4 is divided into 8 small matrices of 8 rows and 128 columns.

Generally speaking, sample data of M rows and N columns is Q
The Q matrix is a matrix with M' rows and P columns. Furthermore, here M, N
, M', P and Q are the electric fluxes of 2, respectively. Also, in this example, M=M'.

Therefore, the first Sharafing is performed within each of these 8 rows and 128 columns of small matrices, that is, within each data group. In this case, in a data group consisting of a small matrix of 8 rows and 128 columns, sample data in each column is fixed and 128 columns are subjected to sharfling. Figure 5 shows the configuration of the address encoder section for performing the shard ringing of each data group. By providing a connection circuit (address encode circuit) for inverting the LSB-MSB of the digits of the 8-pin address signal terminal, an encoded 8-bit address signal terminal of the digits 2° to 21 is obtained. This address encoding is 128 in 8 lines each.
Do this for each column data group.

Note that encoding is not performed on the 3-bit address signal representing the address of sample data constituting each column.

In addition, various other address encoding circuits are possible for this shard ringing for each data group.
For example, it is also possible to perform as shown in FIG. That is, in FIG. 6, the small circles on the left are the 8-bit address signal terminals for the 20th to 27th digits for each column, and the small circles on the right are the encoded 8-bit addresses (V
This is an external terminal. In this case, a full adder (52) is provided,
The address signal of the 24th to 2' digits at the input end and the 2° to 2j
and the address signal of the digits 24 to 2C of the encoded address signal on the output side are added. However, any overflow will be discarded. And ゛? of the digits 2° to 2j on the input side? The dress signal is used as it is as an output signal of the 2° to 2J digit on the output side.

In this example, the full adder (52) adds the -higher 4 bits and the upper 4 bits of the address signals of the 8 pins at the input end.
Although bits are added, the digit of the address signal supplied to the full adder (52) can be arbitrary as long as bit signals of consecutive digits are added.

Then, C1 is 8 which has been shuffled by address encoding as explained in FIG. 5 or FIG. 6 above.
The sample data of the matrix with rows and 1024 columns is the seventh
As shown in the figure, the data are grouped into unit data groups of 8 points each in the row direction and arranged to form a matrix of 8 rows and 128 columns.

Therefore, although the circle mark in FIG. 4 indicates the data of one sample, the double circle mark in FIG. 7 will omit the data of eight samples. The matrix in Figure 7 generally has R rows and S
It becomes a matrix of columns, and RlS are both raised to the power of 2. Also, if the number of sampling data of the unit data group constituting this matrix is shifted from 'F', then Rx5xl'=A
becomes. Of course, GonoT is also a guard of 2.

In order to perform Sharafing of each unit data group of the matrix shown in Fig. 7, in order to perform Sharafring between 8 x 128 unit data groups, as shown in Fig. 8, according to Fig. 5. , a connection circuit that inverts the LSB-MSI3 of the 10-bit address signal of the digits 2° to 29.
It may be provided between the 0-bit input and output terminals.

Alternatively, as shown in FIG. 9, according to FIG. The outputs are the encoded address signals 26 to 29. In this case as well, the overflow in the full adder (56) is discarded. 24 digit signal as it is on the output side 2° ~ 2
A 4-digit signal may be used.

It should be noted that various other modifications can be made to the address encoding method for Sharaf ring shown in ff15 and FIG. 6, and FIG. 8 and FIG. 9.

Therefore, the address encoder shown in FIG. 5 or 6 and the address encoder shown in FIG.
The address encoders of FIG. 9 or FIG. 9 can be connected in cascade or can be integrated.

Next, we will explain the specific configuration of the time axis error correction circuit, time axis expansion circuit/deshasofling circuit (31a), (31b), and deshasofring circuit (32a), (32b) in the reproduction circuit of the digital VTR shown in Figure ff12 above. This will be explained with reference to the figures. Circuit (31a).

(31b) is composed of a cascade circuit of a serial-parallel conversion circuit (54), a Memo'J (55), and a parallel-serial conversion circuit (56).

The memory (55) can have a capacity of 2 fields, and in this embodiment, a 1 field memory is used. Note that this memory (55) performs the time axis error correction and time axis expansion of the signal as described above.

Next, deshuffling will be explained. This circuit (
In circuits 31a) and (31b), deshuffling corresponding to the above-mentioned second Sharaf ring is performed, and in circuits (32a) and (32b), deshuffling corresponding to the above-mentioned first Sharaf ring is performed. Circuits (31a) and (31b) In order to increase the writing speed in the memory (55), each bit of the parallel 8-bit signal is further converted into an 8-bit parallel signal by the serial-parallel conversion circuit (54). Convert and store memory (
55) and is inversely converted into nine parallel 8-bit signals by the parallel-to-serial conversion circuit (56). And for C1 this memory (55),
A small address signal forming circuit is provided in FIG. 3 described above, and uses the double write and read clock signals as address signals to perform address decoding, which is the reverse of the address encoding shown in FIG. 8 or 9. °C
There is.

Furthermore, in the circuits (32a) and (32b),
The memory is provided with an address signal forming circuit similar to that shown in FIG. 3, and performs address decoding which is the reverse of the address encoding performed in FIG. 5 or 6.

Thus, most of the memory capacity for the desyasofring is used by the time axis error correction circuit (31a).

Since it is occupied by the memory (55) of (31b), the capacity of each memory of the desensitizing circuit WR (32a) and (32b) can be as small as, for example, 1/6 line.

On the other hand, the present invention is applicable not only to digital VTRs but also to digital audio recorders, digital video or audio disc (optical, magnetic, etc.) recording 4j+ raw systems.

According to the present invention described above, it is possible to use the time axis error correction circuit in a digital playback device as a part of the deshuffling circuit, and to obtain a deshuffling method that can reduce the memory capacity of the original deshuffling circuit. can.

Effects of the Invention According to the present invention described above, it is possible to use the time axis error correction circuit in a digital playback device as a part of the Desyasofling circuit, thereby obtaining a Sharafing method that can reduce the memory capacity of the original Desyasofring circuit. be able to.

[Brief explanation of drawings]

1 and 2 are block diagrams of the recording circuit system and the reproducing circuit system of a digital VTR to which the present invention is applied, respectively, and FIG. 3 shows the specific configuration of the sharrafling circuit of the recording circuit shown in FIG. 1. FIG. 4 is a block diagram for explaining the Sharaf ring, FIG. 5 and FIG. Figure 7 is a layout diagram to explain the Sharaf ring, Figures 8 and 9 are circuit diagrams of the address signal encoding circuit for the Sharaf ring, and Figure 10 is the time axis error correction in Figure 2. FIG. 2 is a block diagram showing a specific configuration of a circuit and a deshuffling circuit. Procedural amendment dated July 28, 1980 1. Indication of the case 1989 Patent Application No. 76277 2. Appearance of the invention / Sharafling method 3. Person making the amendment Relationship with the case Patent applicant address Tokyo Parts Co., Ltd. Ward Kitashina 6-7-35 Name (21
8) Soni 7 Co., Ltd. Representative Director: Nori Kaga [4, Agent: 1-8-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (
Utsubo Dairy Building) Tokyo (03) 343-5821 (Representative)
6. Number of inventions increased by amendment (IJ The scope of claims in the specification is corrected as shown in the attached sheet.
...is a feature. ” should be changed to a new line and corrected as follows. ``The Sharuff ringing method according to the present invention performs first Sharuff ring for each sample data within a predetermined number of sample data of a digital signal, and for every certain number of sample data on which this first Sharuff ring has been performed. The invention is characterized in that the first Sharuff ring is performed for each sample data within a predetermined number of sample data of a digital signal, and 1st
A second Sharafing method is characterized in that a second Sharafing is performed for every certain number of sample data that have been subjected to Sharuffling.

Claims (1)

[Claims] The sample data of digital signal A (lkl (however, human is 2 makurida) is divided into data groups of 8 pieces (however, B is 2 makuni) each of C11lII (however, C is 2 makugi). D 1ll11 ((11L, , D is 2's The method is characterized in that it is divided into E unit data groups (where E is 2 to the M power) consisting of sample data of E(11+1), and a second Sharaf ring is performed between the E(ll+1) unit data groups. Sharafling method.