JPS60217658A - Protective circuit for input to semiconductor integrated circuit device - Google Patents

Protective circuit for input to semiconductor integrated circuit device

Info

Publication number
JPS60217658A
JPS60217658A JP59074336A JP7433684A JPS60217658A JP S60217658 A JPS60217658 A JP S60217658A JP 59074336 A JP59074336 A JP 59074336A JP 7433684 A JP7433684 A JP 7433684A JP S60217658 A JPS60217658 A JP S60217658A
Authority
JP
Japan
Prior art keywords
input
voltage
input protection
circuit
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59074336A
Other languages
Japanese (ja)
Inventor
Michio Nakajima
中島　三智雄
Yukio Miyazaki
行雄 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59074336A priority Critical patent/JPS60217658A/en
Publication of JPS60217658A publication Critical patent/JPS60217658A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

PURPOSE:To improve the breakdown withstanding voltage of an input protective resistor, or to shorten the retardation time of an input section by constituting an input protective circuit by using a punch-through transistor, which can clamp input applied voltage at voltage higher than a diode for a conventional circuit, and splitting voltage applied to the input protective resistor by the transistor. CONSTITUTION:Punch-through transistors 9, 10 connected in series between maximum potential 2 and minimum potential 3 can clamp input applied voltage at voltage higher than a conventional input protective diode. A junction C between both transistors 9, 10 is connected to a gate 13 in insulated gate field- effect type semiconductor elements 11, 12. Both semiconductor elements 11, 12 are each shaped in P channel and N channel insulated gate field-effect type semiconductor elements, and a terminal 14 represents outputs from both semiconductor elements 11, 12. Input voltage is applied to one end of an input protective resistor 18 consisting of polycrystalline silicon positioned on an insulator, and the other end is connected to the junction C.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体集積回路装置の改良、特にその入力
保護回路の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in semiconductor integrated circuit devices, and particularly to improvements in input protection circuits thereof.

〔従来技術〕[Prior art]

従来のこの種の半導体集積回路装置の入力保護回路を第
１図を用いて説明する。図において、１は入力電圧印加
部分で、これは入力保護抵抗８の一端に接続されている
。この入力保護抵抗８は絶縁物上に置かれ、これの他端
は直列に接続された２つの入力保護ダイオード４．５の
接続点Ｃ及び絶縁ゲート電界効果型半導体素子６のゲー
ト７に接続されており、この入力保護ダイオード４のカ
ソードは本回路内で使用している最高電位２に、またダ
イオード５のアノードは本回路内で使用している最低電
位３に接続されている。A conventional input protection circuit for this type of semiconductor integrated circuit device will be explained with reference to FIG. In the figure, 1 is an input voltage application part, which is connected to one end of an input protection resistor 8. This input protection resistor 8 is placed on an insulator, and its other end is connected to the connection point C of two input protection diodes 4.5 connected in series and to the gate 7 of the insulated gate field effect semiconductor element 6. The cathode of this input protection diode 4 is connected to the highest potential 2 used in this circuit, and the anode of the diode 5 is connected to the lowest potential 3 used in this circuit.

次に動作について説明する。Next, the operation will be explained.

この従来の入力保護回路は、異常電圧が入力電圧印加部
分１に印加された場合に、ゲート７のゲート酸化膜破壊
を防止する回路である。第１図において、入力電圧印加
部分１に急峻な異常電圧が印加された場合、異常電圧値
が最高電位２と入力保護ダイオード４の順方向電位降下
とをプラスした値以上であれば、その電位差が入力保護
抵抗８に印加される。また、異常電圧値が最低電位３と
入力保護ダイオード５の順方向電位降下とをプラスした
値以下であれば、その電位差が入力保護抵抗８に印加さ
れることになる。This conventional input protection circuit is a circuit that prevents the gate oxide film of the gate 7 from being destroyed when an abnormal voltage is applied to the input voltage application portion 1. In FIG. 1, when a steep abnormal voltage is applied to the input voltage application portion 1, if the abnormal voltage value is greater than the sum of the highest potential 2 and the forward potential drop of the input protection diode 4, the potential difference is applied to the input protection resistor 8. Further, if the abnormal voltage value is equal to or less than the sum of the lowest potential 3 and the forward potential drop of the input protection diode 5, that potential difference will be applied to the input protection resistor 8.

しかし、この従来回路では、入力保護ダイオード４．５
の順方向電位降下が０．７Ｖ程度しかなく、急峻な異常
電圧値から最高電位２、もしくは最低電位３を引いた値
のほぼ全部が入力保護抵抗８に印加され、そのため、こ
の従来回路では入力保護抵抗８の破壊を招きやすく、ま
た、この破壊を防止するため入力保護抵抗８の抵抗値を
大きくとると、入力部分の時定数τが大きくなり、遅延
時間が長くなるという欠点があった。However, in this conventional circuit, the input protection diode 4.5
The forward potential drop is only about 0.7V, and almost all of the value obtained by subtracting the highest potential 2 or the lowest potential 3 from the steep abnormal voltage value is applied to the input protection resistor 8. Therefore, in this conventional circuit, the input The protection resistor 8 is likely to be destroyed, and if the resistance value of the input protection resistor 8 is increased to prevent this destruction, the time constant τ of the input portion becomes large and the delay time increases.

〔発明の概要〕[Summary of the invention]

この発明は、かかる欠点を解消するためになされたもの
で、従来の入力保護ダイオードをバンチスルートランジ
スタに置き換えることにより、破壊耐圧を向上でき、あ
るいは入力部の遅延時間を短縮できる半導体集積回路装
置の入力保護回路を提供することを目的としている。The present invention has been made to eliminate these drawbacks, and by replacing the conventional input protection diode with a bunch-through transistor, it is possible to improve the breakdown voltage or shorten the delay time of the input section of a semiconductor integrated circuit device. The purpose is to provide an input protection circuit.

（発明の実施例〕 以下、この発明の実施例を図について説明する。(Embodiments of the invention) Embodiments of the present invention will be described below with reference to the drawings.

第２図はこの発明の一実施例による半導体集積回路（０
ＭＯ３）装置の入力保護回路の回路構成を示す。図にお
いて、第１図と同一符号は同−又は相当部分を示し、９
．１０は最高電位２と最低電位３間に直列に接続された
バンチスルートランジスタで、該両トランジスタ９．１
０は入力印加電圧を上記従来の入力保護ダイオード４，
５よりも高い電圧でクランプできる。そして該両トラン
ジスタ９．１０の接続点Ｃは絶縁ゲート電界効果型半導
体素子１１．１２のゲート１３に接続されている。なお
、該両半導体素子１１．１２はそれぞれＰチャンネル、
Ｎチャンネル絶縁ゲート電界効果型半導体素子であり、
１４は該両半導体素子１１．１２の出力である。１８は
絶縁物上に置かれた多結晶シリコンからなる入力保護抵
抗であり、これの一端には入力電圧が印加され、他端は
上記接続点Ｃに接続されている。FIG. 2 shows a semiconductor integrated circuit (0
MO3) The circuit configuration of the input protection circuit of the device is shown. In the figure, the same reference numerals as in Figure 1 indicate the same or corresponding parts, and 9
．． 10 is a bunch-through transistor connected in series between the highest potential 2 and the lowest potential 3, both transistors 9.1
0 is the input voltage applied to the conventional input protection diode 4,
Can be clamped at a voltage higher than 5. A connection point C between both transistors 9.10 is connected to a gate 13 of an insulated gate field effect semiconductor element 11.12. Note that both the semiconductor elements 11 and 12 are P-channel and P-channel, respectively.
An N-channel insulated gate field effect semiconductor device,
14 is the output of both semiconductor elements 11 and 12. Reference numeral 18 denotes an input protection resistor made of polycrystalline silicon placed on an insulator, one end of which is applied an input voltage, and the other end connected to the connection point C mentioned above.

次に作用効果について説明する。Next, the effects will be explained.

本実施例回路では、従来回路において入力保護抵抗８に
かかっていた異常電圧をバンチスルートランジスタ９，
１ｏに分担させることにより、破壊耐圧の向上、入力部
による遅延時間の短縮ができる。In this example circuit, the abnormal voltage applied to the input protection resistor 8 in the conventional circuit is removed by the bunch-through transistor 9.
1o, the breakdown voltage can be improved and the delay time due to the input section can be shortened.

例えば、従来回路及び本実施例回路において、入力容量
がｌ０ＦＦ、入力保護抵抗値が３００Ω、絶縁ゲート電
界効果型半導体素子１１．１２のゲート絶縁破壊耐圧が
５０Ｖ、入力保護ダイオード４．５の順方向電位降下が
０．７　Ｖ、バンチスルートランジスタ９．１０による
電位降下が３ｏｖ、入力異常電圧が１００Ｖ、最高電位
２が５Ｖ、最低電位３がＯｖのとき、従来の入力保護回
路の入力保護抵抗８で消費される電力は２９．６Ｗ程度
であるが、本実施例の入力保護抵抗１８の消費電力は、
１４．１Ｗ程度と少なくなる。For example, in the conventional circuit and the circuit of this embodiment, the input capacitance is 10FF, the input protection resistance value is 300Ω, the gate dielectric breakdown voltage of the insulated gate field effect semiconductor device 11.12 is 50V, and the forward direction of the input protection diode 4.5. When the potential drop is 0.7 V, the potential drop due to the bunch through transistor 9.10 is 3 ov, the input abnormal voltage is 100 V, the highest potential 2 is 5 V, and the lowest potential 3 is Ov, the input protection resistor 8 of the conventional input protection circuit The power consumed by the input protection resistor 18 of this embodiment is approximately 29.6W, but the power consumption of the input protection resistor 18 of this embodiment is
The power consumption is reduced to about 14.1W.

また、従来の入力保護抵抗８と消費電力が同じになるよ
うに本実施例の入力保護抵抗１８の値を決めるとすれば
、該抵抗値は１４３Ω程度となり、そのため入力保護回
路の入力部の時定数は、従来では３ｎＳであるのに対し
、本実施例では１．４ｎＳと小さくなる。Furthermore, if the value of the input protection resistor 18 of this embodiment is determined so that the power consumption is the same as that of the conventional input protection resistor 8, the resistance value will be approximately 143Ω, and therefore, at the input section of the input protection circuit. While the constant is 3 nS in the conventional case, it is reduced to 1.4 nS in this embodiment.

ここで、バンチスルートランジスタ９．１０のバンチス
ルー電圧は、これらが絶縁ゲート電界効果型であれば、
ソース・ドレイン間隔、及びその領域のアクセプタある
いはドナーのドープ量により変えることができ、またバ
イポーラ型であれば、ベース幅あるいはベースの濃度に
より変えることができる。そのため、この入力保護回路
を使用する半導体集積回路装置に応じたパンチスルー電
圧を有するバンチスルートランジスタを用いることがで
きる。Here, the bunch-through voltage of the bunch-through transistors 9 and 10 is, if these are insulated gate field effect type,
It can be changed by changing the source-drain distance and the amount of acceptor or donor doping in that region, and if it is a bipolar type, it can be changed by changing the base width or base concentration. Therefore, a bunch-through transistor having a punch-through voltage suitable for a semiconductor integrated circuit device using this input protection circuit can be used.

なお、上記実施例では半導体集積回路がＣＭＯ８回路で
ある場合について説明したが、本発明はこの種の他の半
導体装置にも適用できることはいうまでもない。In the above embodiment, the case where the semiconductor integrated circuit is a CMO8 circuit has been described, but it goes without saying that the present invention can be applied to other semiconductor devices of this type.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、入力印加電圧を従来
回路のダイオードより高い電圧でクランプできるバンチ
スルートランジスタを用いて入力保護回路を構成し、入
力保護抵抗にががる電圧を該トランジスタにて分割する
ようにしたので、入力保護抵抗の破壊耐圧の向上、もし
くは入力部遅延時間の短縮ができる効果がある。As described above, according to the present invention, an input protection circuit is configured using a bunch-through transistor that can clamp the applied input voltage at a voltage higher than that of a diode in a conventional circuit, and the voltage across the input protection resistor is transferred to the transistor. Since it is divided into two parts, the breakdown voltage of the input protection resistor can be improved or the delay time of the input section can be shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体集積回路装置の入力保護回路の回
路図、第２図は本発明の一実施例による半導体集積回路
装置の入力保護回路の回路図である。 図において、１８は入力保護抵抗、９．ｌＯはパンチス
ルートランジスタ、２，３は半導体集積回路装置の最高
電位、最低電位、１１．１２は絶縁ゲート電界効果型半
導体素子、１３は半導体素子１１．１２のゲートである
。 なお図中、同一符号は同−又は相当部分を示す。 代理人　大岩増雄 第１図 第２図FIG. 1 is a circuit diagram of a conventional input protection circuit of a semiconductor integrated circuit device, and FIG. 2 is a circuit diagram of an input protection circuit of a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 18 is an input protection resistor, 9. 10 is a punch-through transistor, 2 and 3 are the highest and lowest potentials of the semiconductor integrated circuit device, 11.12 is an insulated gate field effect semiconductor element, and 13 is the gate of the semiconductor element 11.12. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2

Claims (2)

【特許請求の範囲】[Claims] （１）　絶縁物上に置かれ一端に入力電圧が印加され他
端が半導体集積回路装置の絶縁ゲート電界効果型半導体
素子のゲートに接続された入力保護抵抗と、上記集積回
路装置の最高電位と最低電位間に直列に接続されその接
続点が上記半導体素子のゲートに接続された２個のパン
チスルートランジスタとを備えたことを特徴とする半導
体集積回路装置の入力保護回路。(1) An input protection resistor placed on an insulator and having one end to which an input voltage is applied and the other end connected to the gate of an insulated gate field effect semiconductor element of a semiconductor integrated circuit device, and the highest potential of the integrated circuit device. An input protection circuit for a semiconductor integrated circuit device, comprising two punch-through transistors connected in series between the lowest potentials and whose connection point is connected to the gate of the semiconductor element. （２）　上記入力保護抵抗は、多結晶シリコンからなる
ことを特徴とする特許請最の範囲第１項記載の半導体集
積回路装置の入力保護回路。(2) The input protection circuit for a semiconductor integrated circuit device according to claim 1, wherein the input protection resistor is made of polycrystalline silicon.
JP59074336A 1984-04-12 1984-04-12 Protective circuit for input to semiconductor integrated circuit device Pending JPS60217658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59074336A JPS60217658A (en) 1984-04-12 1984-04-12 Protective circuit for input to semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59074336A JPS60217658A (en) 1984-04-12 1984-04-12 Protective circuit for input to semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60217658A true JPS60217658A (en) 1985-10-31

Family

ID=13544172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59074336A Pending JPS60217658A (en) 1984-04-12 1984-04-12 Protective circuit for input to semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60217658A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5099302A (en) * 1988-09-14 1992-03-24 Sgs-Thomson Microelectronics, S.A. Integrable active diode
EP0860941A2 (en) * 1997-02-25 1998-08-26 Nec Corporation Semiconductor integrated circuit having input protection circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5099302A (en) * 1988-09-14 1992-03-24 Sgs-Thomson Microelectronics, S.A. Integrable active diode
EP0860941A2 (en) * 1997-02-25 1998-08-26 Nec Corporation Semiconductor integrated circuit having input protection circuit
EP0860941A3 (en) * 1997-02-25 2002-01-09 Nec Corporation Semiconductor integrated circuit having input protection circuit

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