JPS60217596A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To boost appropriately a supply voltage supplied to a terminal for common use of a signal and a power source by increasing a supply voltage and by limiting it to the prescribed value with the aid of a constant voltage means. CONSTITUTION:When a pin 6 is switched from for signal use to for power supply use, a supply voltage is supplied and a control signal A becomes ''L'', an oscillator circuit 20 operates and a transistor 8 of an invertor 21 is controlled. On the other hand, an output end O1 of a power source switching circuit 11 is charged by a difference voltage between the supply voltage and a threshold voltage of a transistor 4, while an output voltage of the output end O1 of the invertor 21 is boosted through the capacitor 21 by synchronizing with an oscillation outut of the circuit 20. When this boosting voltage exceeds a break voltage, a diode 24 is broken down and said voltage is set to the prescribed value. The output voltage of the output end O1 of a power source switching circuit 13 is boosted by the prescribed value, and an appropriate supply voltage without a drop due to the threshold voltage of a transistor 4, etc., can be taken out from an output end O2 of an invertor 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit having a function of boosting the voltage of a power supply supplied to the same terminal as a terminal to which a signal is supplied.

[Technical background of the invention and its problems]

Generally, the number of external lead-out pins (terminals) led out from the package of a semiconductor integrated circuit is preferably small from the viewpoint of downsizing the package. One possible solution to problem B is to share the external lead pins of the integrated circuit, but when considering sharing the signal pin and power supply bin, the internal wiring of the integrated circuit associated with this bin may be Since it is a problem to flow a current exceeding the current capability of the input signal (for example, about +10 μA to −10 μA), it is necessary to suppress the current value within the range of this capability. Such a bin sharing circuit is described in detail in, for example, Japanese Patent Application No. 54-23204, and this circuit will be explained below. The circuit shown in FIG. 1 basically consists of a power supply switching circuit 1 and an inverter (inverting circuit) 2. The circuit shown in FIG. Among these, the power supply switching circuit 1 is a depletion type MOS whose sources are commonly connected and whose output terminal is the common connection point O1.
and an enhancement type MOS) Lanzostar 4. An external lead-out pin 5 is provided at the drain of the transistor 3, and the power supply voltage VC used is normally supplied to this pin 5 at all times. Further, a control signal A is supplied to the dart of the transistor 3. Further, the drains and darts of the transistors 4 are commonly connected, and another pin 6 is provided at this common connection point. The pin 6 is connected to a signal related to the power supply voltage VC, that is, a signal that sets the Vc level to a high logic level and the earth (ground) level to a low logic level, or a power supply voltage V that is also a high voltage in addition to the VC level. Either one is supplied. The power supply switching circuit 1 constituted by the transistors 3 and 4 is as follows:
Depending on the level of the control signal A, the power supply voltage ve or Vp supplied to each pin 5.6 is switched and outputted from the output terminal O1. Note that the signal supplied to the pin 6 is supplied to another circuit (not shown).

The drain of the inverter 2 is connected to the output terminal 01 of the power supply switching circuit 1, and the source thereof is connected to the output terminal 02 of the power supply switching circuit 1.
It is composed of a depletion type MOS transistor 7 connected to the output terminal 02, and an enhancement type MOS transistor 8 having a drain connected to the output terminal 02 and a source connected to ground. A control signal B is supplied to the dart of the transistor 8.

In the above configuration, when pin 6 is used as a signal pin, control signal A is set to a high (logical) level (ve
level (for example, +5 built) and turns on transistor 3. Transistor 3. If it turns on, the output terminal O1
The voltage is approximately VC. 'At this time, if the signal voltage supplied to pin 6 is used as an input signal for another circuit, the maximum voltage is usually (vc 11) volts, and the output terminal is 0.
The voltage of 1 is approximately V. Therefore, if the threshold b value voltage Vth4 of the transistor 4 is set to around 1 build, almost no input current will flow when a signal is supplied to the pin 6, and it can be used as an input signal for other circuits. At this time, high and low level signals are outputted to the output terminal 02 of the inverter 2 in accordance with the level of the control signal B.

On the other hand, when pin 6 is used as a power supply pin, power supply voltage Vp (for example, +25 melt) is supplied to pin 6, and control signal A is set to a low level. At this time, V, -
Vth4〉Vas ”th5 and V,〉Vas -Vt
hs (however, vo3, Vthsc) 5 y 9
The transistor 3 is cut off in the range of f-) voltage and threshold voltage of xri3, and the voltage at the output terminal O1 becomes v
It becomes p-vth4. At this time, if the control signal B is at a low level, the voltage vrvth4 remains at the output terminal 0.
2 is output.

Figure 2 shows an EFROM (
(Racer pull programmable ROM) is a circuit configuration diagram. This ROM uses pin 6 as a signal bin when reading data, and pin 6 when writing data.
This is used as a power supply bottle to supply +25♂ volt voltage. In Figure 2, 10 is a voltage detection circuit that detects the voltage at pin 6, and the voltage at pin 6 is vc.
A high level signal is output in the following cases, and a low level signal is output in the case of vp. The output signal of this voltage detection circuit 10 is supplied as a control signal A to the dart of the transistor 3, and is also supplied as a control signal B to the transistor P-) of the transistor 8.

Further, 111 to 11n are address decoders, and the output terminals of each of the address decoders 111 to 11n are connected to depletion type MO8 transistors 12 to 12n, each of which receives the output signal of the voltage detection circuit io as a dart input. , for example, to each of the row lines 135 to 13n to which the darts of a large number of memory cells (not shown) are connected. In addition, each of the row lines 131 to 13n includes a depletion type MOS) transistor 14f-),
The sources are commonly connected, and each transistor 14
The inverter 2 is connected between the drain of the inverter 2 and the pin 6.
Each of the enhancement type MOS lanzosters 15 is inserted to input the voltage at the output terminal 02 of the R-).

When writing data to each memory cell in the above ROM, the normally used power supply voltage ve(+
5s) Since it is necessary to apply a high voltage,
In this case, pin 6 is supplied with the power supply voltage vp (+25 volts). At this time, the output signal of the voltage detection circuit 10 is at a low level, and the transistor 3 in the power supply switching circuit 1 and the transistor 8 in the inverter 2 are cut off, so the voltage at the output terminal 02 of the inverter 2 is as described above. It becomes approximately vp-vth4. Furthermore, when the voltage at the output terminal 02 becomes approximately Vp-vth4, each transistor 15
is turned on, and the hood is on each row line 131 to 13n.
4-vthI5 (where vthI5 is the threshold voltage of transistor 15) is applied.

At this time, the transistors 121 to 12n are cut off or turned on according to the outputs of the address decoders 111 to 11n, so the above voltage vP-vt h is applied only to the row line to which the cut-off transistor among the transistors 121 to 12n is connected. 4-Vt hl 5 is applied to write data.

However, in the above ROM, V is +25? When the current is supplied, the threshold voltages of transistors 4 and 15 are approximately 3? due to the back dart bias effect. (However, the resistivity of the substrate is 20
Q", P -) If the oxide film thickness is so l and the threshold voltage is Q, 8 del when the substrate and source are at the same potential) 1. Is the voltage at the output terminal 02 of the inverter 2 +25?
Ruto Yoshi is also about 3? Root low - +22 volts, line 131
The voltage applied to ~13n is +22♂ and also about 3? In this way, in the past, when power supply voltage was supplied to an external output bin that was shared for both signal and power supply, the voltage that could actually be used was lower, resulting in poor voltage efficiency. However, in the ROM shown in FIG. 2, the output voltage of each transistor 15, that is, the output pO of the inverter 2,
If the voltage of z is set to a voltage close to the drain voltage, that is, the voltage vp supplied to the bin 6, but also higher than the voltage Vp, 1: j), the voltage applied to the rows fm13s to fm13n will be approximately Vp. I can do it. Therefore, in order to make the voltage at the output terminal 0 of the inverter 2 close to V or higher than V, it is necessary to boost the voltage supplied to the bin 6.

[Purpose of the invention]

This invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide a voltage boosting means for signals and power supplies. The smear source voltage is boosted, and the boosted voltage is limited to a predetermined value by a constant voltage means.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In Figure 3, 1. Second. Third power supply switching circuit 11g
Each of 12r13 is an enhancement type MOS whose drain and dart are commonly connected to the transistor 3 of the disol 7Illn type which receives the control signal A as the r-to input, as shown in FIG. 4
It is composed of. Also number 1. Each of the second inverters 21 and 22 is also similar to that shown in FIG.
A deresolution type MOS whose dart and source are commonly connected to the output terminal 02.Transistough and control signal B are connected to P
-) an enhancement type MOS as an input; and) a run source 8. The output terminal O1 of the first power supply switching circuit 11 is connected to the power supply terminal of the first inverter 21, that is, the drain of the transistor 7. Also, the transistor 8 in the first inverter 21
The above-mentioned 1st, 2nd, etc. are used for the dirt. Third power supply switching circuit 1
8.1 □, an oscillation circuit 20 that generates a repetitive signal of a predetermined frequency during a period when the power supply voltage vp is supplied to the bin 6 to which the drains of the transistors 4 in 13 are commonly connected;
The output signal of is supplied as the control signal B. Output terminal O of the first inverter 21! A first capacitance 2 is connected between the output terminal O1 of the second power supply switching circuit 12 and the output terminal O1 of the second power supply switching circuit 12. Further, the second power supply switching circuit 12
A second capacitor/4' capacitance 22 is connected between the output terminal 02 and ground. Note that this second capacitance is at the output terminal 0. Parasitic capacitance such as stray capacitance and f-) capacitance may be used, or a new capacitance may be added. The output terminal O1 of the third power supply switching circuit 13 is connected to the power supply terminal of the second inverter 22, that is, the drain of the transistor 7. Further, the second and third power supply switching circuits 1. ．． Between the output terminals of 13, there is an I-type MO whose drain and dart are commonly connected and diode-connected.
S) The run source 23 is connected. Does the I-type transistor mentioned here have a threshold voltage of 0? It refers to something near the root (eg -0,3♂ root). Furthermore, the second
The connection between the output terminal 01 and the ground of the power supply switching circuit 12 is as follows:
A diode 24 is connected with its anode facing the ground side.

FIG. 4 shows a specific configuration of the oscillation circuit 20. As shown in the figure, this circuit is a depression type,
It is composed of an enhancement type Oyohi type I (MOS) transistor (transistor 41) and a capacitor, and has a power down function. That is, when the control signal X is at a low level (when the pin 6 is used as a signal pin), the arm is in a power-down state and does not oscillate. On the other hand, when the signal I is at a high level (when the bin 6 is used as a power supply bin), it oscillates to generate a repetitive signal of a predetermined frequency.

FIG. 5 (a3 to (h)) are waveform diagrams showing an example of the operation of the above-mentioned embodiment circuit. The voltage change waveform is shown in the same figure (
c) shows the output voltage change waveform of the oscillation circuit 20;
is the voltage change waveform of the control signal B, and (e) of the same figure is the voltage change waveform of the control signal B. The voltage change waveform of is shown in the same figure (f
) shows the voltage change waveform at the output terminal O1 of the second power supply switching circuit 12, and (g) in the figure shows the voltage change waveform at the output terminal O1 of the third power supply switching circuit 13.
The voltage change waveform of the output terminal O: of the second inverter 22 is shown in FIG.

Hereinafter, the operation of the above embodiment circuit will be explained using FIGS. 5(a>-(h)).

First, as shown in FIG. 5(a), bin 6 is used as a signal bin at time 1, before and after t4, and at time t
It is assumed that the pin is used as a power supply pin during the period from 1 to t4. Before time t1 and after time t4, the voltage of the bin 6 is VC or O built, and the signal A is at a high level and the signal I is at a low level, so the output of the oscillation circuit 20 is at a low level.・-Evening 2! The voltage at the output terminal of 0,
Second. Third power supply switching circuit 1. ．． The voltage at the output terminal O1 of each of the 13 output terminals becomes approximately vc (for example, +5 volts).

At this time, signal B is at a high level, so the 'Fl pressure at the output terminal of the second inverter 22, Oz, is O? Built, ie low level. Next, time 1. In this case, the pin 6 is used as a power supply pin, and a power supply voltage VP (for example, +25V) is supplied. At this time, the oscillation circuit 20 operates with the signal A at a low level and the signal As shown, a repetitive signal of a predetermined frequency whose voltage changes between ve and 0♂tort is input. Furthermore, at this time, the drain of the transistor 7 in the first inverter 21 has a voltage VP 'th4 which is lower than VP by the threshold voltage VthJ of the transistor 4. Since the voltage of
A waveform in which the voltage changes between h4 and h4 is obtained. On the other hand, the second. Third power supply switching circuit 1, . 13, each transistor 4 causes an output terminal 0. Each is charged to vP-vth4. Furthermore, the voltage at the output terminal O1 of the second power supply switching circuit 12 is raised to a higher voltage by capacitive coupling by the first capacitor 21 in synchronization with the output voltage of the first inverter 21; Since the voltage at the output terminal 02 of the second inverter 22 is OM silt at this level, it is not boosted. Therefore, in the period from time ti to time t2 when control signal B falls to a low level,
Second. The voltage at each output terminal 01 of the third power supply switching circuit 12.13 becomes approximately constant.

When the signal B falls to a low level at time t2, the transistor 8 in the second inverter 22 is cut off, so that the voltage at the output terminal O1 of the second power supply switching circuit 12 becomes the first voltage.
The output end of the inverter 21 O! The level is shifted sequentially in synchronization with the voltage. The level-shifted voltage at the output terminal O1 of the second power supply switching circuit 12 is rectified by the diode-connected transistor 23, and this rectified output voltage is input to the output terminal O1 of the third power supply switching circuit 13. For,
A boosted voltage is obtained at the output terminal 01 of the third power supply switching circuit 1s and the output terminal O- of the second inverter 21. During the period in which this boosted voltage is obtained, the second. Since each transistor 4 in the third power supply switching circuit J2+J3 is cut off, no current flows to pin 6.

Furthermore, when the voltage at the output terminal 01 of the second power supply switching circuit 1- exceeds the breakdown voltage of the diode 24 during reverse bias during boosting, this diode 24 causes breakdown. Third power supply switching circuit 12.13
Each output terminal O! The voltage is suppressed to a predetermined value, and it is possible to prevent each transistor from being destroyed due to an abnormally high voltage. Therefore, the breakdown voltage of the diode 24 is the same as that of the second and third power supply switching circuits J.
2*73, the breakdown voltages of each transistor in the second inverter 22 and the transistor 23, such as the sojunction breakdown voltage and the field induced junction breakdown voltage, are also set low.

Here, the high-level voltage at the output terminal 02 of the first inverter 21 is V(,2□), and the low-level and high-level voltages at the output terminal O1 of the second power supply switching circuit 12 are respectively vL(Jz
), vHClx), and the capacitances of the first and i2 capacitances 21 and 22 are C, , C, respectively. When the voltage at the output terminal 02 of the first inverter 21 becomes v(21), The formula holds true.

Cs (V(2,)+vL(h)) +c! vL(Jg
)=(Ct+Cs)Vn(Js)-(11Here, if α=91, vHClz) is expressed by the following formulaC.

be done.

(1+(X)Vb(zl)+V(2,)-(21■H(
1) -1+ke□ Therefore, v! 1(Jx) is determined by the value of the capacitance ratio α between C1 and C, and can be set within the range of the following formula in principle.

VL('Jl)<Va(71)<vL(h)+v(2t
) ”' (3) As a result, the substrate concentration is 7 x 10”
atoms/an3, gate oxide film thickness so o l,
1st when Pack Dart/Quias is 0 built. Second
．． Assuming that the threshold voltage Vth4(o) of each transistor 4 in the third power supply switching circuit 11a1m+'s is 0.8 corts, the threshold voltage Vth4(zs) of the transistor 4 when V'=+25&lt;・Rf−)−−Rt due to the Ias effect, therefore, v(J,)””p Vth4(2s) =25−3=22[&Rt]...(4) vL(Ji
)=vp'th4(25)=25-3=22Cd] ...(5), α=1, that is, C1""C
In the case of 2, h vH (J,) = 33 according to the above formula (2)
It becomes Z Ruto. At this time, the threshold voltage of the type MOS transistor 23 is approximately 1.2, J? due to the pack f-) bias effect. Due to the silt, the voltage at the output terminal 02 of the second inverter 22 becomes 31.8 &lt; after a certain period of time.

The period from time t3 to t4 and after t4 are the same operations as the period from time t1 to t4 and before t1, so the explanation will be omitted.

The above embodiment circuit is used in place of the power supply switching circuit 1 and inverter 2 of the ROM shown in FIG. V to 6, = +25d? When the voltage is applied, the voltage at the output terminal 02 of the second inverter 22 becomes, for example, 31.8 &lt;
Each transistor 15 enters the triode region, and the row lines 131~
13n has +25? applied to bin 6? The root will be output approximately 1-1.

In this way, if the circuit of the above embodiment is used in an EPROM, the problem of poor voltage efficiency as in the conventional case does not occur.

FIG. 6 shows the output terminal o of the second power supply switching circuit 12 in response to the power supply voltage Vp supplied to the bin 6 in the above embodiment circuit.
The peak voltage Vpz (J□) of , and the second inverter 22
This shows the change characteristics of the voltage (23) at the output terminal 02 of . The characteristics shown by the solid line here are those when the diode 24 is provided, and the characteristics shown by the broken line are those when the diode 24 is not provided. As is clear from FIG. 6, when the diode 24 is provided, the peak voltage vpg (1*) at the output terminal O1 of the second power supply switching circuit 12 is: The breakdown voltage Vlln of each transistor in inverter 22 and transistor 23 is also set to a lower constant voltage. Therefore, the diode 24 acts as a constant voltage circuit.

FIGS. 7(a) to (c) each show the above diode 240.
This figure shows an example of a constant voltage circuit that can be used instead. The circuit shown in FIG. 7(a) connects a field inductor diode 3 and a pair of resistors j and 2. J
The breakdown voltage can be set by the voltage of the diode 31. The same figure (bl is n enhancement type MOS) transistor 34
1 to 34n are connected in series, and the voltage at the output terminal O1 of the second power supply switching circuit 12 is n·Vlh (34).

However, Vth (54) is for each transistor 341 to 34n.
Assume that the threshold voltages are all equal.

In the same figure (c), the f-) oxide film is extremely thick (for example, 80 mm).
00X) Field MO8) Runnostar 35.

FIGS. 8(a) to 8(d) each show the above-mentioned No. 1. Second. Third
This figure shows the configuration of a power supply switching circuit that can be used in place of the power supply switching circuits 11.1□ and 13. Figure 8-(a
), (b) The circuits shown in each are one degradation type MOS.) Lanzostar 36 and two enhancement type MOS.) Lanzostar 36 and two enhancement type MOS.) Lanzostar 36 and two enhancement type MOS. 37, 38, and 39, and when the power supply voltage ■ is applied to the bin 6, the output terminal o is Vp 2
A voltage of Vthg (vth" is the threshold voltage of each of the two enhancement type MOS transistors 37? and 311) is obtained. Also, the circuits shown in FIG. type MOS
) transistor 36 and n enhancement type MOS
) by Lanzosta 391-39n or (
n+1 ) (D-enhancement type MOS transistors 39. to 39n+1, and the bin 6
When power supply voltage vp is applied to output terminal O1, vp-
nVthz (Vthz is the threshold voltage of each n enhancement type MOS Lanzostar 391 to 39n)
The following voltage can be obtained.

FIG. 9 shows the structure of another embodiment of the invention. In the embodiment circuit shown in FIG.
This is for rapidly increasing the drain voltage of the transistor 7 in the second inverter 22. Therefore, if the time required for the voltage at the output terminal 02 of the second inverter 22 to rise is not a particular problem, it may be omitted as shown in FIG. 9. In this embodiment circuit, the diode 24 as a constant voltage circuit is connected to the second inverter 2.
This diode is connected to output terminal 02 of P24.
By providing the output terminal 0 of the second inverter 22'
The voltage 2 is determined by the breakdown voltage of the diode 24 and remains constant regardless of the threshold voltage of the MOS transistor 23. Note that this diode 24 is connected to the output terminal O1 of the second power supply switching circuit 12 as in the embodiment shown in FIG.
You may also connect it to

In addition, a diode-connected MOS) transistor 23
The second. Third power supply switching circuit 1g, each output terminal 0 of 1g
In order to suppress the voltage drop at 1, it is better to have a smaller threshold b-value voltage, and as in the embodiments shown in FIG. 3 or FIG. 9, the threshold voltage is θ? It is preferable to use a type MOS transistor near the root (type MOS transistor) near the root, but this is because the normal enhancement type MOS transistor C pack gate bias is O? Any device having a rectifying effect can be used, such as a normal PN junction diode (the threshold voltage of 0.8 &lt;

In addition, Fig. 10 shows the pack P-) bias voltage 〆IVn
The graph shows the change characteristics of the threshold voltage Vth with respect to l, and the solid line shows a 1-type MOS transistor, and the broken line shows an enhancement-type MOS transistor. Here, the reason why the Vth of the enhancement type MOS (Lanzostar) changes greatly in the range of 〆lVml>2 is due to the influence of the channel angler.

In the semiconductor integrated circuit according to the present invention, since a rather high boosted voltage can be obtained, a high breakdown voltage structure is used for the transistor to which this high voltage is applied. Fig. 11 shows the element configuration of the transistor 4, 7, and 8 parts, Fig. 11 (a) is a plan view, Fig. 11 (b) is a cross-sectional view, and Fig. 11 (c) is a symbol diagram. be. In the figure -L
! is a p-type substrate, 51, 52.53 are n+ type drain regions, 54, 55.56 are male-type source regions, and 57 is a p-type substrate.
- type field region, 58 is the same conductivity type as the source and drain regions, and has a low concentration of inn- type low concentration regions, 59 is the first polysilicon wiring, 60 is the second polysilicon wiring, 61 is an At wiring, and 62 is an insulating film. As shown, each drain region 51, 52, 53 and each source region 54, 55 each have a direct field region 57.
The drain regions 51, 52, 53 and the source regions 54, 55
A reduction in the junction breakdown voltage due to contact between each and the field region 57, a dirt modulation junction breakdown voltage (Breakdo
wn voltage of the Field 1n
(Deduced Junction) can be prevented from decreasing.

〔Effect of the invention〕

As explained above, according to the present invention, the semiconductor integrated circuit has the function of boosting the power supply voltage supplied to the terminal shared for signals and power supply, and the boosted voltage does not exceed a certain value. can be provided.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a shared circuit, Fig. 2 is a circuit block diagram of an EPROM using the above circuit, Fig. 3 is a circuit block diagram of an embodiment of the booster circuit of the present invention, and Fig. 4 is a circuit diagram of an embodiment of the booster circuit of the present invention. FIG. 5 is a waveform diagram showing an example of the operation of the example circuit, FIG. 6 is a characteristic diagram for explaining the example circuit, and FIG. 7 is a diagram of the example circuit. 8 is a circuit diagram showing another example of a part of the circuit of the same embodiment; FIG. 9 is a circuit diagram of another embodiment of the present invention; FIG. A characteristic diagram for explaining the example circuit shown in FIGS. 3 and 9, and FIG. 11 is a characteristic diagram for explaining the example circuit shown in FIG.
FIG. 2 is a plan view, a cross-sectional view, and a symbol diagram showing the element configuration of a transistor in the example circuit shown in the figure. DESCRIPTION OF SYMBOLS 11... 1st power supply switching circuit, 12... 2nd power supply switching circuit, 13... 3rd power supply switching circuit, 21...
First inverter, 22...Second inverter, 20
...Oscillation circuit, 21...First capacitance, 2
2... Second capacitance, 23... lff1 no MO8) Lanzo star, 24... Diode. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 4 20

Claims (1)

[Claims] The present invention includes a terminal to which a power supply voltage is supplied from the outside, voltage boosting means for boosting the voltage supplied to this terminal, and constant voltage means for limiting the boosted voltage obtained by this means to a predetermined value. Features of semiconductor integrated circuits.