JPS60216626A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To attain high speed operation of a dynamic circuit by impressing an output of a delay circuit to the 2nd and 3rd field effect transistors (TR) provided to a reference potential and one terminal and a gate of the 1st field effect TR. CONSTITUTION:An insulation gate type field effect TRQ3 keeps unsaturated region and the level of an output and a node 2 rise almost in synchronizing with a clock input phi. The level of the output of the delay circuit, that is, that of a node 3 rises with a prescribed delay from that of the node 2. When a potential of the node 3 rises, insulation type field effect TRs Q2, Q4 are conductive and a clock input phi' is at a low level and the insulation type field effect TRQ1 is in the nonconductive state, then the level increased rapidly of the potential of the node 1 dops to a common potential at first. The insulation type field effect TRQ3 is nonconductive and the level decreases to the common potential level by the conduction of an insulation type field effect TRQ4. The potential of the node 2 rises rapidly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse generation circuit, and more particularly to a pulse generation circuit using an insulated gate field effect transistor.

Note that all the explanations below refer to a typical MOS transistor (hereinafter referred to as MO8T) and an N-channel MO transistor.
8T, the high level is the logic "1" level, 1),
The low level is the logic "'0" level. However, circuit-wise, the P-channel MO8T is essentially the same.

The operation of a dynamic integrated circuit using MO8T is divided into an active operation period and a reset/precharge period, and in each period, the external input that drives the circuit or the internally generated clock timing waveform is used as the active operation timing waveform and This will be called the reset/precharge timing waveform.

The former waveform is related to the performance of the original circuit operation, and the latter waveform has the function of resetting the circuit end state of the previous active operation period and making preliminary settings for the next active operation period. When transitioning from the reset/precharge period to the active operation period or from the active operation period to the reset/precharge period, it is important that the active operation timing waveform or reset/precharge timing waveform rises immediately after each transition. Desirable for obtaining operation.

In each case, if the reset/precharge timing waveform or the activation timing waveform has not fallen sufficiently (in most cases, below the threshold voltage of MO8T), the circuit will consume DC current or power. Put it away. In practice, the active operation timing waveform or the reset/precharge timing waveform can hardly be activated until the reset/precharge timing waveform or active operation timing waveform has reached a sufficiently low level. . If a high-speed active operation timing waveform or reset/precharge timing waveform is required so that the transition occurs and the waveform immediately rises, the reset/precharge timing waveforms or active operation timing waveforms connected to the common circuit stage are reset respectively. - This requirement can be met if the function is achieved and the signal falls within the precharge period or active operation period.

The purpose of the present invention is to provide a circuit that generates an output waveform that satisfies the above requirements, rising υ synchronously when receiving an input signal pulse, and falling with the pulse width determined within the circuit within a range shorter than the input signal pulse width. It is to provide. .

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 shows a circuit diagram of the principle of the present invention, and FIG. 2 shows waveforms at each node in FIG. A clock input φ and the positive inverse of φ are applied to the circuit. Before the clock power φ rises, the voltage is normally at the vDD level, node 1 is at the (■ − dark value voltage) level, and the bootstrap capacitor CF between nodes 1 and 20 is at the (vDD−threshold voltage) level. ) is charged to the level. When φ rises, the level of node 1 rises due to capacitor CF [V - threshold voltage DF and \, CI is the capacitance of node 1, ! >, VZ is the voltage at node 2. ] MO8TQ3 maintains the non-saturation region, the output, node 2 rises almost synchronously with φ, and if the required pulse width of the output is longer than the rise time of φ, the final level equal to φ (usually vDD) reach up to.

Node 2 is also connected as an input to a delay circuit as shown in FIG. 1, so that the output of the delay circuit, node 3, rises after a time Td from node 2, as shown in FIG. . When node 3 rises, MO8TQ2 and MO8T (
j4 becomes conductive, but at this time, since ■ is at a low level and MO8TQI is non-conductive, the level of node 1, which has risen above, is first rapidly lowered to the ground potential. Therefore, MO8TQ3 then becomes non-conductive, and the node 2 becomes a floating potential, which quickly drops to the ground potential level as MO8TQ4 becomes conductive. The operation from node 3 rising to output and node 2 falling to the ground potential is rapid, and the width Td of the period during which node 2 is rising is the delay time determined by the delay circuit. matches.

Therefore, at node 2, the desired output waveform is obtained, which falls rapidly while maintaining the width determined by the delay circuit within a pulse width range shorter than the clock input φ.

Next, a specific example of the circuit of the present invention is shown in FIG.

A delay circuit is composed of six MO8Ts from MO8TQ5 to MO8TQIO. FIG. 4 shows the waveform of each node in FIG. 3. Clock power T is normally set to VDD level, node 4 is set to ground potential, node 5 is set to (V-threshold voltage) level, and node 3 is set to D ground potential. When φ rises, the output node 2 rises in synchronization, MO8TQ5 becomes conductive, and after j has sufficiently decreased, the node 4 rises to the (DD-threshold focal voltage) level. When node 4 exceeds the threshold voltage, MO8T
Q8 conducts, and at this time Oka decreases and MO8TQ7
changes from a non-conducting state or a state close to it to a non-conducting state, so that the node 5 decreases from the (VDD - threshold voltage) level to the ground potential. M
O8TQ9 becomes conductive when φ increases, but MO8TQ1
The dimensions of MO8TQIO (1°, where W is the channel width and L is the channel length) are adjusted so that node 3 does not rise until 0 becomes non-conductive or close to it.
Make it larger than TQ9. Therefore, after node 5 has fallen sufficiently, node 3 passes through M'OS T Q 9, and (■
-threshold voltage D (voltage) level. When node 3 rises above the threshold voltage, the output, node 2, rapidly drops in level as described above. As shown in Figure 4, the time from when node 2 rises until when node 3 rises is from MO8TQ5 to M
This is the delay time Td due to the delay port composed of six M08Ts of O8TQIO, and this corresponds to the width of the rising period of the output node 2. The delay time TdO value is M
It can be adjusted by taking the dimensions of O8TQ5νMO8TQ8 and MO8TQ10. If the dimensions of MO8TQ5 rMO8TQ8 are made smaller and the dimensions of MO8TQ10 are made larger, T
The direction is to lengthen d.

In the circuit of FIG. 3, the DC current from the vDD power supply only flows through MO8TQ9 during the delay time Td and is kept small, so this circuit can be operated with low power.

To illustrate the effects of the circuit according to the invention, reference is first made to the circuit of FIG. This circuit is part of the timing generation circuit of the MO8 memory integrated circuit.
It has a function of receiving TTL and generating activation timing φ of the address inverter buffer and reset/precharge timing P for the entire memory integrated circuit.

FIG. 6 shows the operating waveforms of each node in FIG. 5. TTL level clock "The period during which TTL is low level corresponds to the active operation period, and the period during which it is high corresponds to the reset/precharge period. When φTTL is at high level, that is, in the sufficiently latter half of the reset/precharge period, node 1. Node 9 is (VDD-
threshold voltage) level, node 3, node 7, node 8 are at ground potential, node 2, node 60 level is equal to, MO8
Of course, the size of TQ3 is larger than that of MO8TQ2, so that it is less than the threshold voltage.The effect of the bootstrap capacitor OF2 between node 4 and corner point 5 is ■It rises above the DD level, where C4 is the capacitance of node 4, and VB is the voltage of node 5.] MO8TQ7 is driven to the non-saturation region, and node 5 is at V level. .' TTL Ka A Ly Hair Color D When moved to low level 4 and enters the active operation period, MOS T
Q 3 p M 08 T Q 5 is non-conductive,
Due to the effect of the boot strap capacitor CFI between node l and firj point 2, node 1 rises above the vDD level (where C1 is the capacitance of node 1) and Vt is the capacitance of node 2. voltage. ), MO8TQ2 is driven to the non-saturation region, and node 2 rises to the V level, then node 3 rises to (■ DD - positive value voltage le).The dimensions of MO8TQ8 are MO8TQ7. If the voltage is set sufficiently large and node 3 rises, P will move to a low level below the dark value voltage.

When P decreases, MO8TQ13 and MO8TQ14 are no longer conductive, and node 8 becomes (vDD-) through MO8TQ12.
Then, through MO8TQ15, node 9 falls from the charge level of (vDD-threshold voltage) to ground potential. Boot between node 6 and node 7
Strap capacitor CF3 increases until node 9 falls (■
DD - Charged to positive value voltage le. When node 9 falls and MO8TQII becomes non-conductive, due to the effect of CF3, node 6 rises above the ■DD level and CJ■ = x
v.

[V - threshold voltage +. 6+CF3 D Here, C6 is the capacitance of node 6, and ■ is the voltage of node 7. ), driving MO8TQIO to the non-saturation region,
φ1 rises to the vDD level.

φ, activates the address impark buffer and memory circuit operation begins.

When the active operation period ends and #TTL transitions to high level and enters the reset/precharge period, M08TQ3
．． MO8TQ5 is conductive, and node 2g and node 3 are at a low level below the threshold voltage, respectively, and MOSTQ
4 becomes non-conductive, it shifts to ground potential. When node 3 goes down, MO8TQ8 becomes non-conducting and P becomes vDD due to the effect of the bootstrap capacitor CF2.
' and rises. Along with this, since MO8TQ12 is already non-conductive, node 8 reaches the ground potential through MO8TQ13! p, MO8TQ15 becomes non-conductive and node 9 is charged through MO8TQ14 (VDD-
threshold voltage) level. Node 6 and node 2 are already at a low level below the threshold voltage through MO8TQ9, MO8TQ10 is in a non-conducting state, and as node 9 rises, φ1 immediately reaches the ground potential. The circuit operation of FIG. 5 is as described above, but due to the circuit operation of the memory, it takes time (t, + t, +t, tent, tent
s).

The circuit in Figure 5 is a TTL level human clock # TTL
Then, the MO8 level inverted output is obtained at node 2, and the timing φtap is generated based on this.
), gl The dimensions of MO8TQ3 must be large enough with respect to MO8TQ2 so that node 2 is at a sufficiently low level below the 1-value voltage for gl TTLO high level. 2) The dimensions of MO8TQ3 need to be considered to fit within the $TTL input capacitance limit, and 3) The dimensions of MO8TQ2 are small due to the addition of standby vDD power supply current standards. Normally, it can be suppressed, so if we set node 2 directly to φ,
Connecting to the gate of MO8TQ8 cannot be practically adopted because the load is too heavy and the speed decreases. Therefore, as shown in Figure 5, a buffer circuit is inserted between node 2 and the φsyp generation stage to lighten the load on node 2, but φ1 in Figure 6 passes through the response of five stages of inverters. In order to obtain high-speed operation of memory, it is required to shorten this time.

FIG. 7 shows a circuit in which the circuit according to the present invention in the dotted line frame is added to the circuit in FIG. 5, and the gates of MO8TQ13 and MO8TQ14 are replaced with P in FIG. Timing P. This is a circuit with a closed configuration. FIG. 8 shows the operating waveforms of each node in FIG. 7.

Limiting the content that differs from the description of FIGS. 5 and 6, the circuit operation of FIG. 7 will be explained in conjunction with FIG. 8 as follows. Timing P. Rise in synchronization with FiP, P
It falls with a pulse width determined within the O generation circuit and reaches the ground potential within the reset/precharge period.
' Immediately before TTL transitions to low level and enters the active operation period, MO8TQ13 and MO
8TQ14 is non-conductive. d When TTL becomes a low level, node 2 and then node 3 rise, and P shifts to a low level below the threshold voltage, as in Figure 5, but since MO8TQ13 is non-conductive, node 1 rises. 2 rises and through MO8TQ12, node 8 becomes (vDD-
threshold voltage) level.

Since MO8TQ14 is also non-conducting, when node 8 rises above the threshold voltage, node 9 immediately transitions from a charge level of (V - threshold D voltage) to ground potential. Between node 2 rising and node 9 falling, node 6 rises to the (VDD - threshold voltage) level through MO8TQ9, and the bootstrap capacitor CP3 between nodes 6 and 70 also rises to this level. charged to the level. When node 9 goes down and MO8TQII becomes non-conductive, CF
Due to the effect of 3, the node 6 rises above the ■DD level, drives MO8TIO to the non-saturated region, and φ1 rises to the ■DD level. The memory circuit operation starts with the rise of φ, but at the same time MO8TQ26 becomes conductive.
At this time, P shifts to a low level and MO8TQ27 is almost non-conductive, so φ2 begins to rise (■D
D-threshold voltage) level is reached. Node 13 due to φ2
is at the [■DD-2×(threshold voltage)] level, node 12,
Node 14 leads to ground potential. Also, node 11 is MO8TQ
Through 18, it becomes a low level below the same threshold voltage as P,
The bootstrap capacitor CF4 between nodes 10 and 110 is charged to V -2X (threshold voltage) and D .

When OkaTTL becomes high level and enters the reset/precharge period, node 29 and then node 3 fall, and the process is the same as in Fig. 5 until P rises, but when P rises, CF
4, the level of node 10 rises to (V −
2X (threshold voltage) + D where CIO is the capacitance of node 10 and V+t is the capacitance of node 1
1 voltage. ], MO8TQ18 maintains the non-saturated region and rises in synchronization with poUp and t't'x.

The dimensions of MO8TQ27 are set sufficiently larger than those of MO8TQ26 so that when P rises sufficiently, φ becomes a low level below the threshold voltage. Therefore, when Po rises sufficiently, ≠2 becomes a low level and MO8TQ21
, MO8TQ22 is almost non-conductive, and as described in the explanation of FIG. 3, MO8TQ20 to MO8TQ2
While the circuit consisting of 6 MO8Ts of 5 responds, P
I) ij P and y maintain the same cylinder level, and as a result, as node 14 rises, MO8TQ17, MO8
TQ19 becomes conductive and Po quickly shifts to ground potential.

While Po is at a high level, node 8 rises to ground potential, node 9 rises to the (■DD-threshold voltage) level, and φ
1 to ground potential and prepare for the next active operation period, the width of the high level period of Po is set from MO8TQ20 to MO8T.
It is necessary to adjust and set the dimensions of MO8T of the circuit composed of six MO8Ts of Q25.

As shown in Figure 8, the time at which φ1 begins to rise after TLL goes to a low level and enters the active operation period is (tl + t4 + ts), compared with Figure 6. It is shortened by (tz+tm). This is MO8TQ
I 3, MO8TQ14 gate at timing P. This is because when the input node 2 rises during the active operation period, the nodes 8 and 9 immediately respond. that's all,
From the explanations in FIGS. 5 to 8, it is possible to use the timing waveforms generated by the circuit of the present invention to speed up the active operation period in a MOS memory integrated circuit that operates in response to a TTL level human clock. An example was shown that it can be measured.

As described above, according to the present invention, there is a circuit that generates an output waveform that rises in synchronization with the input signal pulse and falls with the pulse width determined within the circuit section within a range shorter than the input signal pulse width. This is effective for high-speed operation of dynamic circuits using MO8T.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the principle of the present invention, and FIG. 2 shows its operating waveform diagram. FIG. 3 shows the specific circuit shown in FIG. 1, and FIG. 4 shows its operating waveforms. FIG. 5 is a conventional pulse generation circuit diagram, and FIG. 7 is a pulse generation circuit diagram according to an embodiment of the present invention. 6 and 8 are operational waveform diagrams of FIG. 5 and FIG. 7, respectively. In the figure, Qt'Qt is a transistor that constitutes an inverter, Qs' Q4 is an output circuit transistor, and CF
indicates a Pootstrap capacitor. Representative Patent Attorney Shinmo Uchihara, L 2nd 3rd Leather 4 @ Unyiro

Claims (2)

[Claims] (1) The first pulse is applied to one of the first field effect transistors.
In addition to the end, an Nc2 field effect transistor is provided between the other end of the M1 field effect transistor and the reference potential, and the other end of the first field effect transistor is used as an output terminal and as an input terminal of the delay circuit. a third field-effect transistor is connected between the gate and a reference point, and the gate is provided with means for precharging the gate of the first field-effect transistor at least during the period in which the first pulse is inactive; A pulse generating circuit, characterized in that a field effect transistor is connected, and the output of the delay circuit is applied to each gate of the second and third field effect transistors. (2) at least two external pulses as the first pulse;
The precharging is performed by a second pulse using a pulse obtained through an inverter in the stage, and as the second pulse, the external pulse is combined with a pulse obtained through an inverter in at least one stage and the output terminal. The pulse generating circuit according to claim 1, characterized in that the pulse generating circuit uses a pulse obtained by