JPS60215249A - Computer peripheral unit incorporating multi-task control element - Google Patents

Abstract

PURPOSE:To enable even another peripheral input/output element having the priority set at a lower level to receive the support, by accepting the task switching interruption requested by a multi.task control element having the priority of a higher level by a master CPU and requesting a normal interruption to the master CPU. CONSTITUTION:Multi.task control elements 11-1m of a multi.task control element group 1 serve as independent function elements which perform plural task controls to be executed by a master CPU2 by means of elements except the CPU2 and requests an interruption to the CPU2 at a time point when the task switching is needed. Each of the elements 11-1m has the priority, and the elements 11 and 1m have priorities of the highest and lowest levels respectively. If an applicable task exists among those tasks within a control range of upper control elements, the upper elements inhibit the interruption effective for task switching of lower elements. When no applicable task exists no more, the tasks within a control range of lower control elements are applicable.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a computer peripheral device having a built-in multi-task control function that is effective for a microcomputer system management program.

<Prior art> In a microcomputer system, one C
In order for the PU to execute multiple processes at the same time,
Multi-task control by the OS (operating system) of the computer system is required.

When a multi-risk control element and other peripheral input/output elements are combined to form a system, an interrupt control line ( IEI.

By simply connecting an IEO), it was possible to control the interrupt priorities of multi-task control elements and peripheral input/output elements to the master CPU.

However, due to internal memory limitations of multi-task control elements, there is a limit to the number of tasks that can be managed simultaneously by one control element, so in order to manage a large number of tasks, multiple multi-task control elements must be Control line (IEI, I
EO, LEO) must be used for cascade connection. However, when a cascade-connected multi-task control element with a higher priority level is executing a task under its control, it prohibits interrupts from lower-level multi-task control elements via the interrupt control line. Therefore, if other peripheral input/output elements are directly connected to the lower side of multiple cascade-connected multi-task control elements, the problem arises that interrupt requests from the peripheral input/output elements are not properly accepted by the mask CPU. occurred.

Purpose> The present invention is intended to solve the problem of interrupts to the master CPU from other peripheral input/output elements connected to the lower side of the plurality of multi-task control elements mentioned above. Even for other peripheral input/output devices connected to the side, the master CPU accepts task switching interrupts requested by the multi-task control device on the upper side, and if they are not currently being executed, they will normally issue interrupts to the master CPU. The purpose is to make it possible to request and receive interrupt support.

<Example> An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of a microcomputer system. Element group 1 is a multi-layer device according to the present invention.
Multiple cascaded multi-task support processors to achieve task control.
Like other peripheral devices, input and output are provided in the form of bare hands. Hereinafter, each device in this element group will be referred to as a multi-task control element. Master CPU2, program memory (ROM)8. Data memory (RAM) 4 and other I
The peripheral input/output elements 5, such as /, are also included in a well-known microcomputer system, and are
It is interconnected with the task control element group 1 via a bus 6. The program memory 3 independently programs an initialization program for the multi-task control element group 1 and a plurality of tasks. Further, interrupts of the peripheral input/output elements 5 are controlled from the multi-task control element group 1 via the peripheral input/output element interrupt control circuit 7.

Each element 11 to 1m of each multi-task control element group 1
are independent functional elements that manage a plurality of tasks executed by the master CPU 2, respectively, by a device other than the master CPU 2, and have task scheduling functions (execution in order of priority or time-sharing) and management of the same control element. Synchronization and communication function between the tasks below (sends and receives data between each task, determines task execution relay and execution restart), memory management function (prohibits duplication of memory area used by each task), clock function (time setting using a built-in timer), etc.

Each of the multi-risk control elements 11 to 1m manages up to eight tasks under its own management. Further, each of the elements 11 to 1m requests an interrupt from the master CPU 2 when it becomes necessary to switch tasks. Each of the elements 11-1m has an interrupt priority, with element 11 being the highest and element In being the lowest. If there is an executable task among the tasks managed by the higher-level element, the higher-level element prohibits interrupts for switching the tasks of the lower-level element. If there are no executable tasks, lower-level interrupts are enabled, so tasks within the management of lower-level elements become executable. (In order to match the priority of each task with the interrupt priority of each element, (It is assumed that high-priority tasks are registered in higher-order elements and lower-priority tasks are registered in lower-order elements.) Hereinafter, we will add an explanation of the individual multi-risk control elements 11 to 1m. Figure 2 shows multi-task control element 11=1
FIG. 3 is a block diagram showing an example of the internal configuration of M.

The multi-task control elements 1□ to 1m are provided with a register group accessible from the master CPU 2.

Command-parameter register CPIO is masked by C
Parameters input when executing commands from PtJ2,
Retains parameters to be output after execution. The command/status register CN5T functions as a register for writing commands during writing, and as a register for storing execution information of executed commands during reading. The new stack pointer register SPN has two functions. 1
First, the value of the stack pointer of the task that will be newly executed is output as task switching information.

The other is input to save the current stack pointer if the task is relayed while still in the running state during 6 executions. Also, the old stack pointer register SPB
is a register for inputting the value of the stack pointer of the task that has been in the execution state as task switching information.

The mask interrupt control register MIC is a register for controlling the generation of interrupts to the master CPU 2 in the present elements 11 to 1m, and the interrupt vector register MIV writes an interrupt vector name value. Data register PID, P2
D and P8D are registers for data input/output of port 1, port 2, and port 8. port 1 and port 2
is an 8-bit input/output port whose data input/output direction can be set bit by bit by program;
This is a bit input port. Port 3 can be set to an event input (a task in a stopped state is moved to a ready state by transition of an input signal to port 3) by a program.

The above register group is accessed by the master CPU 2 and used for mutually exchanging information between the present elements 11 to 1 m and the master CPU 2.

Data bus interface DBI, bus timing generation/control circuit BTGC, interrupt control circuit INTC
is provided as an interface circuit with the master CPU 2. The IEI (interrupt enable input) terminal and IEO (interrupt enable output) terminal in the interrupt control circuit INTC, and the LEO (lower element enable output) terminal of port 3 (vote write register P3D) will be described later.

The task control block TCB (1-8) is a memory area for saving the state of a task. Each control element 11-1
m can handle up to eight tasks. Each T
As shown in Figure 3, the CB block has the following information: task status ■, task priority ■, number of task connected to ready Q first ■, number of task connected to ready Q later ■, task It has an area for storing the start address (■) of the work memory occupied by the work memory, its size (■), the mailbox number (■) in use, and the stack pointer value (■) during task execution relay.

The mail box MBX is a buffer memory area provided so that data can be exchanged between tasks managed by the same element.

The memory map MEMMAP is a memory area for managing work memory, and for example, 32
Consists of bytes. It is possible to manage work memory in units of 256 bytes using the memory map MEMMAP. When the work memory is not in use, the bit corresponding to that area is 0#, and when it is occupied, the bit is set to 11''.

The timer TM is used for time-sharing processing (task children 11 to 11 with the same priority).
The system clock area SCA is a memory area that stores time data such as 2 minutes and 2 seconds counted by the output of the timer TM.

The internal arithmetic control circuit C0NT is a logic arithmetic unit (ALU).
), a ROM that stores programs for the devices 11 to 1m;
It has a RAM for temporary storage, a flag register for various controls, and the like.

Multi-task control elements 11 to 1 from master CPU 2
Access to one of the multi-tasking control elements 11 of m is done by a command to the addressed control element 11 issued from the executing task, and by a command to the addressed control element 11 from the multi-tasking control element 1i to the master CPU 2. Access is based on the generation of interrupt signals by the multi-tasking control element 11. FIG. 5 is a diagram showing command types, input parameters, and output parameters.

The basic operation is as follows. It is assumed that the state of each task is already stored in the task control block TCB.

The multi-task control elements 11 to 1m select the task with the highest priority from the tasks in the executable state, and prepare the registered value of the stack pointer of that task in the new stack pointer register SPH. After preparing the value of the stack pointer, the multitasking control element 11
~1m sets an interrupt (IP) flag in order to generate an interrupt to the master CPU 2. Master CPU
When 2 receives an interrupt, it executes the interrupt routine corresponding to the multi-task control element (one of 11 to 1m) requesting the interrupt, and
Loads the value of the stack pointer set in the task control element into its own stack pointer, pops the initial value of the register written in advance from the stack, and rewrites the register. Then, the designated task is executed under the control of the master CPU 2.

The multi-task control elements 11-1m are in a waiting state until there is a command input from the task being executed or until there is an interrupt due to an input to the timer TM or port 8. For example, if a command is input here, the command to the multi-task control elements 11 to 1m is analyzed and the command is processed. If this command includes a task switching function, the value of the stack pointer of the next task to be switched is stored in the new stack pointer register S.
PN and sets the interrupt (IP) flag to 1 to request an interrupt from the master CPU 2.

When this interrupt is accepted, the master CPU 2 stops executing the task currently being executed, and reads the stack pointer value of the task to be executed next from the multi-task control elements 11-1m.

The internal processing of the individual multi-task control elements 1 to 1m will be explained in more detail below with reference to flowcharts.

FIG. 6 is a flowchart illustrating the operation of the main routine of the multi-task task control elements 11 to 1m (7).

7 to 21 are flowcharts explaining the operation of the processing routine according to each command θ to 14, FIGS. 22 and 28 are flowcharts explaining the operation of the task switching routine, and FIG. Flowchart explaining the operation of the interrupt processing routine, No. 25
The figure is a flowchart illustrating the operation of a flotine for explaining the operation of the interrupt processing routine by the timer TM.

In FIG. 6, when the system is powered on, the multi-task control elements 11-1m perform a reset operation to initialize each internal functional element (step 2). Then, it waits for a command to be written from the master CPU 2 to the command/status register CN5T (step ■). When the commands are written, command processing corresponding to each command code is performed (step ■).

Command 0 (command name: INIT, jJT diagram flowchart) initializes the multi-task control element 11. This command is a vector value output to the master CPU 2 when the multi-task control element tl-im generates an interrupt to the master CPU 2.
This is a command for registering the start address and size of the work memory area managed by the task control elements i1 to 1m, and the priority of the task for each task.

When this command is executed, it will check the input data for errors (step ■), and if there is an error in the input data,
Error code in command/status register CN5
Set to T (step ■).

If the input data is correct, the command/parameter/
Write the interrupt vector value to the interrupt vector register MIV from the data sent to register CPIO (step
), and the memory a map MEMMAP is initialized based on the data of the start address of the work memory area and its size (step 2). Then, each task control block TCB is created based on the written priority of the task (step 2). Then, they are arranged in descending order of priority to form a ready Q (step ■). At this time, 0.0 in the task control block TCB. ■Order by. After generation, set the normal completion code to command/status register CN5T (step [phase]),
The T, S K CHG flags of the internal arithmetic control circuit CONT are reset (step @), and the process returns to the main instruction shown in FIG.

Error code in command/status register CN5
When set to T, the TSKCHG flag is similarly reset and the process returns to the main routine.

Command 1 (command name: TSTR, flowchart in Figure 38) executes the initialized multi-task control elements 11 to 1.
This is a command to move m to an execution state.

This command 1 checks whether the process of command 0 has been executed (step @), and only if it has been executed, executes the task connected to the beginning of ready Q (the task with the highest priority). TSKCH to move to state,
The G flag (control flag of the internal arithmetic control circuit C0NT) is set (step ■), and the process returns to the main instruction shown in FIG. If it has not been executed, set the command/status register (step [phase]) and return to the main routine.

The above commands o, 1# and multi-risk control element 11
~I'm write information is, for example, the program shown in Figure 1.
It is stored in advance in the initialization program of the memory 3, and the program can be changed according to the task content, and each multi-task control element 11~1mg! This allows various initialization settings to be made.

Command 2 (command name: TCRT, time chart in Figure 9) is a command for arbitrarily generating a task after initial settings, and the number of the task to be generated and its priority are set as input data from the control elements 11 to 11. 1m command parameter register CPIO.

When this command 2 is executed, the input data is checked for errors (step 0), and if there is an error, an error code is written to the command/status register CN5T (step [phase]).

If there is no error, a task control block TCB for the task specified by the input data is generated (step @).

Task status in task control block TCB
(see Figure 3) includes the following four flags.

The RUN flag indicates that the task is in a running state.

The READY flag indicates that the task is in the ready state and connected to ready-Q.

The PENDW flag indicates that the device is waiting to receive a message.

The 5TJSPRNn flag indicates that the task is in the stopped state.

When generating the above task control block TCB (step 0)
, and simultaneously sets the READY flag therein.

Then, the tasks are reconnected to the ready Q in descending order of priority (step [phase]). Next command/status -
To set a normal completion code in register CN5T (step [phase]), TSK is used to compare the priorities of the task in execution state and the task connected to the beginning of ready Q.
The CHG flag is set (step [phase]) and the process returns to the main routine of FIG.

Command 8 (command name: TDEL, jJl time chart in figure 0) is a command for erasing unnecessary tasks, and is executed using the number of the task to be erased as input data.

Inspecting input data for errors (step [phase])
If there is an error, an error code is set in the command/status register CN5T (step [
phase]), the process returns to the main routine of FIG.

If there is no error, in order to release the work memory occupied by the task to be erased, read the occupied memory start address O and the occupied memory size in the task control block TCB of this task, and based on this data. II The corresponding area on the memory map MEMMAP
Clear OII (step [phase]). Next, if this task is in the ready state, the task control block TCB of the task to be erased is separated from the ready Q and step [
phase]), clear everything in this task control block TCB (step [phase]). Once completed, a normal completion code is set in the command/status register CN5T (step [phase]) and the process returns to the main routine.

Command 4 (command name: TR5M, flowchart in FIG. 11) is a command for bringing a waiting or stopped task with a task number specified by input data into a ready state (restartable state). Execute the task number as input data.

When command 4 is executed, the input data is first checked for errors (step [phase]), and if there is an error, an error code is set in the command/status register CN5T (step [phase]). ), return to the main routine.

If there is no error, the PENDW flag or 5USPEND flag of the specified task is reset, the REA DY flag is set, and this task control block TCB is set to Ready Q in order of priority of the task.
Connect to (step [phase]). Then, set the normal completion code in the command/status register CN5T.
Set the TSKCHG flag to compare the priorities of the tasks connected to the top of the task. Step 0) Return to the main routine.

Command 5 (command name: TSPD, flowchart in FIG. 12) is a command for bringing a task in a running or ready state with a task number specified by input data into a stopped state.

When this command 5 is executed, the input data is checked for errors, and if there is an error, an error code is set in the command/status register CN5T and the process returns to the main routine (steps [phase], [phase]).

If there is no error, first, it is checked whether the input data specifies that the task that is in the stopped state is made ready (restarted) by the input signal (external event) from port 8 (step [ phase]). If no external event is specified, skip to step @ processing. If specified, checks whether another task is already using the external event (
Step [phase]), if used, sets an error code in command/status register CN5T (step [phase]) and returns to the main routine. If not used, enable internal interrupts due to transitions of input/output signals of port 8 (step [phase]).

In other words, by setting the input data of this command 5, it is possible to perform bathing in the kL building ) or the READY flag (if it is in the ready state)
and set the 5USPEND flag (step 0). Once completed, a normal completion code is set in the command/status register CN5T (step [phase]). Then, considering the case where the specified task is in the ready state, this task is separated from the ready Q, and the task control block T connected to the ready Q is
The CBs are rearranged again in priority order (step O), the TSKCHG flag is set to compare the priorities of the running task and the task connected to the beginning of ready Q (step [phase]), and the main Return to routine.

Command 6 (command name: TPRI, flowchart in FIG. 13) is a command for changing the priority of the task number specified by the input data.

In checking whether there is an error in the input data (step ◎), if there is an error, set the error hood in the command/status register CN5T (step @
) Return to main routine.

If there is no error, the priority ■ (see FIG. 3) in the task control block TCB of the designated task is rewritten to the value of the changed priority of the input data (step @). Next, the task control blocks TCB connected to the ready Q are rearranged in priority order (step @)), and a normal completion code is set in the command/status number register CN5T (step @). Then, set the TSKCHG flag to compare the priorities of the running task and the task connected to the beginning of ready Q (step @).
, return to the main routine.

Command 7 (command name: TSLI, flowchart in FIG. 14) is a command for limiting the mask CPU occupation time of a task group having a priority specified by input data. That is, this command specifies time-sharing processing of tasks with the same priority. Time-sharing processing is effective only when there is no ready task with a higher priority than the specified priority. If there is a task in the ready state with a higher priority, that task will be executed and time-sharing processing will be disabled, but if there is no task with a higher priority, then it will be enabled.

When this command 7 is executed, first, the input data is checked for errors (step 0). If an error is detected, an error code is set in the command/status register CN5T (step @) and the process returns to the main routine.

If no error is detected, it is determined whether the input data is a specification for canceling time-sharing processing (step @). In case of cancellation, internal arithmetic control circuit C
Clear the time division control registers 5LICNT and SL I PRI in 0NT to 10'' (step [phase], o). If the input data specifies new time division processing settings, the task is The CPU occupation time is set in the control register SL I CNT (step 0), and the priority of the task that performs time-sharing processing is set in another control register 5LIPRI (step 0).

And finally the command/status register CN5T
Set the normal completion code to (step ■) and return to the main routine.

Command 8 (command name: C3ET, flowchart in FIG. 15) is a command for setting the time on the clock provided in the multi-task control elements 11 to 1m.

From master CPU2 to control element 1. ~ Commands within 1m
Write hour 2 minutes 1 second data as input data to parameter register CPIO and execute the command.

The input data is checked for errors (step Φ), and if an error is detected, an error code is set in the command/status register CN5T (step [phase]), and the process returns to the main routine.

If there is no error, data for hours 2 minutes and 1 second is transferred to the system clock area SCA (step O). Then, a normal completion code is set in the command/status register CN5T (step 0) and the process returns to the main routine.

This clock is kept ticking by a timer interrupt routine to be described later.

Command 9 (command name=CGET, flowchart in FIG. 16) is a command for reading the current time from the above clock.

When this command 9 is executed, the hour 1 minute 1 second data from the system clock area SCA is transferred to the command parameter register CP accessible from the mask CPU 2.
Moved to IO. After the transfer, a normal completion code is set in the command/status register CN5T (step [phase]) and the process returns to the main routine.

Command 10 (command name: MALC, flowchart in FIG. 17) is to select a work of the size requested by the task executing the command from the work memory area managed by the multi-task control element 11-1m. - This is a command that allows the use of memory. The number of work memory required for the command exposure parameter register CPIO (
256-byte unit) and execute the write command.

When command 10 is executed, error detection of input data is performed (step [phase]). If an error is detected, an error code is set in the command/status register CN5T (step O) and the process returns to the main routine.

If no errors are detected, the memory map MEMMA
Examine P and check whether the requested work memory is free (step [phase]). If there is no free space, command/status register CN5T
Set a memory-unoccupied code to (step o),
Return to main routine. If a free area is found, the corresponding bit on the memory map MEMMAP is set to "1" by the size requested by the task that executed the command (step). Then, set the respective values in the occupied memory start address ■ and occupied memory size ■ areas (see Figure 3) in the task control block TCB of the task that executed the command (step [phase]), then command Φ Occupied memory for parameter register CPIO
Write the start address (step O). If written,
Set the normal completion code in the command/status register CN5T and return to the main routine.

Command 11 (command name: MREL, flowchart in FIG. 18) is a command for releasing the occupied work memory area.

If the task that executed command 11 does not occupy the work memory (step O), an error code is set in the command/status register CN5T (step [phase]) and the process returns to the main routine.

If the new work memory is already occupied, the memory map MEMMA is created by referring to the values of the occupied memory start address ■ and occupied memory size ■ registered in the task control block TCB of the task that executed the command.
The corresponding bit on P is reset to '0' (step @).Then, the occupied memory start address ■ and the area of occupied memory size O in the task control block TCB are cleared (step [phase]).Final A normal completion code is set in the command/status register CN5T (step @), and the process returns to the main routine.

As mentioned above, when requesting memory from a task, the multi-task control element II ~ 1m requires Tecomant 1.
0 (memory exclusive command l', MALC) is executed. Also, if the memory used by a task is no longer needed and you want to release it, use command 11 (memory release command, MR
Execute EL).

In this way, the multi-task control elements 11 to 1m can control the pre-registered 64 by using these commands 10.11.
It has the function of determining whether the work memory area up to 2 bytes is in use in units of 256 bytes, searching for a free area of the size requested by the task, and allocating it to the task.

This function is effective in effectively utilizing limited memory space among multiple tasks, and is also useful in preventing multiple tasks from using the same memory area overlappingly. The setting of the work memory area for the multi-task control elements 11 to 1m is performed at the time of initial setting of each multi-task control element 11 to 1m (when executing command 0). : PO8T, flowchart in Fig. 19), multi-task control elements 11 to 1m
This is a command to send data to a memory area called mailbox MBX provided within the mailbox. The mailbox MBX serves as a message relay point between the task that executed this command 12 and another task within the same element management (execution of command 13, which will be explained next). One of the five mailboxes MBXI to MBX5 can be specified. The number of the mail box MBX to be used and the data to be sent to the designated mail box MBX are written in the command parameter register CPIO, and the command is executed.

When command 12 is executed, the input data is checked for errors (step @), and if an error is detected, the command/
Set the status register CN S T error code (step @) and return to the main routine.

If no error is detected, write the transmitted data to the mail box MBX with the specified number (step [phase]
). Next, it is checked whether there is a task that has already executed command 13 and is waiting for data to be sent to the specified mail box MBX by executing command 12 (step [phase]). This is done by referring to the PENDW flag and mailbox number 0 in the task status 1 in the task control block TCB of all tasks. If there is no task waiting to be sent, skip to step [phase]. When there is a task waiting for transmission (only one is allowed in this example)
resets the PENDW flag in the task control block TCB of the task waiting for transmission, sets the READY flag, and reconnects the ready Qs in priority order (step [phase]).

Then, whether there is a task waiting for transmission or not, a normal completion code is set in command/status register CN5T (step [phase]), and TSKCHG
Set the flag (step 0) and return to the main routine.

Command 13 (command name: PEND, flowchart in FIG. 20) is a command to receive data from another task via the specified mail box MBX. Write the number of the mail box MBX that receives data into the command parameter e register CPIO and execute the command. When command 18 is executed, the input data is first checked for errors (step [phase]), and if there is an error, an error code is set in the box mant/status register CN5T (step [phase]), and the process returns to the main routine. return.

If no error is detected, it is checked whether data has already been written to the designated mail box MBX (step [phase]). If it is not written,
'Reset RUN flag.

Set the PENDW flag (step [phase]), and set the TSKCHG flag (step O).

Then, command/status register CN5
Set the data unarrival code in T (step ) and return to the main routine. If data has already been written, transfer the data written to the mail box MBX specified by the command φ parameter register CPIO.
Set the normal completion code to N5T (step [phase]
), return to the main routine.

Command 14 (command description: PMOD, flowchart in FIG. 21) is a command for setting the data input/output direction of port 1 and port 2. A code for specifying the input/output direction of port 1 and port 2 is set in the command parameter register CPIO, and the command is executed.

pmant - Specify the input/output direction of port 1 and port 2 based on the code set in parameter register CPIO.Step O), command/status register C
Set the normal completion code to N5T (step O),
Return to main routine.

Execute the processing routine for the above arbitrary commands 0 to 14 issued from the task, and determine whether an error code is set in the main routine 1r large in Figure 6 - Suzu command/status register CN5T. Do (step [phase]). If the error code is set, skip to step [phase]; if the error code is not set, then it is determined whether the TSKCHG flag is set (step). T.S.
If the KCHG flag is II O#, step [phase]
Skip to step 1''', execute the task switching routine (step [phase], the task switching routine is detailed in the flowchart of FIG. 22); skip from step [phase] or step When the task switching routine (step [phase]) is executed and returns to the main routine, preparations are made to accept the next command (step 0), and the TSKCHG flag is reset (step ■).Then, the process returns to step ■,
The next command reception is in a waiting state.

As mentioned above, the command processing routine 'ff5Kc)I
When the G flag is set (1"), a task switching routine is executed. In the flowchart of FIG.
When entering the task switching routine, a check is first made to see if it is time to execute command l (initialization end and execution start) (step [phase]).

When executing command 1, skip to step @,
Through the subsequent processing, first, from among the tasks previously registered with command 0 (initial setting), the task control block TCB of the task connected to the beginning of Ready Q is separated from Ready Q. Step (2) Write the value of the task stack pointer (see FIG. 3) in the task control block TCB to the new stack pointer register SPN. and task control block TCB
Set the RUN flag in the task status ■ (step ■)), set the interrupt (IP) flag to request an interrupt from the master CPU2 (step ■), and receive an interrupt response from the master CPU2. (Step (El)). The master CPU interrupt response waiting routine will be described in FIG.

When the master CPU 2 receives an interrupt, it reads the value of the stack pointer of the new task prepared by the task switching interrupt routine corresponding to the control element that requested the interrupt, and at the same time as the interrupt routine returns, it manages the master CPU 2. Perform the task below. The interrupt routine for task switching in the mask CPU 2 will be described in detail in FIG.

At times other than when command l is executed, it is checked whether the task is in the execution state (step [share]). If it is not in the execution state, skip to step O and transfer the data in the old stack pointer register SPB to the task stack in the task control block TCB of the task that was in the execution state before.
Write to the pointer ■ area and save.

Thereafter, it is determined whether there is a task in a ready state that can be executed next among the management tasks of the control elements 11 to 1m that have accepted the command.
The LEO (lower element enable output) terminal is set to "Low" (step O) to prohibit execution of the lower multi-task control element.

(At initial setting, the LEO terminal is set to "l Low II.") If there is no task in the ready state, the LEO terminal is set to "High" (step O) and the lower multi-task control element is Enables interrupts and enables execution of subordinate elements and tasks under management.The program itself loops through steps 2 and 0 and waits until a ready task appears.

In this embodiment, a ready task appears from a state where all tasks under the control of the same element are stopped or in a standby state and no ready task exists. In this embodiment, command 5 (TS
This is a case where a task that has been designated to be activated by an external event (PD) is activated due to the transition of the boat 3 and becomes ready.

Both when a ready task exists and when a ready task does not exist and is waiting until a ready task appears.
Subsequently, through the processing of steps ■ to C9■, the purpose is to execute another task.

From the multi-task control elements 11 to 1m to the master CPU 2
In order to request an interrupt from the master CPU 2, an interrupt (IP) flag is set and a response from the master CPU 2 is waited. If the interrupt is accepted, an interrupt is generated and switching to a task under the control of the control elements 11 to 1m is performed.

The master CPU interrupt response wait routine shown in FIG. 23 will now be explained. Multi-task control element 11, respectively.
Even if the interrupt (IP) flag is set within ~1m, an interrupt is not necessarily applied to the master CPU 2 immediately. The IP flag is set and the interrupt signal IN
T becomes “Low” because the IEI input terminal of the element is “Low”.
"High" (see FIG. 27).

Incidentally, the multi-task control elements 11 to 1m are provided with an IEI (interrupt enable input) terminal and an IEO (interrupt enable output) terminal in order to control interrupts between the respective elements. IEO terminal is IEI
When the terminal is “Low” and IEI terminal force (“Hi”
It
This is the terminal that becomes L Ow jl. In addition, as mentioned above, the LEO (lower element enable output) terminal is a terminal that becomes "L, o w" when there is a task in execution or ready status among the tasks under each element's control. be.

(It is assumed that the multi-task control elements 11 to 1m are connected in cascade through these terminals as shown in FIG. 27.) Therefore, after setting the IP flag in step 2 of FIG. (see figure).
It is determined whether the interrupt has been accepted (step O). Interrupt is set. If there is no executable task in the upper multi-task control element, the interrupt is immediately accepted. However, if the interrupt exists, the interrupt is not accepted, and the IRTDS flag is set (step ■)). ○.

■Loop and wait. If the interrupt is accepted, reset the IRTDS flag (step 0),
Return.

In the judgment of step [phase] in Fig. 22, if the task is in the execution state (RUN state), the time
Up time is checked (step [phase]). When the time is up for a task specified for time-sharing processing, it skips to step [phase]. This skip routine is executed only during timer interrupt processing in the flowchart of FIG. 25, which will be explained later.

If the time is not up, check whether there is a task connected to Ready Q (step [
phase]). If there is no task in the execution waiting (ready) state other than the task currently in the execution state, the sixth
Return to the main routine shown in the figure. If there is a task connected to the ready Q, then the priority of the task in the execution state is compared with the priority of the task connected to the beginning of the ready Q (step [phase]). If the priority of the task in the execution state is higher, the process returns to the main routine shown in FIG. 6 as well. If you return to the main routine with steps [phase] and [phase],
No interrupt is generated, and the currently executing task continues to execute.

If the priority of the task connected to the beginning of ready Q is higher, the task control block TC of the task being executed is
Connect B to ready Q and reset the RUN flag (step [phase]).

Then, the data of the old stack pointer register SPB is transferred to the task stack of the task control block TCB.
It is stored in the pointer [existence] area and an interrupt is generated through the processing of step [phase]) and subsequent steps 0-e). In addition, in Steps - C), the other task that newly enters the execution state is the task that is connected to the beginning of Ready Q as described above, and is the task that has the highest priority (has become the highest priority due to command execution, etc.). .After requesting an interrupt,
After the interrupt is accepted by master CPU2,
Returning to the main routine in FIG. 6, preparations are made to receive the next command (step [phase] in FIG. 6).

24, 25, and 26 are flowcharts of the interrupt processing routine for the main routine of FIG. 6.

FIG. 24 shows interrupt processing by input to port 3, in which a task in a stopped state is activated by an external event by command 5 (stop task, flowchart in FIG. 12).

This routine is activated by the transition of the signal input to port 8. In this routine, the task control block TCB of the task for which external event activation is set with command 5 is connected to the ready Q in order of priority.
Reset the ND flag and set the READY flag (step φ). That is, this enables the stopped task to be restarted, and once this is completed, the interrupt processing routine returns.

FIG. 25 shows interrupt processing by a timer. The signal from the timer TM in FIG. 2 is used as an internal interrupt signal, and when this occurs in fixed time units, a timer interrupt processing routine is entered.

When an internal interrupt signal is generated from the timer TM, first, the clock value (hour 1 minute 1 second data) registered in the system clock area SCA is advanced (step O).

Next, check the IRTDS flag (see Figure 23) and confirm that the interrupt for task switching is sent to the master CPU2.
It is determined whether the request has been accepted (step e). ``If the IRTDS flag is set, that is, if the interrupt is not accepted, return directly. If the IRTDS flag is reset, check the time-sharing processing (step ■). In other words, step ( 917) Judgment: Wait for interrupt acceptance in the master CPU interrupt response wait routine in Figure 13 (step @, (E;)) or wait for ready task in the task switching routine in Figure 22 (step ■, This is to ensure that the system clock area SCA can be counted normally even in the state (2).

In step [), the register S set by command 7 (setting of task time-sharing processing, flowchart in Figure 7) is
The priority registered in L I PRI is compared with the priority of the task currently in execution state.

Time-sharing processing is effective only when there is no task in a ready state with a higher priority than the specified priority.

If there is a ready task with a higher priority, that task will be executed and time-sharing processing will be disabled.
It becomes valid if there are no tasks with a high priority.The comparison in step e above is equivalent to checking whether the task with the priority registered in the register 5LIPRI is being executed, and time-sharing processing is performed. If the specified task is not in the execution state, immediately return from the interrupt processing routine.

If the priority registered in register 5LIPRI matches the priority of the currently running task, that is, if the currently running task is a task specified for time-sharing processing, then the time registered in register 5LICNT has elapsed. It is determined whether or not (step C). If the elapsed time has not elapsed, return from this interrupt processing routine. That is, the multi-task control elements 11 to 1m return to the main routine and enter a waiting state for receiving the next command, and the master C
The PU2 continues to execute the task currently in the execution state specified by the time-sharing process.

When the registered time has elapsed, connect the task control block TCB of the task in execution state to the end of ready Q, reset the RUN flag, and set the READY flag (step CD), the task switching routine shown in FIG. (Step O).

In the flowchart of FIG. 22, when the time is up for a task designated for time-sharing processing, the process skips from step [phase] to step [phase]. Then, the processes of steps [phase] to (2) are performed. As a result, the data of the old stack pointer register SPB is saved in the task stack pointer area of the task that was previously in the execution state (step [phase]).

Next, through step O1■, the task control block TCB of the task with the same priority specified for time-sharing processing is separated from ready Q (step ■), and the task stack pointer in this task control block TCB is Write the data of the area to the new stack pointer register SPN (step e). Finally, the RUN flag is set in the task status ■ (step O).

After performing such a task switching routine, the program returns from the interrupt. In the mask CPtJ2, another task designated for time-sharing processing is executed by the operations of the multi-task control elements 11 to 1m described above.

FIG. 26 is a flowchart of processing when an internal interrupt occurs at the falling edge of the IEI terminal.

Among the plurality of multi-task control elements 11 to 1m connected as shown in FIG.
When a task in the ready state appears among the tasks under the control of the IH (this is called an IH), the upper control element IH
Set the terminal to LL0w 11 (Figure 22 - Step (I)
FI)) Therefore, the IE1 input and IEO output of all elements lower than that element IH become It L 0WII, and an I'EI interrupt is generated internally.

At this time, the element between the control elements IH and IL is RUN.
Since there is no task in the state, it returns as is (Step O). However, since there are 9 tasks currently being executed, the control element 1L proceeds to Stella m to set the interrupt (IP) flag (step 2), and enters the master CPU interrupt response waiting routine (step 2). at this point
After the upper control element IH sets the IEO terminal to "Low" (see FIG. 22), it generates an interrupt through steps (1) to (2) and (2). Since the control element IH is at the top level at that point, this interrupt is immediately accepted and the control element IH
Execution moves to the task under the control of H. And element I
The execution of the task being executed under the control of L is interrupted even though it should be in the execution state.゛Execution is resumed when there are no tasks in the ready state among the tasks under the management of an element higher than the element IL (the 22nd task).
Figure/Step ○, ■), IEI terminal of element IL is °'H
until it becomes “high”.

The internal processing of the element IL is performed during the interrupt response wait routine of step (2) (see Figure 28),
) and waits until the IEI terminal becomes "High". When the IEI terminal II H=gh It, an interrupt from the element IL is accepted, and the task that was previously suspended while in the execution state under the control of the element IL resumes execution.

In this way, the IEI interrupt ultimately changes the operating state of the lower control element that is managing the task being executed, as shown in Figure 22 or 28.
The master CPU interrupt response wait routine shown in the figure is entered, and execution of a task whose execution has been interrupted by a higher-order control element can be resumed while remaining in an execution state.

FIG. 27 is a connection diagram of interrupt control lines between a plurality of multi-task control elements and other peripheral input/output elements. Each multi-task control element has eight signal lines LEO and IEO as interrupt control lines.

Equipped with IEI. For example, the following description assumes that a task under the control of the control element 11 is currently being executed.

The LEO terminal is connected to the lower element 12 when there is a task in the running or ready state among the management tasks of the element 11.
This is to disable interrupts from ~1m, and if such a task exists, the LEO pin will be set to 'Low.
”(If the ready task no longer exists, LEO
The terminal becomes II Hlgh II (explanation of Fig. 22,
(See step O9O). The IEO terminal is connected to lower elements 12 to 1m while element 11 is executing a task switching interrupt.
The IEO terminal is set to "Low" while interrupt processing is being executed.

At the IEI terminal, the lower elements 12 to 1m are connected to the upper element 11.
This is for inputting whether or not interrupts are enabled from
It is not possible to request an interrupt unless the signal is "I N T e Low". In other words, the interrupt signal cannot be set to "I N T e Low". Also, if the IEI terminal becomes “1LOW71”, the IEI terminal becomes “1LOW71”.
The EO terminal automatically becomes II L OW7+ (23rd
(See illustration).

Therefore, LEO and IEO as shown in FIG.

If the control elements 11 to 1m are connected by the IEI terminal,
In the elements 12 to 1m, while a task under the control of the element 11 is being executed, or while an interrupt process for task switching requested by the element 11 is being executed, all IEI terminals of the elements 12 to 1m are set to "Low", and the elements 12 to 1m are in a low state. The 1m interruption is
All are prohibited.

In this way, between the control elements 11 to 1m, LEO.

The IEO and IEI terminals allow determination of interrupt priorities and management based on task priorities.

In addition, the control elements 11 to 1m and other peripheral input/output elements 51 to
Between 5Ps, interrupt priorities are controlled only by the IEI and IEO terminals. In other words, the other peripheral input/output elements 51 to 5P are connected to the control elements 11 to 1 by the logic circuit 7.
Interrupts to mask CPtJ are prohibited only when one of m (this is referred to as 1x) is executing interrupt processing for task switching. That is, the IEI of the control i child lx is High ghI+, and the IEO is '
Only when it is Low', the IEI terminal of the peripheral input/output element 51 becomes 'L0w'. Therefore, the peripheral input/output element 51
~5P is not affected by the LEO terminals of the control elements 11~1m. Further, the peripheral input/output elements 51 to 5P are directly connected through IEI and IEO terminals.

Next, task switching interrupt processing prepared on the master CPU 2 side will be explained in detail.

FIG. 28 is a flowchart of this task switching interrupt routine. If a plurality of multi-task control elements 11-1m are connected as shown in FIG. 27, a task switching interrupt routine corresponding to each element is required. When the master CPU 2 accepts an interrupt, it can identify which control element is requesting the interrupt by the vector written in the interrupt vector register MIV in FIG. 2, and which interrupt mapping processing routine should be executed. I can judge whether it is strong or not.

The process will be explained below according to the flowchart shown in FIG. Now, assuming that the control element for which the interrupt has been accepted is 11, the interrupt processing corresponding to the control element 11 will be described below. When an interrupt occurs, the register of the task that was being executed just before is pushed to the stack area (step e).
). Next, the control element (self) where the interrupt was accepted
Check whether the task under the control of li is to be switched or not.
Judging from the value of the pointer (, S P ) (step O
). In other words, a task whose execution was interrupted by an interrupt will
It is determined whether it is under the control of the control element 11 that generated the interrupt. A stack area for each task is prepared for each task as shown in FIG. 29, and each control element 11=1 m
It shall be prepared so that it can be identified. Therefore, in step O, read the current SP value,
Depending on which address range that value falls within, you can determine which task was being executed.

If the tasks are under the control of the same element 11, the old stack pointer register SPB of its own control element 1i
Write the current SP value to (step -)). Next, steps O) and S read the value of SP of the task to be executed next from the new stack pointer register SPN.
Rewrite P to that value (step O). After that, if you pop the register from the stack area (step e),
The register of the task to be executed next is restored.

After that, when the program returns from the interrupt, the next task starts executing.

If the execution of a task under the control of another control element (this is called IX) is interrupted in step 1, SP
Judging from the value of (Step ○). Next, it is determined whether the control element lx that manages the task whose execution was interrupted is lower than the control element 1i that generated the interrupt (step O).

If it is a higher control element (this is called IXH), the task being executed under that control element IXH is stopped or in a standby state. In this case, control element IX
The old stack pointer register SPH of H is set to the current stack pointer register SPH.
Write the value of P (step O). Next, control element 1
1 executes its own steps ① to ① and returns from the interrupt.

In step Q, the control element (
(this is called 1xL), the bath, control element 1xL
This is the case when the task that was being executed under is interrupted while still in the running state. Therefore, in this case, the control element 1x
The new stack pointer register SPN of L is set to the current S
After saving the value of P (step ■), similarly executing steps ○ to O, the process returns. The value of SP saved in step C is determined when the interrupt of control element 1xL is accepted and this task switching routine is entered when there are no more executable tasks under the control of control elements higher than control element 1xL. At this time, the new stack pointer register SPN is read out in step (2).

Effect> As described above, according to the present invention, other peripheral input/output elements connected to a lower priority level than a plurality of cascade-connected multi-task control elements request an interrupt to the master CPU. However, it has the advantage of being able to receive normal interrupt support from the masked CPU. Additionally, by adding a simple logic circuit, peripheral input/output elements are no longer affected by interrupt control for task switching between multi-task control elements (disabling interrupts of lower control elements by LEO signals). This has the advantage that. Additionally, interrupts from peripheral input/output devices are only prohibited when the master CPU is processing interrupts from these control devices.
This also has the advantage of enabling normal interrupt control between the master CPU and peripheral input/output elements.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a system configuration using a control element of the present invention, FIG. 2 is a block diagram showing an example of an internal configuration of a control element in an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a system configuration using a control element of the present invention. FIG. 4 is a diagram explaining the control block TCB area, FIG. 4 is a diagram explaining the memory map MEMMAP area of FIG. 2, and FIG.
The figures are diagrams explaining commands, input parameters, and output parameters used in the control element, Figure 6 is a flowchart explaining the operation of the main routine of the control element, and Figure 7 is a diagram explaining the operation of the main routine of the control element.
21 is a flowchart explaining the operation of the processing routine by each command, FIG. 22 is a flowchart explaining the operation of the control element task switching routine, and FIG.
22 is a flowchart showing details of the master CPU interrupt response waiting routine, FIG. 24 is a flowchart explaining the operation of the interrupt processing routine based on event input, and FIG. 25 is a flowchart explaining the operation of the timer interrupt processing routine. FIG. 26 is a flowchart explaining the operation of the IEI interrupt processing routine, FIG. 27 is a block diagram showing an example of cascade connection of a plurality of control elements,
FIG. 28 is a flowchart explaining the operation of the task switching interrupt routine in the master CPU, and FIG. 29 is a diagram explaining the stack area of the master CPU. 1...Multi-task control element group, 11-1m...
Multi-task control element, 2... Master CPU, 3.
...Program memory, 6...Data memory, 7
...Logic circuit, INTC...Interrupt control circuit, IN
T...interrupt signal, TCB...task control block,
C0NT...internal calculation control circuit, TM...timer,
SCA...System clock area, MIV...Mask interrupt control register, CPIO...Command/
, e parameter register, SPN...new stack pointer register, SPB...old stack pointer register, IEI...interrupt enable input terminal, IEO...interrupt enable output terminal, LEO
...lower element enable output terminal. Agent Patent Attorney Aihiko Fuku (2 others) Figure 6 Figure 7 Figure 9 Figure to Figure 13 Figure 14 Figure 15 Figure 21 Figure 23 WJ Figure 22 Figure 24 Figure 25 WJ 28111 Tsutadegu Suriki 2nd CIW! a

Claims (1)

[Claims] 1. An interrupt enable input terminal (IEI terminal) into which a control signal for controlling interrupts between each element is introduced into a plurality of multi-task control elements that manage a plurality of tasks executed by a master CPU. ), an interrupt enable output terminal (IEO terminal) from which a control signal for controlling interrupts between each element is derived, and an interrupt enable output terminal (IEO terminal) from which a control signal for controlling interrupts between each element is derived. A lower element enable output terminal (LEO terminal) is provided from which a control signal for inhibiting an interrupt from a lower element is derived, the plurality of multi-task control elements are cascade-connected, and the plurality of cascade-connected multi-task control elements are・
The IEI terminal enables interrupts to the master CPU of other peripheral input/output elements connected to a lower interrupt priority level than the task control element. A computer peripheral device incorporating a multitasking control element, characterized by comprising an IEO terminal, a LEO terminal, and a connected logic circuit.