JP3361949B2 - Program verification device - Google Patents

Description

Detailed Description of the Invention

[0001]

This invention relates to real-time
The present invention relates to program verification for comparing and verifying the end time of a multitask program and the required execution time.

[0002]

2. Description of the Related Art In a development simulation of an automobile, a missile or the like, since a highly accurate simulation result is required, a real-time multitask program given a spec time, that is, a time constraint condition is executed.

The real-time multi-task program is a multi-task program which executes programs as if a plurality of tasks were operating at the same time, with a time constraint condition added thereto. In reality, the operating system is executed by dispatching multiple tasks.

In this real-time multi-task program, an interrupt processing task may be executed during execution of a plurality of tasks, and the time constraint condition may not be satisfied depending on the generation time of the interrupt processing task. Before describing the original prior art, FIG.
This will be described in more detail with reference to the timing charts of FIG. Here, in order to simplify the technical problems, a program that runs on a single processor will be described.

In FIG. 2, as a program to be executed, three tasks 1 to 3, an interrupt processing task,
There are system resources such as disk devices, and an operating system dispatcher. A time constraint condition of time 20 is given to the end time of task 1. Further, task 1 permits interrupts from time 0 to time 4.

Each of the tasks 1 to 3 has a priority, and here, the tasks are switched by the dispatcher according to the priority of task 1> task 2> task 3. Switching the tasks by the dispatcher requires some time penalty, here time 1.

Task 2 requests and occupies the system resource at time 5, and until task 2 releases the occupation of the system resource, here, after time 3,
When other tasks try to demand system resources,
The operating system suspends the execution of that task.

In the example of FIG. 2, the interrupt processing task is not executed, task 1 ends at time 16, and the time constraint condition is satisfied.

FIG. 3 shows that an interrupt request is generated at time 2 and control is transferred from task 1 to the interrupt processing task. After the completion of the interrupt processing task, the control is transferred to the task 1 having a higher priority again.

Here, even if the interrupt processing task requests the same system resource as the task 2, there is no conflict between the interrupt processing task and the task 2 in the system resource. As a result, the end time of task 1 is time 20, which satisfies the time constraint condition.

However, as shown in FIG. 4, if the generation time of the interrupt request is slightly shifted, the time constraint condition cannot be satisfied. In FIG. 4, when an interrupt request occurs at time 3, the occupation of system resources by the interrupt processing task is released after time 3, that is, at time 9.

In this case, task 2 originally started by the dispatcher is postponed by the operating system and dispatched to task 3. When the occupation of the system resource by the interrupt processing task is released, the operating system causes the dispatcher to dispatch the task 3 to the task 2 in order to cancel the suspension of the task 2, which originally has a high task priority. Due to this extra dispatch, the end time of task 1 becomes time 21, and the time constraint condition cannot be satisfied.

Further, if the generation time of the interrupt request is deviated, the time constraint condition is satisfied again as shown in FIG. In FIG. 5, the interrupt request is generated at time 4, and as a result, the end time of task 1 is time 19. This is because the release of system resources by the interrupt processing task is delayed (released at time 10), so that extra dispatch from task 3 to task 2 does not occur.

As described above, in the real-time multi-task program, a situation in which the time constraint condition cannot be satisfied may occur due to a slight difference in the interrupt processing task generation time. Therefore, conventionally, interrupts are generated at various times to verify real-time multitask programs.

A conventional verification technique will be described with reference to FIG. In FIG. 6, an external memory 31 stores an operating system, a plurality of tasks to be verified, and an interrupt verification program, and is connected to a bus 35 via an address bus 33.

The instruction execution unit 37 outputs the clock signal CLK to the programmable timer 39 every unit time during the program execution period, and when the interrupt signal IRS output from the programmable timer 39 becomes active, the address bus 33 and the bus 35. It is instructed by the operating system via the to execute the interrupt processing task.

The programmable timer 39 is a counter 4
1, an interrupt generation count value holding unit 43, and an interrupt generation unit 45. The counter 41 counts up the value based on the clock signal CLK and measures the execution time. The interrupt generation count value holding unit 43
The interrupt generation program holds the interrupt generation count value set via the data bus 47. The interrupt generation unit 45 compares the measured time TIME of the counter 41 with the count value of the interrupt generation count value holding unit 43,
When the values match, the interrupt signal IRS is activated. As a result, an interrupt request is issued to the instruction execution unit 37.

Two examples of a method of performing the interrupt verification of the task subject to the time constraint condition by such a conventional verification technique will be shown. However, it is assumed that the time range in which the interrupt is permitted is limited in the operation time of the target task.

The first method is to operate the interrupt verification program completely independently of the task subject to the time constraint condition. The interrupt verification program sets the interrupt generation count value in the holding unit 43, and the instruction execution unit 3
The interrupt request generation time is set in 7. This interrupt request generation time must be set so that there is no omission of verification for the task subject to the time constraint condition.

At this time, a random number may be set as the interrupt generation count value. The random number may be generated and set by the programmable timer 39 itself without being set by the interrupt verification program.

The second method is a method of registering in the operating system so that the interrupt verification program is always started before the task subject to the time constraint condition is dispatched. In this method, the interrupt verification program sets the time at which an interrupt request is issued to the instruction execution unit 37 as the interrupt generation count value.
This time is the time when it is desired to issue an interrupt request immediately after the target task is dispatched after the start of the interrupt verification program.

[0022]

As described above, the conventional verification method has two methods, but each has a problem. The problem with the first method is that since the interrupt request generation time is generated with a uniform random number for the entire task subject to the time constraint condition, an interrupt is issued outside the interrupt enable range of the target task. The request may be issued.

In this case, the task ignores the interrupt request, and as a result nothing happens.
If the range of interrupt permission is short with respect to the task execution time, the probability of occurrence of interrupt verification is low and the efficiency is low. As a result, a great deal of verification time is required.

In the second method, the time at which the interrupt request is generated can be limited within the range of interrupt permission.
The problem like the first method does not occur, and the verification time can be saved.

However, in the second method, the existence of the interrupt verification program itself poses a problem. The interrupt verification program is a program that is not included in the original application program, but consumes the CPU time of the instruction execution device when setting the interrupt generation count value. Therefore, the end time of the target task is different between when the application program is executed while verifying by the second method and when the application program consumes 100% of the CPU time of the instruction execution unit 37 and executes it. .

Further, as a common problem between the first method and the second method, it is necessary to have a function of judging whether or not the execution time of the target task satisfies the time constraint condition. There are cases where this function is provided to the task itself and where it is provided to the interrupt verification program. In both cases, the CPU time of the instruction execution unit 37 is consumed, and the same problem as described above occurs.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an interrupt request necessary for verification of a real-time multitask program without consuming CPU time of an instruction execution unit. It is an object of the present invention to provide a program verification device that can reduce the verification time and improve the accuracy of the verification result by generating efficiently.

[0028]

In order to achieve the above object, a program verifying apparatus of the present invention includes an external memory for storing an application program including a plurality of tasks and an interrupt processing task, and the external memory. An instruction execution device that executes the application program while dispatching a plurality of tasks and an interrupt processing task, an execution time of a test target task of the application program when the interrupt processing task is dispatched, and a request execution of the test target task The instruction execution device dispatches the interrupt processing task according to an interrupt signal output from the interrupt test device during execution of the plurality of tasks, and the interrupt processing device compares the time with the interrupt test device. After execution, While restarting the execution of the task of, while outputting the clock signal to the interrupt test device for each unit time during the execution period of the application program, the interrupt test device outputs the clock signal from the instruction execution device. A counter that measures the execution time of the test target task of the application program based on a clock signal and a start address of the test target task of the application program are held, and the start address output by the instruction execution device is monitored. A measurement start address holding means for outputting an interrupt condition instruction signal at the same time as the execution of the task to be tested, and a measurement condition instruction for instructing an interrupt generation time based on the interrupt condition instruction signal output from the measurement start address holding means. Means and means for instructing the measurement condition Therefore, the measurement condition holding means for holding the interrupt generation time instructed is compared with the interrupt generation time held in the measurement condition holding means and the execution time measured by the counter, and if they match, the interrupt signal To the instruction execution device, a request execution time holding means for holding the request execution time of the application program, and an end address of a test target task of the application program, By monitoring the end address to be output, a measurement end address holding unit that outputs a measurement end signal simultaneously with the end of the test target task, and a counter based on the measurement end signal output from the measurement end address holding unit End time of the measured application program And request execution time comparing means for comparing the request execution time held in the request execution time holding means, and measurement result holding means for holding the comparison result by the request execution time comparing means.

[0029]

According to this structure, since the interrupt test device is provided, it is possible to efficiently generate the interrupt required for verification of the real-time multitask program without consuming the CPU time of the instruction execution device. .
Further, by comparing the program end time and the required execution time, the verification time can be shortened and the accuracy of the verification result can be improved.

Further, the program verification apparatus of the present invention further comprises
The measurement start address holding unit outputs a counter reset signal simultaneously with the start of execution of the test target task, and the counter resets the execution time measured by the counter reset signal.

With this, every time the application program is executed, the measurement value of the counter is automatically reset at the same time when the execution of the task is started, and the measurement of the execution time of the application program can be restarted.

Further, the program verification apparatus of the present invention further comprises
The measurement condition holding means holds a plurality of the interrupt generation times, and the measurement condition instructing means instructs one of the plurality of interrupt generation times held in the measurement condition holding means, The measurement result holding means holds the comparison result by the request execution time comparing means in association with one interrupt generation time instructed by the measurement condition instructing means.

With this, since a plurality of arbitrary interrupt generation times can be set in advance, different interrupt generation times can be designated each time the execution of the application program is started. Further, since the instructed interrupt generation time and the comparison result by the interrupt generation time can be associated with each other, the efficiency of verification is improved.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the program verification device of the present invention.

In FIG. 1, the program verification device is roughly composed of an external memory 1, an instruction execution device 3, and an interrupt test device 5.

The external memory 1 stores an operating system and an application program composed of a plurality of tasks and interrupt processing tasks, and is connected to a bus 9 via an address bus 7.

Similarly, the instruction execution unit 3 connected to the bus 9 via the address bus 7 is a commonly used instruction execution unit, and includes a plurality of tasks and interrupts stored in the external memory 1. Execute application programs while dispatching processing tasks.

When the interrupt test device 5 outputs the interrupt signal IRS during execution of a plurality of tasks, the instruction execution device 3 dispatches the interrupt processing task if the interrupt is permitted, and after the execution of the interrupt processing task is completed, Resume execution of multiple tasks. Further, during the execution period of the application program, the clock signal CLK is constantly output to the interrupt test device 5 every unit time.

The interrupt test device 5 is a device which is a feature of the present invention. The interrupt test device 5 causes the instruction execution device 3 to generate interrupt requests at various times, and the end time of the application program when the interrupt processing task is dispatched. Compare with the required execution time (time constraint). Further, it has a function of holding the comparison result in association with the interrupt generation time.

The counter 11 measures the execution time after the execution of the application program is started, based on the clock signal CLK output from the instruction execution unit 3. Further, the measured execution time is reset by the counter reset signal CLR output from the measurement start address holding unit 13.

The measurement start address holding means 13 holds the start address of the test target task of the application program, and coincides with the value of the monitored address bus 7, and at the same time, the counter reset signal CLR and the interrupt condition instruction update signal INC. To activate.

When the interrupt condition instruction update signal INC output from the measurement start address holding unit 13 becomes active, the measurement condition instruction unit 15 updates the measurement condition, that is, the interrupt generation time, to the measurement condition / result holding unit 17. Give instructions.

The measurement condition / result holding means 17 holds a plurality of measurement conditions that are instructed to be updated by the measurement condition instructing means 15 and the measurement results corresponding thereto.

The interrupt generating means 19 compares the measurement condition designated by the measurement condition instructing means 15 with the value TIME measured by the counter 11, and when they match, activates the interrupt signal IRS to activate the instruction executing device 3 Interrupt request to.

The request execution time holding means 21 holds the request execution time (time constraint condition) of the application program.

The measurement end address holding means 23 holds the end address of the task to be tested of the application program, and makes the measurement end signal ETRG active at the same time when it coincides with the monitored address bus 7.

The request execution time comparison means 25 has a measurement end signal ETR output from the measurement end address holding means 23.
When G becomes active, the end time of the application program measured by the counter 11 (TIM
E) is compared with the required execution time held in the required execution time holding means 21, and the comparison result is output to the measurement condition / result holding means 17.

As described above, one embodiment relating to the program verifying apparatus of the present invention is configured. Next, the interrupt verifying of the task subject to the time constraint condition by the program verifying apparatus will be described.

Generally, the life cycle of a task is considered to be from when the instruction execution device 3 executes the instruction at the start position of the task to when it executes the instruction at the end position. That is, the start and end of the task can be distinguished by the value of the address bus 7 output by the instruction execution device 3. Therefore, when the task start address is set in the measurement start address holding means 13 and the task end address is set in the measurement end address holding means 23, the counter 11 when the measurement end signal ETRG from the measurement end address holding means 23 becomes active The value of indicates the end time of the task.

When the task time constraint conditions are stored in the required execution time holding means 21, the required execution time comparison means 2
The comparison result of whether or not the time constraint condition of 5 is satisfied is stored in the measurement result corresponding to the measurement condition instructed by the measurement condition instructing means 15.

The generation time of the interrupt request required for verification is
It may be stored in the measurement condition in advance as a relative time from the task start time. This is because the counter 11 is cleared to zero by the counter reset signal CLR when the task start is detected by the measurement start address holding unit 13.

The interrupt generation means 19 compares the measurement condition instructed by the measurement condition instruction means 15 with the measurement time of the counter 11 incremented by the clock signal CLK, and when they match, the interrupt signal IRS becomes active. Interrupt request is made.

The comparison result of the task execution time extended by the interrupt processing task and the request execution time is stored in the measurement result in association with the measurement condition.

The measurement condition instructing means 15 is updated every time the measurement start address holding means 13 detects the start of a task, and changes the position for storing the measurement condition and the measurement result. When the measurement condition instructing means 15 reaches the bottom of the storage area for the measurement condition and the measurement result, the verification ends there.

As described above, the measurement start address holding means 13, the measurement end address holding means 23, the required execution time holding means 21, and the measurement conditions can be set prior to the execution of the verification, and therefore, during the verification. Is the instruction execution unit 3
CPU is never consumed. In addition, the measurement condition can be specified by the relative time from the start time of the task subject to the time constraint condition, and the verification result is
Since it can be confirmed by the measurement result associated with the measurement condition, the verification can be performed efficiently.

[0057]

As described above, according to the program verification device of the present invention, the CPU time of the instruction execution device is not consumed,
Since it is possible to efficiently generate interrupts required for verification of real-time multitasking programs and to judge whether time constraint conditions are satisfied, it is possible to shorten verification time and improve the accuracy of verification results. .

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a program verification device according to the present invention.

FIG. 2 is a timing chart showing how a real-time multitask program is executed.

FIG. 3 is a timing diagram similar to FIG.

FIG. 4 is a timing diagram similar to FIGS.

FIG. 5 is a timing diagram similar to FIGS.

FIG. 6 is a block diagram for explaining a conventional verification technique.

[Explanation of symbols]

1 External memory 3 Instruction execution device 5 Interrupt test equipment 7 address bus 9 buses 11 counter 13 Measurement start address holding means 15 Measuring condition instruction means 17 Measuring condition / result holding means 19 Interrupt generation means 21 Request execution time holding means 23 Measurement end address holding means 25 Request execution time comparison means

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-5-108418 (JP, A) JP-A-2-271437 (JP, A) JP-A-5-250186 (JP, A) JP-A-2- 206848 (JP, A) JP 63-58550 (JP, A) JP 63-289653 (JP, A) Actual development 58-190751 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11/28-11/34 G06F 9/46

Claims (3)

(57) [Claims] 1. An external memory for storing an application program including a plurality of tasks and an interrupt processing task, and an instruction execution for executing the application program while dispatching the plurality of tasks and the interrupt processing task stored in the external memory. The device, and an interrupt test device for comparing the execution time of the test target task of the application program when the interrupt processing task is dispatched and the request execution time of the test target task , the instruction execution device, Multiple tags
The interrupt output from the interrupt tester during
The interrupt processing task is executed by the interrupt signal.
Switch, and after execution of the interrupt processing task,
Restart the execution of the task of
The clock signal is output every unit time during the execution of the program.
Is output to the interrupt test device,
The interrupt test device outputs from the instruction execution device
Based on the clock signal, the application program
Counter for measuring the execution time of the task under test in grams
And the task to be tested by the application program
Holds the start address of the
By monitoring the start address, the test target task
When the execution of the
Measuring start address holding means and measuring start address holding means
Based on the interrupt condition instruction signal output from the stage,
Measuring condition instructing means for instructing the interrupt generation time,
The interrupt generation time instructed by the measurement condition instruction means
The measuring condition holding means to hold and the holding to the measuring condition holding means
Depending on the existing interrupt generation time and the counter
Compare the measured execution time and if there is a match,
Generate an interrupt that outputs an interrupt signal to the instruction execution unit
Means and the request execution of the application program
Request execution time holding means for holding a line time, and the application
End address of the task to be tested by the application program
And the end address output by the instruction execution unit
By monitoring the
Measurement end address holding means for outputting a measurement end signal,
Measurement end signal output from the measurement end address holding means
The counter measured by the counter based on
Application program end time and the requested execution time
Comparing with the requested execution time held in the holding means
That requests an execution time between the comparing means, to the request execution time comparison means
A program verification device comprising a measurement result holding means for holding the comparison result according to the above . 2. The measurement start address holding means outputs a counter reset signal at the same time as the execution of the test target task is started, and the counter resets the execution time measured by the counter reset signal. The program verification device according to claim 1 . 3. The measurement condition holding means holds a plurality of the interrupt generation times, and the measurement condition instruction means holds one of a plurality of interrupt generation times held in the measurement condition holding means. The measurement result holding means indicates the comparison result by the request execution time comparison means,
3. The program verification device according to claim 1, wherein the program verification device is held in association with one interrupt generation time instructed by the measurement condition instructing means.