JPS60215246A - Data fetch control mechanism - Google Patents

Abstract

PURPOSE:To carry out processing with the smallest number of steps for a data fetch control mechanism by deciding a microprogram containing entries for each data access type and the data access type according to the address and the length of a given operand and branching them to entries of corresponding types of said microprogram. CONSTITUTION:An external data memory 2 stores the data to which access is possible with the word width containing plural byte widths. An external microinstruction memory 3 contains a proper entry for each data access type and stores a microprogram containing a microinstruction which controls the data fetching. A microprocessor 1 contains a sorting means and a processing means, and the sorting means sorts the data access types to the byte string data. While the processing means decides the data access type by the microprogram as well as the address and the length of the byte string data and branches the access type to a proper entry of the microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a Cheetah etch control mechanism used in a microprocessor. (Prior Art) In a microprocessor, bytes stored in an external data storage device that can be accessed in units of words each having a width of multiple bytes (Prior Art) When attempting to fetch and process string data, various data access cases occur depending on the starting address and length of the data if the data is not on a word boundary.

Conventionally, a common method is to sequentially determine the length of unprocessed data and perform necessary processing according to the determination results. However, this method requires a large number of conditional branching steps, resulting in slow execution speed.

(Object of the Invention) The object of the present invention is to provide a microprogram having an entry for each data access type, and to determine the data access type according to the address and length of a given operand, and to determine the corresponding type of the microprogram. By providing a control mechanism configured to branch to an entry, the above disadvantages can be eliminated and a data fetch control mechanism capable of processing each data access type with a minimum number of execution steps can be provided. be. .

(Structure of the Invention) A data fetch control mechanism according to the present invention includes an external data storage device, two classification means, an external microinstruction storage device,
The apparatus is configured to include a processing means. ``External data storage is for storing data that can be accessed in word widths that are multiple bytes wide.

The classification means is for classifying data access types for IJ songs (Pytos).

The external microinstruction storage device is provided with appropriate entries for each data access type and is for storing microprograms consisting of microinstructions that control data fetching.

The processing means is for determining the data access type by the microprogram and the address and length of the byte string data and branching to the appropriate entry of the microprogram.

(Embodiment) Next, an embodiment of the data fetch control mechanism according to the present invention will be described in detail with reference to the drawings.

In this embodiment, a flowchart of a transfer command for transferring byte string data will be taken as an example, and a case will be described in which 7-byte length data is transferred.

The above transfer instruction has a data length as a first operand, a transfer source address as a second operand, and a transfer destination address as an eighth operand. Data reading, ie, access to the transfer source address, is represented by A, and data writing, ie, access to the transfer destination address, is represented by B. Here, one word is defined as 4 bytes.

FIG. 1 is a block diagram showing one embodiment of a data fetch control mechanism according to the present invention. In FIG. 1, 1 is a microprocessor, 2 is an external data storage device for storing byte string data, 3 is an external microinstruction storage device for storing microinstructions, and 11 to 13 are each 1 word wide. A group of registers, 14 is a byte ring thick for performing a shift in byte units, 20 is a group of registers for storing data length and address, 21 is a register group that determines the operand fetch type and generates a branch address according to the determination. The decision branch address generation block 30 is an internal data bus having a data width of one word.

FIG. 2 is a diagram partially showing the inside of the external data storage device 2 in FIG. 1. As shown in FIG. DA is the transfer source data, D
B is the location where DA is transferred and stored, A1-A3 . B1.
B2 is a unit of data that is accessed at one time. A
11, A12 moves the data DA to the position DBK'! This is a unit that is written at one time when storing data, and indicates the portion corresponding to B1 and B2.

FIG. 8 is a flowchart showing the operation of the data fetch control mechanism according to the present embodiment. In FIG. 8, Mvl is the data length of the first operand,
This is a step of taking the addresses of the second and eighth operands into the register group. MV2 and MV24 are steps for taking in 4 bytes (1 word) of data from the external data storage device 2, respectively. MV3 is step MV2
This is a step in which the number of bytes of valid data among the 4-byte data fetched in step MV1 is subtracted from the data length LEN of the data fetched in step MV1. MVA is
This is a step of deepening the branch according to the fetch type determined by the decision branch address generation block 2.1 according to the data taken in step MV1. MV5, M
Vl 0 , MVl 5 , MVl 1 , and KM
V23 is a step in which the contents of the register group 11 are stored in the V register group 12 through the byte ring shifters 1-4.1, respectively. MV6, MVl 1 , MVl 6 and KMV20 are steps in which, in addition to the functions of step MV2 or step MV24, the byte length of one word, ie, 4, is subtracted from the data length LIN. MV7, MVl 7 and MV25
are from register group 11 to byte ring shifter 14, respectively.
J) I/register group 13 by merging the data obtained through the I/register group 13 with the data held in the register group 12 according to the shift state in the bitling thick 14.
This is the step of storing the MV8, MVl4,
and ffMVlB are steps for writing the contents of the 7912 group 13 into the external data storage device 2, respectively. MV1 and MV21 are steps that branch into two depending on the data length LKNO value. MVl 2 , MVl 3 , and MV22 are steps for storing data obtained from the contents of the register group 11 through the byte ring shifter 14 into the register group. In the fetch type, A represents reading of one word; B represents 1 word write. Further, AB is of a type in which the transfer is completed by reading one word and writing one word K. AAB
is a type in which the transfer is completed by writing one word after reading one word repeatedly twice. AB(
AB) is a type in which after performing AB for the first time, A and B are repeated zero or more times, and finally KAB is performed to end the transfer. AAB (AB) is of a type similar to AB (AB) except that the first time is AAB. A
B(B) is of a type similar to AB(AB) except that it ends only with B. AAB
(B) is AB(B) except that the first time is AAB.
) is of table type. In Figure 4,
(a) is AB type, (b) is AABAB type c) a
AB (AB) type, (d) is AB (B) □ type,
(1) is a diagram showing an example of AAB (B) type data.

Next, the operation of this embodiment shown in FIGS. 1 to 8 will be explained in detail. First, in step MVI, when a microinstruction is taken out from the external microinstruction storage device 3, interpreted and executed, a file representing the data length of the V register group 2DK and the start addresses of DA and DB are stored.

Therefore, based on the mutual relationship between the address and the data length, the decision branch address generation block 21 uses the function of the byte ring shifter 14 to decide to shift the data by one byte to the left, and at the same time, performs an operand fetch type AAB.
(AB) is decided. This is because the register 20 stores the start address and data length data. This information is used to detect the deviation between the two data and determine the bite ring thick 140 function. That is, the byte ring shifter 14 either does not shift at all, shifts to the right (left) [by 1 byte, shifts by 2 bytes, or shifts to the right (left)].
There are cases where there are 4 byte shifts.

Next, in step MV2, data A1 is read out and stored in register group 11, and in step MV3, the number of effective bytes in data A1, that is, 2, is set to data length LEN (=7).
Subtract from. Accordingly, the data length LEN becomes 6.

Next, in step MV4, AAB (
AB). Next, the instruction of one step MV15 is executed, and the data A1 is shifted to the left by one byte and stored in the register group 12. In step Mv16,
The next one word of data A2 is stored in the register group 111/c, and the data length LEN is subtracted by 4 to become IK. Then, in step MV17, the 8 bytes from the left of the register group 12 and the rightmost 1 byte of the output of the byte ring shifter 14 are processed.
Bytes, that is, the leftmost 1 byte of register group 11 are merged, data A11 is stored in 7912 group 13, and the contents of 7912 group 13 are transferred to position BIK in step MV1B.
written. In step MV19, the result obtained from the register group 11 through the byte ring shifter 14 is stored in the register group 12. In step MV20, the next one word of data A3 is read out and stored in the V register group 11, and data LEN is subtracted by 4. Therefore, the obtained result becomes negative after six steps, and in step MY21 the control branches to the Y side, and in step MV25, the data in register group 11 and the data A12 merged into register group 12 are transferred to register group 13. In step MV14, the data of the V register group 13 is written to B2, and the data transfer from DA to 6DB is completed.

In this embodiment, the AAB (AB) type is illustrated and an example in which steps MV17 to MV21 are executed only once has been described. However, if the data length is even longer, steps MV17 to MV21 may be executed multiple times. is executed repeatedly. Further, in each example shown in FIG. 4, each step is executed according to each type.

In this embodiment, a data transfer instruction has been explained using a flowchart, but the present invention can also be applied to a practical example where a first operand and a second operand are fetched, operated, and stored in the second operand. Furthermore, in such a case, it goes without saying that the present invention is applicable even if the data lengths of the first operand and the second operand are different.

(Effects of the Invention) As explained above, the present invention classifies data access types, uses microprograms each having an entry according to each data access type, and accesses data according to the address and length of the data. By determining the type and branching to the above entry, there is an effect that processing can be executed with a minimum number of execution steps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a data fetch control mechanism according to the present invention. FIG. 2 is a diagram showing the state of the transfer source and transfer destination of data stored in the external data storage device in this embodiment. FIG. 8 is a flowchart showing the execution of a transfer command in one embodiment of the data fetch mechanism shown in FIG. FIG. 4 is a diagram showing an example of data of each data access type. 1...-Microprocessor 2.3...Storage device 11 to 13, 20/Red/Register group 14...ll11 Byte ring shifter 21@...Judgment branch address generation block 3011/
Bus DA...Data DB...Data positions A1-A3, B1, B2, A11, A12@.
...Section Data Unit Patent Applicant NEC Corporation Agent Patent Attorney Hisashi Inoro Figure 1 Figure 2 Figure 3 (a) Figure 3 (b) Figure 1 (a) (C) (e ) (!0) (cl')

Claims (1)

What is claimed is: An external data storage device for storing word-wide accessible data consisting of multiple bytes. A classification means for classifying data access types for byte string data, and an external storage device for storing a microprogram comprising microinstructions for controlling data etching, with appropriate entries for each data access type. and a processing means for determining the data access type based on the address and length of the microprogram and the byte string data, and branching to an appropriate entry of the microprogram. A data fetch control mechanism featuring: