JPS60214106A - Oscillator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillator. With known oscillators, the rise to the maximum oscillation amplitude requires several oscillation cycles following the instant of switching on the oscillator. Similarly, following switching off of the oscillator, the amplitude of the oscillating voltage decays slowly over several oscillation cycles. With such oscillators, there are many applications where the oscillator output cannot be used during the rise and decay periods mentioned above.

When the oscillator is used in a vehicle detection system, it is particularly desirable to have the rise and decay durations reduced or eliminated. This is particularly true in vehicle detection systems where several channels are repeatedly scanned in sequence and an oscillator is used for each channel to detect vehicles. Since the vehicle to be detected may be moving at high speeds, the time available for each scan period is limited, so the rise and fall of the oscillation further limits the operation of the detection device.

An object of the invention is to reduce the rise time of an oscillator.

The oscillator of the present invention is an oscillator comprising a power source that generates a substantially constant current and includes a control element capable of controlling the magnitude of this current, a tuned resonant circuit, and switching means, wherein the switching means is the one described above. The mode of operation of said oscillator is switched from standby mode to oscillation mode and vice versa by switching a control element from one mode of operation to another, and during standby mode said tuned resonant circuit is switched from said power source to said tuned resonant circuit. When charging power is supplied to the inductor and the mode changes from standby mode to oscillation mode,
The supply of the charging current is interrupted,
A control loop is provided between the resonant circuit and the control and sub-elements, which provides the control element with a control voltage that is dependent on the voltage across the tuned resonant circuit, thereby controlling the tuned resonant circuit during the oscillation mode. is characterized in that a pulse of current is supplied from the power supply to the tuned resonant circuit at every other half cycle of the oscillating voltage that occurs across the oscillating voltage.

In one form of the invention, the control loop is connected to key the control element in synchronization with every other half cycle of the oscillating voltage generated across the tuned resonant circuit. Contains a keying signal generator.

Preferably, the amplitude of the oscillator output is stabilized. According to another aspect of the invention, amplitude stabilization means are provided which are responsive to the peak-to-peak amplitude of the oscillating voltage across said tuned resonant circuit, whereby said means generates a signal generated by said keying signal generator. The control element is keyed such that the amplitude of the keying pulse varies inversely to the peak-to-peak amplitude variation of the oscillating voltage.

In a practical example according to this aspect of the invention, a differential amplifier is associated with said control loop, said differential amplifier having a first input terminal connected to said keying signal generator;
a second input terminal connected to monitor the oscillation voltage across the tuned resonant circuit, and an output terminal of the differential amplifier configured to supply a keying pulse to the control element. and the differential amplifier is operative to produce a keying pulse having a magnitude dependent on the difference between the peak-to-peak voltage of the oscillating voltage across the tuned resonant circuit and the reference voltage. Make it.

When the oscillator is in oscillation mode, it is also desirable to reduce the period of time until oscillation ends following selection of standby mode. In this regard, according to another aspect of the invention, said switching means is adapted to control the voltage present across the first input terminal connected to detect the selected mode of operation and the tuned resonant circuit. a second connected to monitor
and a controlled delay means having an input terminal, the controlled delay means being activated when the standby mode is selected, and when the oscillator is in the oscillation mode, the transition to the standby mode and the input terminal to the inductor of the tuned resonant circuit are performed. The supply of the charging current is delayed until the current flow in the inductor due to the flow of the oscillating current in the tuned resonant circuit is approximately at its maximum in the direction opposite to the flow of the charging current.

The invention will be explained with reference to the drawings.

In the circuit of the oscillator of the present invention shown in FIG. 1, a tuned resonant circuit TC consisting of an inductor 1 and a capacitor 2 is connected to a DC power supply (not shown) through a series circuit of a transistor TRI and a resistor 5. Connected between power supply lines 3 and 4. The resistor 5 mentioned above is connected between the emitter electrode of the transistor TR1 and the positive power supply line 3. The pace electrode of the transistor TRI is connected to the interconnection point of the bias network consisting of resistors 6 and 7, and the end of the resistor 7 opposite the base side of the transistor TRI is connected to the switch S and thus Is S in the position marked with “A” or “B”?
The said end of the resistor 7 is connected to the positive voltage line 3 or to the negative voltage line 4, depending on the position marked with ``.The base of the transistor Tft1 is connected via the resistor 8 to the voltage comparator 9. The input terminal of this voltage comparator 9 is connected across the capacitance 2. The input terminal 11 of the comparator 9 is connected to the output terminal of a keying signal generator in the form of . It is connected to the positive voltage line 3 and via the resistor 13 to the negative voltage line 4.

The values of resistors 5, 6.7 and 8 are chosen such that transistor TRI functions in conjunction with a DC power source (not shown) as a substantially constant current source for resonant circuit TC.

Furthermore, the transistor TRI, together with its associated circuitry, functions as a control element that controls the magnitude of the current supplied to the resonant circuit TC. In order for the transistor TRI to function in such a manner that a nearly constant current supply is obtained, during operation the maximum peak-to-peak voltage developed across the resonant circuit TC over the entire control range provided by the transistor TRI must be It is necessary to select the values of resistors 5, 6.7 and 8 such that the voltage is so low that transistor TRI does not saturate.

When the switch S is in the position marked "B", the oscillator of FIG. It flows through the emitter-collector path of the TRI and through an inductance 1, which magnetically charges a capacitor 2.

The magnitude of the charging current supplied via inductance 1 depends on the voltage present at the interconnection point of resistors 6 and 7. When switch S is switched to the position marked with "A",
The transistor TRI shuts off and the supply of current to the inductor 1 is abruptly interrupted.

Despite the interruption of current flow through transistor TRI, current flow through the inductance continues. The reason for this is that current circulates in a resonant circuit consisting of inductance 1 and capacitance 2. Without the control loop provided by the voltage comparator 9 and the resistor 8, the train of oscillations in the resonant circuit TC is damped. However, controlling the transistor TRI by the loop supplies additional energy to the resonant circuit TC through the emitter-collector taffeta path of the transistor TRI at the correct time, compensating for the losses in the resonant circuit TC and thus sustaining the oscillation.

At this point, the (positive) input terminal 11 of the voltage comparator 9 is connected to the electrode of the capacitance 2 on the side adjacent to the negative voltage line 4, and the (negative) input terminal 10 of the voltage comparator 9 is connected to the negative supply line 4. Connect to the electrode of capacitance 2 on the opposite side.

The (negative) input terminal 10 of the comparator 9 is the (positive) input terminal 1
If it is positive compared to 1, the output of comparator 9 is "low"
Therefore, the low state at this output terminal becomes the potential of the negative power supply line 4, which is approximately the ground potential.
If input terminal 10 is positive with respect to (positive) input terminal 11, the output of comparator 9 will be "high".

When switch S is in the position marked "A", comparator 9
When the output of the transistor TRI becomes 'low' level, the end of the resistor 8 opposite to the base electrode side of the transistor TRI is connected to the power supply line 4 via the comparator 9, and the voltage divider consisting of the resistors 6 and 8 is connected to the power supply line 4. 3 and 4. Under these conditions, the voltage that develops at the interconnection point of resistors 6 and 8 causes transistor TRI to conduct and current therefore flows through the emitter-collector path of transistor TRI into the resonant circuit TC. When the switch S is in the position marked A'', when the output of the comparator 9 goes to the ``high'' level, the resistor 6
The voltage level at the interconnection point of and 8 blocks transistor TRI so that no current is supplied to the resonant circuit TC. Therefore, when the switch S is in the position marked A'', each time the potential at point P swings positive with respect to the supply line 4, the current flows through the transistor The signal is supplied to the tuned resonant circuit TC via the TRI.

In order to explain the signals at the various circuit points in relation to each other in time, FIG. 2a shows the level of the current flowing through the emitter-collector path of the transistor TRI, and FIG. 2b shows the voltage level at the output terminal of the comparator 9. , and the voltage at point P is shown in FIG. 2C.

In Figure 2, INT B corresponds to the state when the switch S is in the position marked "B'", and INT A corresponds to the state when the switch S is in the position marked "A". .

During the time when the switch S is in position "B", the emitter-collector current, which has a relatively high level as shown in FIG. 2a, also flows through the inductance 1 as a charging current. The voltage at this time point P is at a slightly more positive level than the level of the power supply line 4.

However, by biasing the biasing network consisting of resistors 12 and 13 positively to input terminal 11 such that it is slightly more positive than input terminal 10,
When the switch S is in position "B", the output of the comparator 9 goes to the "high" level.

To make a satisfactory transition from standby mode (i.e. zero-power mode) to oscillation mode, it is necessary to move from position “B” to position “A”.
It is necessary to quickly switch the switch S to ``.

In a practical embodiment of the invention, it is necessary to accomplish the switching of the switch S electronically, thereby achieving rapid switching.

During the time when the switch S is in position "Δ", continuous oscillation occurs in the resonant circuit TC, and ideally a sinusoidal continuous oscillation voltage is produced at point P as shown in FIG. 2C. Since the voltage at point P is alternately positive and negative with respect to the supply line 4, the output voltage of the voltage comparator 9 is alternately "low" and "high".
level, and this voltage acts as a keying signal applied to repeatedly switch transistor TRI between conducting and non-conducting states. The level of conduction in the conductive state is determined by the relative values of resistors 6 and 8. Since there is no stabilizing device associated with the circuit of FIG. 1, the peak-to-peak amplitude of the alternating voltage at point P becomes limited to a level determined by the magnitude of the supply voltage between supply lines 3 and 4.

The pulse of current supplied via the emitter-collector path of transistor TRI is shown at 21 in FIG. 2a.

The amplitude of the current is constant for the duration of each separate current pulse 21, and the amplitude for each pulse 21 is equal to that of the current flowing through transistor TRI during standby mode of the oscillator when switch S is in position "B". lower than the constant amplitude value.

An oscillator according to the invention in which the amplitude of the output of the oscillator is stabilized can be obtained by the circuit configuration shown in FIG. In FIG. 3, parts similar to those in the circuit of FIG. 1 are given the same reference numerals as in FIG.

In FIG. 3, an inverter 301 is used in place of switch S in the circuit of FIG. 1 to switch the oscillator from standby mode to oscillation mode and vice versa.

The input terminal 302 of the inverter 301 is connected to the mode selection means (
(not shown), the input terminal 302 is held at a high level to put the oscillator in standby mode, and held at a low level to put the oscillator in oscillation mode.
When the input terminal 302 is set to the low level, the output terminal of the inverter 301 becomes the potential of the negative power supply line 4, and when the input terminal 302 is set to the low level, the output terminal of the inverter 301 becomes the potential of the positive power supply line 3.

The oscillator in Figure 3 consists of transistors TR2, TR3 and T
It has a differential amplifier consisting of R4 and related circuits. The collector electrode of the transistor TR2 is connected to the positive power supply line 3, and its base electrode is connected to the diode D.
It is connected to point P via I and resistor 303. The base of transistor TR2 is also connected via a capacitor 304 to the negative feed line 4 and via a resistor 305 to the collector electrode of transistor TR4. The collector electrode of the transistor TR3 is the transistor TRI.
The base electrode of the transistor TIt3 is connected to the output terminal of the voltage comparator 9 via a diode D5. The base electrode of transistor TR3 is also connected to diode D2. It is also connected to the negative power supply line 4 via a series circuit of D3 and D4. Diotro 5 is bridged by a series circuit of resistors 306 and 307, and the connection point between the resistors of this series circuit is connected to the output terminal of inverter 3. transistor TR
The emitter electrodes of transistor TR'2 and TR3 are interconnected and connected via a resistor 308 to the collector electrode of transistor TR'4, the emitter electrode of transistor TR4 being connected to negative supply line 4. The base electrode of transistor TR4 is connected to the output terminal of inverter 301 via resistor 309.

In the oscillator of FIG. 3, the method of connecting the voltage comparator across the capacitance 2 is different from the method of connecting the oscillator of FIG. 1. In the oscillator of FIG. 3, the (positive) input terminal 11 of the comparator 9 is connected to the interconnection point of resistors 310 and 311 forming a voltage divider between the positive feed line 3 and point P; On the other hand, the (negative) input terminal IO is connected to the interconnection point of resistors 312 and 313 forming a voltage divider between the positive power supply line 3 and the negative power supply line 4. Therefore, in the oscillator of FIG. 3, the output of the voltage comparator 9 will be at the high level when the voltage at point P becomes positive with respect to the negative feed line 4; , will be at a "low" level.Due to the presence of the voltage divider consisting of resistors 312 and 313, the output of comparator 9 will be at a "low" level during standby mode.

The operation of the oscillator of FIG. 3 is essentially similar to that of the oscillator of FIG. However, during the oscillation mode, the peak-to-peak amplitude of the oscillation voltage generated across the resonant circuit TC by the differential amplifier provided in the control loop is used to supply the resonant circuit TC by the control element consisting of the transistor TRI. control the level of energy used. At this point, the oscillating voltage present at point P is rectified, compared with a reference voltage, and using a keying pulse whose amplitude depends on the difference, the amplitude of the current pulse supplied to the resonant circuit TC via the transistor TRI is determined. control, thereby stabilizing the amplitude of the oscillation voltage across the resonant circuit TC.

The oscillating voltage present across the resonant circuit TC, i.e. between the point P and the negative feed line 4, is rectified by the diode D1 and the capacitor 304 is brought to a level determined by the peak-to-peak level of the oscillating voltage. Let it charge. The time constants of capacitance 304 and resistor 303 are selected to approximately match the period of one cycle of the natural frequency of resonant circuit TC, so that capacitor 3
04 is caused to rise rapidly as the peak-to-peak level of the oscillation voltage across the tuned resonant circuit TC increases. The decay rate of the charge on capacitor 304 is determined by the value of resistor 305, and the time constants of capacitor 304 and resistor 305 are selected to be equal to several cycles of the oscillation frequency.

The positive-going pulses occurring at the output terminal of voltage comparator 9 when the oscillator is in oscillation mode have an amplitude approximately equal to the voltage difference between supply lines 3 and 4, and each pulse applied to the base of transistor TR3 has an amplitude approximately equal to the voltage difference between supply lines 3 and 4. Amplitude level is diode D
5 and diode 02. The series circuit of D3.D4 and associated resistors 306 and 307 connect each separate diode D2. It is clamped to a reference level determined by the characteristics of D3 and D4. Preferably, diodes D2.03 and D4 are of the same type. transistor T
The voltage at the base of R3 becomes zero when the oscillating voltage at point P becomes negative with respect to the supply line 4 and the output of the voltage comparator 9 goes to a "low" level.
The voltage at the base of R3 increases across the diodes D2, D3 and D4 when the oscillating voltage at point P becomes positive with respect to supply line 4 and the output of comparator 9 goes to a high level.
clamped to a reference level determined by the characteristics of For example, if the junction voltage of each of diodes D2.03 and D4 is 0.6 volts, then the reference level to which the voltage at the base of transistor TR3 is clamped during the "high" level of the output of voltage comparator 9 is 1 .8 volts.

The base electrode of transistor TR4 is connected to the output terminal of inverter 301. Therefore, when the oscillator is in standby mode, the ``low'' level voltage present at the output terminal of in-hark 301 is applied to the base of transistor TR4, which turns off and also turns off transistors TR2 and TR3.

On the other hand, when the oscillator of FIG. 3 is in the oscillation mode, the high level voltage supplied from the output terminal of the inverter 301 to the base of the transistor TR4 drives the transistor TR4 into saturation, thereby driving the emitter-collector path of the transistor TR4. However, transistors TR2 and T
Depending on the respective separate voltage applied to the base electrode of R3, it is distributed between the respective collector-emitter paths of these transistors TR2 and TR3.

When the oscillator of Fig. 3 is in oscillation mode, the transistor T
The base-emitter current of RI and hence transistor TR
The collector emitter current of I is determined by the magnitude of the collector emitter current of transistor TR3. When the output of the voltage comparator 9 becomes a "low" level and therefore the potential of the base electrode of the transistor TR3 also becomes a "low" level,
Of course, the transistor TR3 becomes non-conductive. However, every time the output of the voltage comparator 9 goes to the "high" level,
Transistor TR3 conducts and the magnitude of the collector-emitter current is determined by the voltage difference between the base voltages of transistors TR2 and TR3. The base voltage of transistor TR3 is at the aforementioned reference level during the relevant period, while the base voltage of transistor TR2 is at the resonant circuit T.
At a voltage corresponding to the instantaneous peak-to-peak level of the oscillating voltage across C, the magnitude of the pulse of collector-emitter current produced by transistor TR3 each time the output of voltage comparator 9 goes to a high level, and hence the transistor The magnitude of the pulse of current delivered through the emitter-collector path of TRI is inversely related to the peak-to-peak level of the oscillating voltage across the tuned resonant circuit TC.

An increase in the peak-to-peak level of the oscillating voltage at point P reduces the energy supplied to the resonant circuit TC via the transistor TRI, and a drop in the peak-to-peak level of said oscillating voltage increases said energy. Therefore, the peak-to-peak level of the oscillating voltage is stabilized at a particular level determined by the parameters of the circuit arrangement, and at this particular level the pulse of current delivered through the transistor TRI is of a magnitude that exactly compensates for the circuit losses.

Since transistor TR4 is cut off when the oscillator of FIG. 3 is in standby mode, the charge present across capacitor 304 at the instant of transition from oscillation mode to standby mode is retained for a considerable period of time, and therefore cannot be switched off to oscillation mode later. Upon switching, the charge present across capacitor 304 is stabilized at the same level as before. Such a configuration is advantageous for application to a vehicle detection device in which a plurality of oscillators operating in standby mode are repeatedly and sequentially switched to oscillation mode within a short period of time.

In the oscillator of FIG. 4, parts similar to those of the oscillator of FIG. 1 are given the same reference numerals as in FIG. The oscillator of FIG. 4 uses a combination of a mode selection switch MS, a D-flip-flop FF, and an inverter 401 interconnected as shown in FIG. 4 in place of the switch S of FIG. It is almost the same as the oscillator shown in the figure.

Mode selection switch MS is a two position switch.

When the switch MS is in position P1, the standby mode is selected and the common terminal 402 is connected to the negative feed line 4, while when the switch MS is in position P2, the oscillation mode is selected and the common terminal 402 is connected to the positive feed line 4. Connected to 3.

The data input terminal of the D-flip-flop FF is connected to the common terminal 402 of the switch MS, and the inverter 4
It is also connected to the set input terminal S of the flip-flop FF through 01. The clear input terminal C of the flip-flop PF is connected to the interconnection point of a resistor 403 and a capacitor 404 connected in series between the voltage supply lines 3 and 4. The clock input terminal CLK of the flip-flop FF is connected to the output terminal of the voltage comparator 9, and the Q output terminal Q of the flip-flop FP is connected to the end of the resistor 7 on the side opposite to the pace side of the transistor TRI.

When the output terminal Q of the flip-flop FP goes to low level, the oscillator operates in standby mode, so the transistor TRI conducts and the charging current flows through the transistor TR.
It flows through the emitter-collector path of I and through the inductance (inductor) 1, and the output terminal Q is ``high''.
level, the oscillator operates in oscillation mode and the output of the voltage comparator 9 therefore alternates between low and low as the voltage present at point P oscillates repeatedly positive and negative with respect to the negative supply line 4.
and ``high'' level, which makes the transistor TRI conductive whenever the output of the voltage comparator 9 goes to a low level, so that a current pulse is supplied through the emitter-collector path of the transistor TRI, thereby supplying energy to the resonant circuit. and maintain the oscillation.

The D-flip-flop FF has a clock input terminal CLK.
The data present at the data input terminal is transmitted to the output terminal Q at the positive edge of the pulse applied to the output terminal Q. Furthermore, whenever the set terminal S goes to the "low" level, the output at the output terminal Q is set to the "high" level, regardless of the state of the clock input terminal CLK or the data input terminal, while the clear terminal C goes to the "high" level. Each time a "low" level is reached, the output at output terminal Q is cleared to a "low" level. Flip-flop FF may be, by way of example, one of the flip-flops included in Symknetics Model No. 74LS74.

The operation of the switching circuit provided in the oscillator of FIG. 4 is as follows. When the supply voltage is applied to the circuit,
Since it takes time for the capacitor 404 to become fully charged, the clear terminal C of the flip-flop FF is held at the 'low' level for a sufficiently long time, and the flip-flop FF is 'cleared'. Therefore, the output terminal Q is at the ``low'' level. Capacitor 404 is then rapidly charged towards the supply potential via resistor 403, and capacitor 404 and resistor 403 are charged until the supply voltage is removed and capacitor 404 is discharged and ready for the next application of supply voltage. It serves no function. The mote selection switch MS must initially be in position P1, in which the terminal 402 is at the ``low'' level and the output terminal of the inverter 401 is therefore at the ``high'' level, causing the output of the flip-flop FF to be at the ``high'' level. Does not affect the condition. Since the output terminal Q is at the "low" level,
The oscillator is operating in standby mode as described above.

By switching the mode selection switch MS to position P2, the terminal 402 goes to the "high" level, the old output terminal of the inverter 4 and the set input terminal S of the flip-flop FF go to the "low" level, which causes the output terminal Q to go to the "high" level.
Set to level state.

When the output terminal Q goes to the 'high' level state, the oscillator operates in the oscillation mode as described above.The oscillator of FIG.
The design must be such that the magnitude of the circulating current in the resonant circuit TC when the oscillator is in oscillation mode is equal to the magnitude of the charging current supplied to the inductance 1 when the oscillator is in standby mode. be.

When the oscillator of FIG. 4 is in oscillation mode and switch MS is in position P2, the positive-going edge of the clock pulse is transferred from the output terminal of voltage comparator 9 to the clock input terminal CLK for each negative half-cycle of oscillation. The data present at the input terminal of the seven lip-flop FP at the said edge of each clock pulse is transmitted to the output terminal Q. switch ms
is at position P2, terminal 402 and the input terminal are at the "high" level. Therefore, switch MS is at position P2.
, the output terminal Q remains at a high power level and the oscillator continues to operate in oscillation mode.

When the mode selection switch MS is returned to position P1 and the oscillation mode of the oscillator is terminated, the terminal 402 goes to a "low" level, and therefore passes through the impark 401 to the set terminal S.
is set to the "high" level. This removal of the set signal from the set terminal S does not change the state of the output terminal Q. Since the output terminal Q is at the "high" level, the oscillator is set to the next positive direction. The oscillation mode is maintained until a pulse is generated by the voltage comparator 9 and the output terminal of the flip-flop FF goes to a ``low'' level.

Each positive-going edge in the waveform supplied by the voltage comparator 9 to the clock terminal CLK occurs at the instant of crossing from the positive to the negative of the oscillator voltage present at point P. At such moments,
The amplitude of the oscillating circulating current flowing through the resonant circuit TC becomes maximum. That is, the current flows through the inductance 1 at its maximum value. The voltage at the output terminal Q is "high" at the first mentioned instant after the mode selection switch MS returns to position P1.
Since the transistor T changes from level to low level,
RI switches to conductive state, so that a current approximately equal to and opposite to the magnitude of the circulating current flows through the inductance 1
is supplied to almost terminate the oscillation of the resonant circuit, after which charging current is supplied via the emitter-collector path of the transistor TRI until the next switching of the mode selection switch MS.

The oscillator in Figure 4 changes from standby mode to oscillation mode,
Next, the state of switching to standby mode again will be explained using waveform diagrams shown in FIGS. 5a to 58. FIG. 5a shows the common terminal 402.
5b shows the voltage present at point P, FIG. 5c shows the voltage at the output terminal of voltage comparator 9, and FIG. 5d shows the voltage at the output terminal Q of flip-flop FF.
Figure 5e shows the current level supplied to the inductance 1 via the emitter-collector path of the transistor TRI.

Before the instant T1, the oscillator is in standby mode and a relatively large charging current is supplied to the inductance 1 via the transistor TRI, as shown by the current level in FIG. 5e. At instant T1, the switching of the mode selection switch MS from the standby mode position P1 to the oscillation mode position P2 takes place, and the terminal 402 goes to the "high" level voltage, which causes the transition as described above and as shown in FIG. 5d. The output terminal Q of the flip-flop FF is brought to a "high" level, blocking the flow of current through the emitter-collector path of the transistor TRI and starting the oscillation.At the moment when the oscillator is in the oscillation mode, the voltage at the point P increases between TI and 13. follows an approximately sinusoidal waveform as shown in the waveform of Fig. 5b,
The output of voltage comparator 9 is alternately switched between ``high'' and ``low'' levels as shown in the waveform of FIG. 5C, thereby delivering current pulses through transistor TRI and imparting energy to tuned resonant circuit TC. . The magnitude of this current pulse is significantly smaller than the magnitude of the charging current as shown by the waveform of Figure 5e.

At instant T2, as shown in FIG. 5a, the mode selection switch MS is returned to the sfin-by mode position Pi, so that the voltage at terminal 402 goes to the low level. However, the output terminal O of the flip-flop FF is at the instant T3 coincident with the leading edge of the next positive-going pulse at the output terminal of the voltage comparator 9, as shown in the waveforms of Figures 50 and 5d.
When the voltage at the output terminal Q goes to the "low" level, the transistor TRI is switched into conduction, the flow of charging current through the emitter-collector path of the transistor TRI is restored, and at the same time the oscillation is stopped. death,
The oscillator's oscillation mode is terminated and standby mode is restored.

[Brief explanation of the drawing]

1 is a circuit diagram showing an example of an oscillator according to the invention; FIGS. 2a, 2b and 20 are diagrams showing waveforms occurring at various points in the first circuit; and FIG. FIG. 4 is a circuit diagram showing still another example of the oscillator of the present invention incorporating control delay means; 5a, 5b, 5c, 5d, and 5c The figure shows the fourth
FIG. 3 is a diagram illustrating waveforms associated with operation of the illustrated circuit. 1... Inductance (inductor) 2... Capacitance (capacitor) 3.4... Power supply line 5, 6.7.8.12.13... Resistance 9... Voltage comparator 301.401. ...Inverters 303, 305
~313...Resistor 304...Capacitor

Claims (1)

[Claims] 1. An oscillator comprising a power source that generates a nearly constant current and includes a control element capable of controlling the magnitude of this current, a tuned resonant circuit, and a switching means, the oscillator as described above. The switching means is for switching the operating mode of the oscillator from a standby mode to an oscillation mode and vice versa by switching the control element from one operating mode to another, and during the standby mode, the switching means is adapted to switch the operating mode of the oscillator from a standby mode to an oscillation mode and vice versa. When charging power is supplied to the inductor of the tuned resonant circuit and the mode shifts from standby mode to oscillation mode, the supply of charging current appears to be interrupted, and control is established between the resonant circuit and the control element. A loop is provided which supplies a control voltage to the control element that is dependent on the voltage across the tuned resonant circuit, thereby increasing every other half of the oscillation voltage developed across the tuned resonant circuit during the oscillation mode. An oscillator characterized in that it supplies pulses of current from a power source to a tuned resonant circuit in cycles. 2. The oscillator according to claim 1, wherein the control loop performs a keying operation on the control element in synchronization with every other half cycle of the oscillation voltage generated across the tuned resonant circuit. 1. An oscillator comprising: a keying signal generator connected to cause a keying signal to be generated; 3. The oscillator according to claim 2, further comprising an amplitude stabilizing means responsive to the peak-to-peak amplitude of the oscillation voltage across the tuned resonant circuit, whereby the keying signal is generated. The control element is keyed such that the amplitude of the keying pulses generated by the oscillator is controlled so that the amplitude of the keying pulses changes inversely to the peak-to-peak amplitude variation of the oscillating voltage. oscillator. 4. An oscillator according to claim 2, in which a differential amplifier is associated with said control loop, said differential amplifier having a first input terminal connected to said keying signal generator; a second input terminal connected to monitor the oscillation voltage across the tuned resonant circuit, and an output terminal of the differential amplifier connected to supply a keying pulse to the control element. and the differential amplifier is operative to produce a key ink pulse having a magnitude dependent on the difference between the peak-to-peak voltage of the oscillating voltage across the tuned resonant circuit and the reference voltage. An oscillator characterized by: 5. An oscillator as claimed in claim 1 or 2, wherein the switching means is arranged to detect a selected mode of operation by controlling the voltage present across the first input terminal connected to detect the selected mode of operation and the tuned resonant circuit. a second input terminal connected to monitor the control delay means;
This control delay means is activated when the standby mode is selected and, when the oscillator is in the oscillation mode, delays the transition to the standby mode and the supply of charging current to the inductor of the tuned resonant circuit. An oscillator characterized in that the flow of current in the inductor due to the current is delayed until it reaches approximately a maximum in the direction opposite to the flow of charging current.