JPS60213180A - Detecting circuit of signal tuning - Google Patents

Abstract

PURPOSE:To reduce the number of parts and to constitute an IC easily by providing the titled circuit with an input circuit for comparing a vertically synchronizing separation signal with a threshold to be switched in accordance with the output of signal presence or absence detection, an oscillated pulse counting circuit and a signal presence or absence detection output circuit. CONSTITUTION:A vertical synchronizing separation signal 3 is transmitted to a differential amplifier 19 through an integrating circuit 18 and compared with a threshold voltage 24 determined by resistors 20-22 and a Tr23 and its output 25 is supplied to the set input of an S-RFF26 with a clear terminal and clear terminals of TFFs 27, 28 through a Tr36. The TFFs 27, 28 constitute binary counting circuits, a vertical oscillation pulse 8 is inputted to the input of the 1st FF27 and its output 29 is connected to the input of the succeeding FF28. The outputs 29, 30 of the FFs 27, 28 are AND-processed by an AND gate 31 and its output 32 is inputted to the clear terminal of an FF26. The output 17 of the FF26 is a tuning detection output.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal tuning detection circuit used in a tuning section of a television receiver.

Conventional configuration and its problems In a tuning device using an electronic tuner, when a certain tuning voltage is applied to the tuner, it is often necessary to detect whether or not the tuner is tuned to a desired television signal.

There are several types of signal tuning detection circuits.

FIG. 1 shows an example of a conventional example. A composite synchronization separation signal 3 is separated from the composite video signal 1 by a synchronization signal separation circuit 2 . Furthermore, the horizontal oscillation pulses 7,
Vertical oscillation pulse 8 is obtained.

These are essentially pulses used for deflection.

9 is a tuning signal detection section.

The synthesized synchronized separated signal 3 and the horizontal oscillation pulse 7 are each input to an integrating circuit 10. It is processed by the differentiating circuit 11, further waveform shaped by the waveform shaping circuits 12 and 13, and the AND of both outputs is processed by the gate 1.
4, and further integrate the output with an integrating circuit 15,
Tuning is determined based on the integrated voltage value. The tuning detection output signal 17 is passed through a Schmitt circuit 16 so that the determination result is not affected by vertical period ripples. In this case, it is detected that K is disturbed when the horizontal synchronization signal 3 is not synchronized with the television signal.

K in order to compare only the horizontal synchronization signal part.

At the end of the horizontal synchronization pulse, extract the horizontal synchronization signal 3.

However, in the horizontal synchronization signal 3 and the horizontal synchronization pulse 7, the separation circuit 4. The latter is delayed in phase due to the presence of the horizontal oscillation circuit 6. Therefore, there is an inconvenience that correction by the integrating circuit 1o and the differentiating circuit 11 is necessary for the correction. In particular, when converting the annual bond circuit into an IC, the phase correction circuits 10 and 11 and the integral simultaneous constant circuit 18 become parts outside the IC.

This causes disadvantages such as an increase in the number of parts and an increase in the number of IC bins.

OBJECT OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, has a small number of parts, and an IC.
It is an object of the present invention to provide a signal tuning detection circuit which is easy to implement and whose response method rf for tuning determination has characteristics equivalent to those of the conventional example.

Structure of the Invention The present invention includes an input circuit that compares a vertical synchronization separation signal with a threshold value that is switched in response to the output of a signal presence/absence detection, and a vertical oscillation pulse that is counted and reset if there is a signal from the input circuit. It is set by a signal from a counting circuit and the above-mentioned input circuit, and the count value of the above-mentioned counting circuit exceeds a certain value.
This signal tuning detection circuit for a television receiver consists of a signal presence/absence detection output circuit that is reset when .

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

In FIG. 2, the same parts as in FIG. 1 have the same numbers as in FIG.

The synchronous separation signal 3 is transmitted to the differential amplifier 19 via the integrating circuit 18. It is compared with a predetermined threshold voltage 24 determined by the states of the resistors 20 to 22 and the transistor 23, and the output 25 is outputted via the transistor 36 with a clear terminal S.
- is supplied to the set input of the R flip-flop 26 and the clear terminal of the T flip-flop 27.28.

These T flip-flops 27 and 28 constitute a binary counting circuit, and the vertical oscillation pulse 8 is input to the input of the first stage 2, and its output 29H is the flip-flop of the next stage.
Connected to the input of flop 28. The outputs 29,30 of the flip flops 27,28 are connected to the AND gate 31.
The AND output 32 is input to the clear terminal of the flip-flop 26. In addition, flip
The reset terminal of No. 1J knob 26 is grounded. The output 17 of flip-flop 26 is the tuning detection output.

The inverted output 33 of the flip-flop 26 is also supplied to the base of the transistor 23, the collector of which is connected to the resistor 2.
It is connected between 1 and 22.

The following table shows the input/output relationship of flip-flops. (Hereinafter referred to as gold and white) Set reset flip 0T with 0 clear terminal Flip-flops 27 and 28 (hereinafter abbreviated as T-F and F). ) Next, the input circuit section 37. Output circuit section 38.
The operation of each block of the counting circuit section 39 will be explained.

First, the input circuit section 37 will be described. Synchronous separation signal 3
is integrated by the integrating circuit 18, and a vertical synchronizing signal is input to the base of the transistor 34.

The waveforms of each part will be explained with reference to FIG. Waveform & is an example of a vertical synchronization signal input to the base of the transistor 34. The synchronization signal has negative polarity.

The period is a vertical period V.

In the figure, V□ indicated by a broken line is the base potential of the transistor 35. Waveform A is the output 25 corresponding to waveform a. That is, during a period in which the base potential of the transistor 34 is lower than the base potential of the transistor 36, the transistor 34
is on, the transistor 36 is off, the transistor 36 is off, and the output 26 of the input circuit section 37 becomes H#.

V□ in waveform a, that is, the threshold voltage 24 is the resistance 20
It is determined by the division ratio of ~22. However, it is switched depending on whether the transistor 23 is on or off.

Next, the output circuit section 38 will be explained. This is 5-R-F, F, which operates in the input/output relationship described above.

It is 26.

Waveform C in FIG. 3 is the initial state S-R-F, F, 26
When the output 17 is 'L' and the clear manual power 32 is 'L', S when the waveform is input to the set input terminal S
-R-F, F, 26 output 17 waveforms.

In other words, the first pulse S to the set input terminal S
Due to HI, the output 17 of S -R-F, 7.26 becomes 'L
Changes from # to 'H', then set manpower 25 becomes L'
Even if it becomes H', the output 17 will be 'H'.
Retained. This output 17 changes to 'L' only when the clearing human power 32 becomes 'H'.

Next, the counting circuit section 39 will be explained with reference to FIG. 7. In the initial state, each T・F, F,
27, 28 clear human power 25 is %LI, output 29.3
0 closed with ゞL#. Input 8 of first stage F, F2 end is waveform d
The vertical oscillation pulse is as follows.

With an input of period V, at the falling edge, T・F, F
, 27 change. Output 29 of T, F, F, 27
is the waveform e. Furthermore, with waveform e as input, T −F
The output 30 of , F, 28 is 5 A varying as the waveform f.
The output 32 obtained by calculating the logical product in the ND gate 31 has a waveform g, which is a pulse waveform with a cycle of 4V and a duty of 1/4.

The overall operation will be explained here. As the vertical synchronization signal (base input of the transistor 34) receives TV radio waves with a stronger electric field, the threshold potential 24 (v in waveform a in FIG. 3) increases.
This is based on the premise that the potential is lower than that in A).

First, the operation when shifting from a non-receiving state to tuning will be explained with reference to FIG. Waveform 1 is vertical oscillation pulse 8, waveform 1 is output 26 of input circuit section 37, waveform 3 is T
, F, F, 27 output 29° waveform has T-F, F, 28
Output 30. The C input 32 of the waveforms tI'1s-R-F, F, 2e and the waveform m correspond to four tuning detection outputs 17, respectively.

Time t. Previously no signal was received and input IJ+-H
The output 25 of the l path section 3 is 'L'0f-i. During this time, as explained in FIG. 1 pulse is input. During the 'H' part of this pulse, the output 17 becomes 'L' and is maintained. This is why the waveform m is L' at time t. .

Now, time t. It is assumed that the receiving state has already been reached and pulses have started to be output from the output 26 of the input circuit section 3. The clear terminal C of T-F, F, 27.28 of the counting circuit section 39 is '
When it becomes H', both outputs 29 and 30 become 'L'...
The clear terminal C of 5-R-F, F, and 26 becomes L'. At this time, 5-R-F.

Since the set input 26 of F, 26 is H', the tuning detection output 17 changes from L' to H'.

This is the waveform m at time t. Smell 1, $L# to H'
This is the reason for the change.

After this, the output remains at 1.gamma.-H' unless the clear terminal 32 becomes 'H#' as explained in FIG.

The clear terminal 32 becomes %HI at T-F and F.

This is the case when the outputs 29 and 28 of 2 and 28 are both 5H', but as can be seen from Fig. 4, once T・F, F, 27
, 28 outputs 29.30 are both 5L', unless the vertical oscillation pulse 8 falls three times, 5-R-F,
The clear terminal 32 of F, 26 does not become 'H'. However, during reception, T −F, F, 27,
28 is cleared by the output 25 of the input circuit section 37, so depending on the phase relationship between the output 26 of the input circuit section 37 and the waveform of the vertical oscillation pulse 8, time 1. , 12, the output 29 of T, F, F, 27 may become H#, but the clear terminal 32 of S-R function F, F, 26 does not become H', and in the end, Tuning detection output 17 is 'H
' remains. Here, waveform m is at time t.

This is the reason why it has remained at H' ever since.

Next, the transition from the tuned state to the untuned state will be explained with reference to FIG. 6. In FIG. 6, the waveform names are the same as those in FIG. As shown in waveform 1 at time t3, there is no synchronization after t3.

At this time, the first counting circuit section 39 starts counting from the falling edge of the waveform at time t4.

Then, at time t5, the waveform t becomes 'H#, and 5-R-F
, F, the output 1 of 26 is converted to %L#.

That is, at time t5, the out-of-synchronization detection output state is entered.

Note that there is a period of 3V from time t3 to time 5, which is necessary in the sense that the determination output 17 does not react sensitively if the synchronization signal is disturbed for a while during reception.

This period can be varied depending on the configuration of the counting circuit section 39.

In the conventional example, the integral time constant circuit 18 shown in FIG. 1 was adjusted.

In order to stabilize the above operation, the threshold potential 24 of the input circuit section 37, that is, the base potential of the transistor 36, is switched by the inverted output 33 of the S-R, F, F, 26. This will be explained with reference to FIG. When transitioning from an unsynchronized state to a synchronized state, the vertical synchronization signal has a waveform of
The threshold potential is waveform B. The threshold potential B is the low potential v0 until time t5. In FIG. 2, the tuning detection output 17 is IL',
The inverted output 33 is H#, the transistor 23 is on, and the base potential of the transistor 24 is approximately equal to that of the resistor 20 and 2.
This corresponds to the case determined by the ratio of 1. Since the threshold potential is low, time 15,1. Then, the output 25 of the input circuit section 37 is ゞL'. It crosses the threshold potential for the first time at time t5, and the fifth
As explained in the figure, the tuning detection output 17 immediately becomes H'. At this time.

The inverted output 33 is ``t,?'', and the transistor 23 is off, so the threshold voltage 24 is the ratio of the sum of the resistors 2o and 21.degree.22, and is a potential VB higher than the previous threshold value v0.

That is, once the tuning state is entered, even if the vertical synchronization signal is slightly disturbed, pulses are stably output from the output 25 of the input circuit section 37, and the tuning state detection output 17 is stable. This has an effect equivalent to the output stage Schmitt circuit (16 in FIG. 1) in the conventional example.

How much strong electric field change should be used to determine tuning?

It is basically determined by the resistors 20 to 22, and can be finely adjusted by the time constant of the integrating circuit 18. Also, the disturbance of the synchronization signal during reception J1. How long should the tuning output be maintained for 1. ? i
Gunbe 39 has been set up several times. The response speed of transition from the non-tuned state to the tuned state is determined by the time constant of the integrating circuit 18.

As this time constant is made smaller, the response speed becomes faster.

Vertical synchronization pulse and vertical synchronization signal pulse width 2 phase 2
Since the difference in period does not pose a problem in this circuit, the correction circuits 10 and 11 as in the conventional circuit 1 are unnecessary.

The integration circuit 18 is located at the signal input section, and the number of IC pins is reduced when integrated into an IC, compared to the conventional case where the integration circuit 18 is provided during processing. That is, in the conventional example, the inputs are 3 and 7, and the integrating circuit 18. While four outputs 17 are required, in this example, the number of inputs can be reduced by one pin to three: the base of the transistor 34, the input of the 8 vertical oscillation terminals, and the output 1.

Effects of the Invention As shown in L, the signal tuning detection circuit of the present invention achieves 1.
;, The degree of freedom of the input signal is large (, the phase and pulse width correction circuits that were conventionally required are no longer required.

Further, since the output holding period for synchronization disturbance during reception and the response speed for transition from the out-of-sync state to the in-sync state can be set separately, design is easy. Furthermore, it has the advantage of having a configuration that can be easily integrated into an IC.

[Brief explanation of drawings]

Figure 1 is a block diagram of a signal tuning detection circuit in a conventional example, Figure 2 is a circuit diagram of a signal tuning detection circuit in an embodiment of the present invention, and Figure 3 is for explaining the operation of the input circuit section in Figure 2. FIG. 4 is a waveform diagram for explaining the operation of the counting circuit section in FIG. FIG. 7 is an explanatory diagram of operating waveforms at the time of transition from to an untuned state, and FIG. 7 is an explanatory diagram of operating waveforms when switching the threshold value of the input circuit section. 3...Synchronization separation signal, 8...Vertical oscillation pulse, 17
・・Tuning detection output, 19 ・・Differential amplifier, 23 ・
・Threshold voltage switching transistor, set with 26 clear terminals - reset flip・) vJ. 17. 27, 28 ・Clear terminal bone T・Flip board, 31 ・AND gate, 37...Input circuit section, 38. .Output circuit section, 39...Counting circuit section. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 L - J Figure 3 Figure 4 Figure 5 Figure A 6

Claims (1)

[Claims] (1) An input circuit that outputs a signal during a period in which the vertical synchronization separation signal exceeds a predetermined threshold value, and a vertical oscillation pulse,
A counting circuit outputs a signal from the input circuit to return a certain count value to the initial state, and the first signal output from the input circuit generates an output indicating the tuned state, and the count value of the counting circuit is further adjusted to a predetermined state. A signal tuning detection circuit comprising: an output circuit that generates an output indicating an out-of-tuning state when the signal exceeds a threshold value, and the threshold value of the input circuit is switched in accordance with the output of the output circuit. . 2)) The input circuit has a comparator circuit configuration using a differential amplifier, the reference comparison voltage is variable by the DC voltage of the tuned state output, and the synchronous separation signal is integrated and input to the input terminal. A plurality of T flip-flops with clear terminals are connected in series, a vertical oscillation pulse is input to the input terminal of the first T flip-flop, and the output of the above input circuit is input to each clear terminal. The circuit consists of a set-reset flip-flop with a clear terminal.The seventh terminal is grounded, the set terminal is connected to the output end of the above input circuit, and the clear terminal is a combination of the outputs of each flip-flop of the above counting circuit. 2. The signal tuning detection circuit according to claim 1, wherein the signal is inputted through the circuit and the output of said set-reset flip-flop is used as a tuning detection output.